Re: [PATCH 2/2] MIPS: Hard-float rounding instructions support

["Junxian Zhu" <zhujunxian@oss.cipunited.com>]

在 2023/12/27 6:50, Xi Ruoyao 写道:
> On Wed, 2023-12-27 at 05:50 +0800, Xi Ruoyao wrote:
>> On Tue, 2023-12-26 at 17:12 -0300, Adhemerval Zanella Netto wrote:
>>> Also, I see no point in implementing this optimizations with assembly where
>>> a C implementation would be way simpler and generate similar code. Similar
>>> to what I did for powerpc with sysdeps/powerpc/fpu/round_to_integer.h, I
>>> implemented a similar approach for MIPS [1].  The resulting code should be
>>> similar to the assembly implementation, taking in consideration the correct
>>> fix to save/restore floating-point exceptions. I did see no math regression
>>> on cfarm23 with a glibc built with -mabi=64 -mips64r2.
>> Is there a micro-benchmark result on the cfarm machine?  AFAIK the FCSR
>> setting instruction may be much more slower than normal instructions, so
>> I'm not sure if this is really a win.
> Add Jiaxun who knows MIPS much better than me.

After disscussion with Jiaxun, we guess that the consuming of switching 
mode in FCSR is the cause of FPU implements slower than generic 
implements. If we don't change or switching mode in FCSR, the FPU 
implements will be faster than generic implements. Tested on Imagination 
Ci40 (MIPS interAptiv (multi) V2.0  FPU V0.0)and loogson 3A2000.

So it's enough to use generic C implements for rounding on MIPS.......