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* [PATCH]
@ 2009-04-02  4:56 Peter Bergner
  2009-04-02  5:05 ` [PATCH] Fix up -Many handling PowerPC (was: [PATCH]) Peter Bergner
  2009-04-02  7:01 ` [PATCH] Alan Modra
  0 siblings, 2 replies; 13+ messages in thread
From: Peter Bergner @ 2009-04-02  4:56 UTC (permalink / raw)
  To: binutils; +Cc: Alan Modra, Jan Kratochvil, Thiago Jung Bauermann

Jan came across a few problems in the GDB testsuite where the GDB disassembly
of gas/testsuite/gas/ppc/power7.s which uses -Many, didn't match up with what
objdump outputs using -Mpower7.  This patch attempts to modify the -Many
handling such that for a large range of processors, the -Many and -M<cpu>
outputs are the same (eg, power7, power6, power5, power4, 970, cell, etc.).

The major change here is that we now only choose a default dialect when
the user fails to pass any -M... options.  We used to choose it when they
passed -Many, but that ended up preferencing some older opcode forms over
newer forms.  For example:

    $ ./gas/as-new -o power7.o -mpower7 ./gas/testsuite/gas/ppc/power7.s
    $ ./binutils/objdump -d -Many power7.o >d-any
    $ ./binutils/objdump -d -Mpower7 power7.o >d-power7
    $ diff -u d-any d-power7
    -  98:  7d 5c 02 a6     mfspr   r10,28
    +  98:  7d 5c 02 a6     mfcfar  r10
    -  9c:  7d 7c 03 a6     mtspr   28,r11
    +  9c:  7d 7c 03 a6     mtcfar  r11
    - 14c:  7e 08 4a 2c     dcbt    16,r8,r9
    + 14c:  7e 08 4a 2c     dcbtt   r8,r9
    - 150:  7e 08 49 ec     dcbtst  16,r8,r9
    + 150:  7e 08 49 ec     dcbtstt r8,r9

By not choosing a default dialect for -Many, we allow the order of the
opcode table to determine which opcode forms have priority.

One "feature" that exists currently and continues to exist even with this
patch, is that if the user types -Many -M<cpu>, then we will first attempt
to disassemble an instruction using -M<cpu> before falling back to -Many.
However, the way the current deprecation of instructions works, we will
never disassemble an instruction that is deprecated for <cpu> even if it
occurs earlier in the opcode table than another instruction form that
matches.  Is this what we want?  It kind of makes sense to me that we
do, since if we pass -Many -M<cpu>, we first try disassembling using
-M<cpu> before falling back to -Many, so it seems to me we're allowing
the user to preference -M<cpu> over everything else, which would seem
to imply they also don't want instructions deprecated by -M<cpu>.
Anyone have an opinion?

The dialect_orig change below was to handle the case when we're handling
-Many (ie, 2nd time through the opcode table) and we've set the dialect
to ~PPC_OPCODE_ANY.  If we continued to use "dialect" in the:

	|| (opcode->deprecated & dialect_orig) != 0)

rather than dialect_orig, any instruction that is deprecated for any
cpu value, will never be matched.

This has passed build and make check, ok for mainline assuming the above
mentioned "feature" is how we want the code to behave?

Peter


opcodes/

	* ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect
	due to -many/-Many.
	(print_insn_powerpc): Make sure we only deprecate instructions using
	the original dialect and not a modified dialect due to -Many handling.
	Move the handling of the condition register and default operands to
	the end of the if/else if/else chain.
	* ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
	instructions from newer processors are listed before older ones.
	<"icblce", "sync", "eieio", "tlbld">: Deprecate for processors
	that have instructions with conflicting opcodes.

Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.39
diff -u -p -r1.39 ppc-dis.c
--- opcodes/ppc-dis.c	10 Mar 2009 06:53:45 -0000	1.39
+++ opcodes/ppc-dis.c	2 Apr 2009 03:57:22 -0000
@@ -226,15 +226,12 @@ powerpc_init_dialect (struct disassemble
       arg = end;
     }
 
-  if ((dialect & ~(PPC_OPCODE_ANY | PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
+  if ((dialect & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
     {
-      if ((dialect & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
-	{
-	  if (info->mach == bfd_mach_ppc64)
-	    dialect |= PPC_OPCODE_64;
-	  else
-	    dialect |= PPC_OPCODE_32;
-	}
+      if (info->mach == bfd_mach_ppc64)
+	dialect |= PPC_OPCODE_64;
+      else
+	dialect |= PPC_OPCODE_32;
       /* Choose a reasonable default.  */
       dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_CLASSIC
 		  | PPC_OPCODE_601 | PPC_OPCODE_ALTIVEC);
@@ -338,6 +335,7 @@ print_insn_powerpc (bfd_vma memaddr,
   const struct powerpc_opcode *opcode;
   const struct powerpc_opcode *opcode_end;
   unsigned long op;
+  ppc_cpu_t dialect_orig = dialect;
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status != 0)
@@ -376,7 +374,7 @@ print_insn_powerpc (bfd_vma memaddr,
 
       if ((insn & opcode->mask) != opcode->opcode
 	  || (opcode->flags & dialect) == 0
-	  || (opcode->deprecated & dialect) != 0)
+	  || (opcode->deprecated & dialect_orig) != 0)
 	continue;
 
       /* Make two passes over the operands.  First see if any of them
@@ -447,16 +445,14 @@ print_insn_powerpc (bfd_vma memaddr,
 	    (*info->print_address_func) (memaddr + value, info);
 	  else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 	    (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
-	  else if ((operand->flags & PPC_OPERAND_CR) == 0
-		   || (dialect & PPC_OPCODE_PPC) == 0)
-	    (*info->fprintf_func) (info->stream, "%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_FSL) != 0) 
 	    (*info->fprintf_func) (info->stream, "fsl%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 	    (*info->fprintf_func) (info->stream, "fcr%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 	    (*info->fprintf_func) (info->stream, "%ld", value);
-	  else
+	  else if ((operand->flags & PPC_OPERAND_CR) != 0
+		   && (dialect & PPC_OPCODE_PPC) != 0)
 	    {
 	      if (operand->bitm == 7)
 		(*info->fprintf_func) (info->stream, "cr%ld", value);
@@ -473,6 +469,8 @@ print_insn_powerpc (bfd_vma memaddr,
 		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 		}
 	    }
+	  else
+	    (*info->fprintf_func) (info->stream, "%ld", value);
 
 	  if (need_paren)
 	    {
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.119
diff -u -p -r1.119 ppc-opc.c
--- opcodes/ppc-opc.c	2 Apr 2009 00:42:29 -0000	1.119
+++ opcodes/ppc-opc.c	2 Apr 2009 03:57:22 -0000
@@ -3464,8 +3464,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"isellt",	X(31,15),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
 
-{"mfcr",	XFXM(31,19,0,0), XRARB_MASK, COM,	POWER4,		{RT}},
 {"mfcr",	XFXM(31,19,0,0), XFXFXM_MASK, POWER4,	PPCNONE,	{RT, FXM4}},
+{"mfcr",	XFXM(31,19,0,0), XRARB_MASK, COM,	POWER4,		{RT}},
 {"mfocrf",	XFXM(31,19,0,1), XFXFXM_MASK, COM,	PPCNONE,	{RT, FXM}},
 
 {"lwarx",	X(31,20),	XEH_MASK,    PPC,	PPCNONE,	{RT, RA0, RB, EH}},
@@ -3726,14 +3726,14 @@ const struct powerpc_opcode powerpc_opco
 {"mullw.",	XO(31,235,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
 {"muls.",	XO(31,235,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
+{"icblce",	X(31,238),	X_MASK,      PPCCHLK,	E500MC,		{CT, RA, RB}},
 {"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC,	PPCNONE,	{RB}},
-{"icblce",	X(31,238),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
 {"mtsrin",	X(31,242),	XRA_MASK,    PPC32,	PPCNONE,	{RS, RB}},
 {"mtsri",	X(31,242),	XRA_MASK,    POWER32,	PPCNONE,	{RS, RB}},
 
 {"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
-{"dcbtst",	X(31,246),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
 {"dcbtst",	X(31,246),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
+{"dcbtst",	X(31,246),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
 
 {"stbux",	X(31,247),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
 
@@ -3767,8 +3767,8 @@ const struct powerpc_opcode powerpc_opco
 {"lscbx.",	XRC(31,277,1),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
 
 {"dcbtt",	XRT(31,278,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
-{"dcbt",	X(31,278),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
 {"dcbt",	X(31,278),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
+{"dcbt",	X(31,278),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
 
 {"lhzx",	X(31,279),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
 
@@ -4399,16 +4399,16 @@ const struct powerpc_opcode powerpc_opco
 {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
 
-{"msync",	X(31,598),	0xffffffff,  BOOKE,	PPCNONE,	{0}},
 {"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	PPCNONE,	{0}},
 {"ptesync",	XSYNC(31,598,2), 0xffffffff, PPC64,	PPCNONE,	{0}},
-{"sync",	X(31,598),	XSYNC_MASK,  PPCCOM,	PPCNONE,	{LS}},
+{"sync",	X(31,598),	XSYNC_MASK,  PPCCOM,	BOOKE,		{LS}},
+{"msync",	X(31,598),	0xffffffff,  BOOKE,	PPCNONE,	{0}},
 {"dcs",		X(31,598),	0xffffffff,  PWRCOM,	PPCNONE,	{0}},
 
 {"lfdx",	X(31,599),	X_MASK,      COM,	PPCNONE,	{FRT, RA0, RB}},
 
-{"lfdepx",	X(31,607),	X_MASK,      E500MC,	PPCNONE,	{FRT, RA, RB}},
 {"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	POWER7,		{FRT, RB}},
+{"lfdepx",	X(31,607),	X_MASK,      E500MC,	PPCNONE,	{FRT, RA, RB}},
 
 {"lddx",	X(31,611),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
 
@@ -4502,8 +4502,8 @@ const struct powerpc_opcode powerpc_opco
 {"sreq",	XRC(31,729,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"sreq.",	XRC(31,729,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
-{"stfdepx",	X(31,735),	X_MASK,      E500MC,	PPCNONE,	{FRS, RA, RB}},
 {"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	POWER7,		{RT, FRB}},
+{"stfdepx",	X(31,735),	X_MASK,      E500MC,	PPCNONE,	{FRS, RA, RB}},
 
 {"stddx",	X(31,739),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
 
@@ -4602,8 +4602,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"lbzcix",	X(31,853),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
+{"eieio",	X(31,854),	0xffffffff,  PPC,	BOOKE,		{0}},
 {"mbar",	X(31,854),	X_MASK,      BOOKE,	PPCNONE,	{MO}},
-{"eieio",	X(31,854),	0xffffffff,  PPC,	PPCNONE,	{0}},
 
 {"lfiwax",	X(31,855),	X_MASK,      POWER6,	PPCNONE,	{FRT, RA0, RB}},
 
@@ -4687,10 +4687,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"stxvd2x",	X(31,972),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
 
+{"tlbld",	X(31,978),	XRTRA_MASK,  PPC,	PPC403|BOOKE,	{RB}},
 {"tlbwehi",	XTLB(31,978,0),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
 {"tlbwelo",	XTLB(31,978,1),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
 {"tlbwe",	X(31,978),	X_MASK,   PPC403|BOOKE,	PPCNONE,	{RSO, RAOPT, SHO}},
-{"tlbld",	X(31,978),	XRTRA_MASK,  PPC,	PPCNONE,	{RB}},
 
 {"stbcix",	X(31,981),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
@@ -4795,16 +4795,12 @@ const struct powerpc_opcode powerpc_opco
 {"stfdu",	OP(55),		OP_MASK,     COM,	PPCNONE,	{FRS, D, RAS}},
 
 {"lq",		OP(56),		OP_MASK,     POWER4,	PPCNONE,	{RTQ, DQ, RAQ}},
-
-{"lfq",		OP(56),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
-
 {"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
+{"lfq",		OP(56),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
 
 {"lfdp",	OP(57),		OP_MASK,     POWER6,	POWER7,		{FRT, D, RA0}},
-
-{"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
-
 {"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
+{"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
 
 {"ld",		DSO(58,0),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
 {"ldu",		DSO(58,1),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RAL}},
@@ -4828,18 +4824,18 @@ const struct powerpc_opcode powerpc_opco
 {"fsqrts",	A(59,22,0),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
 {"fsqrts.",	A(59,22,1),    AFRAFRC_MASK, PPC,	PPCNONE,	{FRT, FRB}},
 
-{"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
-{"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 {"fres",	A(59,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"fres",	A(59,24,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 {"fres.",	A(59,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"fres.",	A(59,24,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 
 {"fmuls",	A(59,25,0),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
 {"fmuls.",	A(59,25,1),	AFRB_MASK,   PPC,	PPCNONE,	{FRT, FRA, FRC}},
 
-{"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
-{"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 {"frsqrtes",	A(59,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"frsqrtes",	A(59,26,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 {"frsqrtes.",	A(59,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"frsqrtes.",	A(59,26,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 
 {"fmsubs",	A(59,28,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"fmsubs.",	A(59,28,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
@@ -5062,15 +5058,12 @@ const struct powerpc_opcode powerpc_opco
 {"xvcvsxddp",	XX2(60,504),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
 {"xvnegdp",	XX2(60,505),	XX2_MASK,    PPCVSX,	PPCNONE,	{XT6, XB6}},
 
-{"stfq",	OP(60),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
-
 {"psq_st",	OP(60),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
+{"stfq",	OP(60),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
 
 {"stfdp",	OP(61),		OP_MASK,     POWER6,	PPCNONE,	{FRT, D, RA0}},
-
-{"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
-
 {"psq_stu",	OP(61),		OP_MASK,     PPCPS,	PPCNONE,	{FRS,PSD,RA,PSW,PSQ}},
+{"stfqu",	OP(61),		OP_MASK,     POWER2,	PPCNONE,	{FRS, D, RA}},
 
 {"std",		DSO(62,0),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RA0}},
 {"stdu",	DSO(62,1),	DS_MASK,     PPC64,	PPCNONE,	{RS, DS, RAS}},
@@ -5121,20 +5114,20 @@ const struct powerpc_opcode powerpc_opco
 {"fsel",	A(63,23,0),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"fsel.",	A(63,23,1),	A_MASK,      PPC,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 
-{"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
-{"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 {"fre",		A(63,24,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"fre",		A(63,24,0),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 {"fre.",	A(63,24,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"fre.",	A(63,24,1),   AFRALFRC_MASK, POWER5,	POWER7,		{FRT, FRB, A_L}},
 
 {"fmul",	A(63,25,0),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
 {"fm",		A(63,25,0),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
 {"fmul.",	A(63,25,1),	AFRB_MASK,   PPCCOM,	PPCNONE,	{FRT, FRA, FRC}},
 {"fm.",		A(63,25,1),	AFRB_MASK,   PWRCOM,	PPCNONE,	{FRT, FRA, FRC}},
 
-{"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
-{"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 {"frsqrte",	A(63,26,0),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"frsqrte",	A(63,26,0),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 {"frsqrte.",	A(63,26,1),   AFRAFRC_MASK,  POWER7,	PPCNONE,	{FRT, FRB}},
+{"frsqrte.",	A(63,26,1),   AFRALFRC_MASK, PPC,	POWER7,		{FRT, FRB, A_L}},
 
 {"fmsub",	A(63,28,0),	A_MASK,      PPCCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
 {"fms",		A(63,28,0),	A_MASK,      PWRCOM,	PPCNONE,	{FRT, FRA, FRC, FRB}},
@@ -5194,10 +5187,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcmpoq",	X(63,130),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
 
-{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE,	{BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
+{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE,	{BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
 
 {"fnabs",	XRC(63,136,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
 {"fnabs.",	XRC(63,136,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
@@ -5253,10 +5246,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"dtstsfq",	X(63,674),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
 
-{"mtfsf",	XFL(63,711,0),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
 {"mtfsf",	XFL(63,711,0),	XFL_MASK,    POWER6,	PPCNONE,	{FLM, FRB, XFL_L, W}},
-{"mtfsf.",	XFL(63,711,1),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
+{"mtfsf",	XFL(63,711,0),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
 {"mtfsf.",	XFL(63,711,1),	XFL_MASK,    POWER6,	PPCNONE,	{FLM, FRB, XFL_L, W}},
+{"mtfsf.",	XFL(63,711,1),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
 
 {"drdpq",	XRC(63,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
 {"drdpq.",	XRC(63,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},


^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PATCH]
@ 2022-10-28  7:20 Joshi, Tejas Sanjay
  2022-10-28  8:15 ` [PATCH] Jan Beulich
  0 siblings, 1 reply; 13+ messages in thread
From: Joshi, Tejas Sanjay @ 2022-10-28  7:20 UTC (permalink / raw)
  To: binutils; +Cc: hjl.tools, jbeulich, Gopalasubramanian, Ganesh

[-- Attachment #1: Type: text/plain, Size: 1635 bytes --]

[Public]

Hello,

Patch attached here adds the following:
	* New AMD znver4 processor (family 25). In addition to znver3 features, the architecture has following features:
		*avx512f, avx512dq, avx512ifma, avx512cd, avx512bw, avx512vl, avx512bf16, avx512vbmi, avx512vbmi2, avx512vnni, avx512bitalg, avx512vpopcntdq, gfni, rmpquery
	* Details for new feature RMPQUERY are available in the public document : https://www.amd.com/system/files/TechDocs/24594.pdf
New test files added:
	* arch-14-1.s: New ISAs supported under march.
	* x86-64-arch-4-1.s: 64-bit version of the test.
	* rmpquery.s: The test checking the rmpquery instruction.
Make check passes on x86-64. Good to commit?

ChangeLog:

2022-09-28  Tejas Joshi <TejasSanjay.Joshi@amd.com>

gas/

	* config/tc-i386.c (cpu_arch): Add CPU_ZNVER4_FLAGS flags.
	* doc/c-i386.texi: Add znver4.
	* testsuite/gas/i386/arch-14-1.d: New.
	* testsuite/gas/i386/arch-14-1.s: New.
	* testsuite/gas/i386/arch-14-znver4.d: New.
	* testsuite/gas/i386/i386.exp: Add new znver4 test cases.
	* testsuite/gas/i386/rmpquery.d: New.
	* testsuite/gas/i386/rmpquery.s: New.
	* testsuite/gas/i386/x86-64-arch-4-1.d: New.
	* testsuite/gas/i386/x86-64-arch-4-1.s: New.
	* testsuite/gas/i386/x86-64-arch-4-znver4.d: New.

opcodes/

	* i386-dis.c (x86_64_table): Add rmpquery.
	* i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CpuRMPQUERY.
	(cpu_flags): Add CpuRMPQUERY.
	* i386-opc.h (enum): Add CpuRMPQUERY.
	(i386_cpu_flags): Add cpurmpquery.
	* i386-opc.tbl: Add rmpquery insn.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

Regards,
Tejas

[-- Attachment #2: 0001-Add-AMD-znver4-processor-support.patch --]
[-- Type: application/octet-stream, Size: 16352 bytes --]

From 96c7d2b1056ad034fa9cb9c0bec7fc5e09ec1bdf Mon Sep 17 00:00:00 2001
From: Tejas Joshi <TejasSanjay.Joshi@amd.com>
Date: Fri, 21 Oct 2022 14:56:32 +0530
Subject: [PATCH] Add AMD znver4 processor support

2022-09-28  Tejas Joshi <TejasSanjay.Joshi@amd.com>

gas/

	* config/tc-i386.c (cpu_arch): Add CPU_ZNVER4_FLAGS flags.
	* doc/c-i386.texi: Add znver4.
	* testsuite/gas/i386/arch-14-1.d: New.
	* testsuite/gas/i386/arch-14-1.s: New.
	* testsuite/gas/i386/arch-14-znver4.d: New.
	* testsuite/gas/i386/i386.exp: Add new znver4 test cases.
	* testsuite/gas/i386/rmpquery.d: New.
	* testsuite/gas/i386/rmpquery.s: New.
	* testsuite/gas/i386/x86-64-arch-4-1.d: New.
	* testsuite/gas/i386/x86-64-arch-4-1.s: New.
	* testsuite/gas/i386/x86-64-arch-4-znver4.d: New.

opcodes/

	* i386-dis.c (x86_64_table): Add rmpquery.
	* i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CpuRMPQUERY.
	(cpu_flags): Add CpuRMPQUERY.
	* i386-opc.h (enum): Add CpuRMPQUERY.
	(i386_cpu_flags): Add cpurmpquery.
	* i386-opc.tbl: Add rmpquery insn.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

---
 gas/config/tc-i386.c                          |  1 +
 gas/doc/c-i386.texi                           |  5 ++--
 gas/testsuite/gas/i386/arch-14-1.d            | 22 ++++++++++++++++++
 gas/testsuite/gas/i386/arch-14-1.s            | 16 +++++++++++++
 gas/testsuite/gas/i386/arch-14-znver4.d       |  5 ++++
 gas/testsuite/gas/i386/i386.exp               |  5 ++++
 gas/testsuite/gas/i386/rmpquery.d             | 19 +++++++++++++++
 gas/testsuite/gas/i386/rmpquery.s             | 13 +++++++++++
 gas/testsuite/gas/i386/x86-64-arch-4-1.d      | 23 +++++++++++++++++++
 gas/testsuite/gas/i386/x86-64-arch-4-1.s      | 18 +++++++++++++++
 gas/testsuite/gas/i386/x86-64-arch-4-znver4.d |  5 ++++
 opcodes/i386-dis.c                            | 16 ++++++++++++-
 opcodes/i386-gen.c                            |  5 ++++
 opcodes/i386-opc.h                            |  3 +++
 opcodes/i386-opc.tbl                          |  8 +++++++
 15 files changed, 161 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/arch-14-1.d
 create mode 100644 gas/testsuite/gas/i386/arch-14-1.s
 create mode 100644 gas/testsuite/gas/i386/arch-14-znver4.d
 create mode 100644 gas/testsuite/gas/i386/rmpquery.d
 create mode 100644 gas/testsuite/gas/i386/rmpquery.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4-1.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4-1.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-arch-4-znver4.d

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index df83d4b79c0..7f7ffe1ade5 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -974,6 +974,7 @@ static const arch_entry cpu_arch[] =
   ARCH (znver1, ZNVER, ZNVER1, false),
   ARCH (znver2, ZNVER, ZNVER2, false),
   ARCH (znver3, ZNVER, ZNVER3, false),
+  ARCH (znver4, ZNVER, ZNVER4, false),
   ARCH (btver1, BT, BTVER1, false),
   ARCH (btver2, BT, BTVER2, false),
 
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9d2ccddafa7..a1a07314f5e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -124,6 +124,7 @@ processor names are recognized:
 @code{znver1},
 @code{znver2},
 @code{znver3},
+@code{znver4},
 @code{btver1},
 @code{btver2},
 @code{generic32} and
@@ -1467,8 +1468,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
-@item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
-@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
+@item @samp{znver4} @tab @samp{btver1} @tab @samp{btver2} @tab @samp{generic32}
+@item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
diff --git a/gas/testsuite/gas/i386/arch-14-1.d b/gas/testsuite/gas/i386/arch-14-1.d
new file mode 100644
index 00000000000..c240cc11262
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-14-1.d
@@ -0,0 +1,22 @@
+#objdump: -dw
+#name: i386 arch 14-1
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	62 f1 d5 48 58 f4    	vaddpd %zmm4,%zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 1b 31[ 	]*vbroadcastf32x8 \(%ecx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 d5 48 b4 f4[ 	]*vpmadd52luq %zmm4,%zmm5,%zmm6
+[ 	]*[a-f0-9]+:	62 f2 7d 48 c4 f5    	vpconflictd %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 1c f5[ 	]*vpabsb %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f1 d5 0f 58 f4[ 	]*vaddpd %xmm4,%xmm5,%xmm6\{%k7\}
+[ 	]*[a-f0-9]+:	62 f2 57 48 72 f4    	vcvtne2ps2bf16 %zmm4,%zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 8d f4[ 	]*vpermb %zmm4,%zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 4f 63 31[ 	]*vpcompressb %zmm6,\(%ecx\)\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 75 48 52 e3[ 	]*vpdpwssd %zmm3,%zmm1,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 48 8f ec[ 	]*vpshufbitqmb %zmm4,%zmm5,%k5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 f5[ 	]*vpopcntd %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 cf ec[ 	]*gf2p8mulb %xmm4,%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/arch-14-1.s b/gas/testsuite/gas/i386/arch-14-1.s
new file mode 100644
index 00000000000..59e3a687dbe
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-14-1.s
@@ -0,0 +1,16 @@
+# Test -march=
+	.text
+
+	vaddpd	%zmm4, %zmm5, %zmm6	 # AVX512F
+	vbroadcastf32x8	(%ecx), %zmm6	 # AVX512DQ
+	vpmadd52luq	%zmm4, %zmm5, %zmm6	 # AVX512IFMA
+	vpconflictd	%zmm5, %zmm6	 # AVX512CD
+	vpabsb	%zmm5, %zmm6	 # AVX512BW
+	vaddpd	%xmm4, %xmm5, %xmm6{%k7}	 # AVX512{F,VL}
+	vcvtne2ps2bf16	%zmm4, %zmm5, %zmm6	 #AVX512_BF16
+	vpermb	%zmm4, %zmm5, %zmm6	 # AVX512VBMI
+	vpcompressb	%zmm6, (%ecx){%k7}	 # AVX512VBMI2
+	vpdpwssd	%zmm3, %zmm1, %zmm4	 # AVX512VNNI
+	vpshufbitqmb	%zmm4, %zmm5, %k5	 # AVX512BITALG
+	vpopcntd	%zmm5, %zmm6	 # AVX512_VPOPCNTDQ
+	gf2p8mulb %xmm4, %xmm5	 # GFNI
diff --git a/gas/testsuite/gas/i386/arch-14-znver4.d b/gas/testsuite/gas/i386/arch-14-znver4.d
new file mode 100644
index 00000000000..3ae309f9988
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-14-znver4.d
@@ -0,0 +1,5 @@
+#source: arch-14-1.s
+#as: -march=znver4
+#objdump: -dw
+#name: i386 arch 14 (znver4)
+#dump: arch-14-1.d
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 4ae9b9a62c1..a7fd26606d3 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -196,6 +196,7 @@ if [gas_32_check] then {
     run_dump_test "arch-13-znver1"
     run_dump_test "arch-13-znver2"
     run_dump_test "arch-14-znver3"
+    run_dump_test "arch-14-znver4"
     run_dump_test "arch-10-btver1"
     run_dump_test "arch-10-btver2"
     run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
@@ -207,6 +208,7 @@ if [gas_32_check] then {
     run_dump_test "arch-12"
     run_dump_test "arch-13"
     run_dump_test "arch-14"
+    run_dump_test "arch-14-1"
     run_list_test "arch-dflt" "-march=generic32 -al"
     run_list_test "arch-stk" "-march=generic32 -al"
     run_dump_test "8087"
@@ -902,6 +904,8 @@ if [gas_64_check] then {
     run_dump_test "x86-64-arch-2"
     run_dump_test "x86-64-arch-3"
     run_dump_test "x86-64-arch-4"
+    run_dump_test "x86-64-arch-4-1"
+    run_dump_test "rmpquery"
     run_dump_test "x86-64-arch-2-lzcnt"
     run_dump_test "x86-64-arch-2-prefetchw"
     run_dump_test "x86-64-arch-2-bdver1"
@@ -911,6 +915,7 @@ if [gas_64_check] then {
     run_dump_test "x86-64-arch-3-znver1"
     run_dump_test "x86-64-arch-3-znver2"
     run_dump_test "x86-64-arch-4-znver3"
+    run_dump_test "x86-64-arch-4-znver4"
     run_dump_test "x86-64-arch-2-btver1"
     run_dump_test "x86-64-arch-2-btver2"
     run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
diff --git a/gas/testsuite/gas/i386/rmpquery.d b/gas/testsuite/gas/i386/rmpquery.d
new file mode 100644
index 00000000000..f6278e3c8c5
--- /dev/null
+++ b/gas/testsuite/gas/i386/rmpquery.d
@@ -0,0 +1,19 @@
+#objdump: -dw
+#name: 64-bit RMPQUERY insn
+#source: rmpquery.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <att>:
+[ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fd[ 	]+rmpquery[ 	]*
+[ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fd[ 	]+rmpquery[ 	]*
+[ 	]*[a-f0-9]+:[ 	]+67 f3 0f 01 fd[ 	]+addr32 rmpquery[ 	]*
+
+[0-9a-f]+ <intel>:
+[ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fd[ 	]+rmpquery[ 	]*
+[ 	]*[a-f0-9]+:[ 	]+f3 0f 01 fd[ 	]+rmpquery[ 	]*
+[ 	]*[a-f0-9]+:[ 	]+67 f3 0f 01 fd[ 	]+addr32 rmpquery[ 	]*
+#pass
diff --git a/gas/testsuite/gas/i386/rmpquery.s b/gas/testsuite/gas/i386/rmpquery.s
new file mode 100644
index 00000000000..75393734648
--- /dev/null
+++ b/gas/testsuite/gas/i386/rmpquery.s
@@ -0,0 +1,13 @@
+# Check RMPQUERY instruction
+
+	.text
+att:
+        rmpquery
+        rmpquery %rax, %rcx, %rdx
+        rmpquery %eax, %rcx, %rdx
+
+	.intel_syntax noprefix
+intel:
+        rmpquery
+        rmpquery rax, rcx, rdx
+        rmpquery eax, rcx, rdx
diff --git a/gas/testsuite/gas/i386/x86-64-arch-4-1.d b/gas/testsuite/gas/i386/x86-64-arch-4-1.d
new file mode 100644
index 00000000000..3ef54d01b29
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-4-1.d
@@ -0,0 +1,23 @@
+#objdump: -dw
+#name: x86-64 arch 4-1
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 	]*[a-f0-9]+:	62 01 95 40 58 f4    	vaddpd %zmm28,%zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 1b 31[ 	]*vbroadcastf32x8 \(%rcx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 95 40 b4 f4[ 	]*vpmadd52luq %zmm28,%zmm29,%zmm30
+[ 	]*[a-f0-9]+:	62 02 7d 48 c4 f5    	vpconflictd %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 1c f5[ 	]*vpabsb %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 01 95 00 58 f4[ 	]*vaddpd %xmm28,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:	62 02 17 40 72 f4    	vcvtne2ps2bf16 %zmm28,%zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 15 40 8d f4[ 	]*vpermb %zmm28,%zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 4f 63 31[ 	]*vpcompressb %zmm30,\(%rcx\)\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 a2 6d 40 52 d1[ 	]*vpdpwssd %zmm17,%zmm18,%zmm18
+[ 	]*[a-f0-9]+:[ 	]*62 92 15 40 8f ec[ 	]*vpshufbitqmb %zmm28,%zmm29,%k5
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 55 f5[ 	]*vpopcntd %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 cf ec[ 	]*gf2p8mulb %xmm4,%xmm5
+[ 	]*[a-f0-9]+:[ 	]*f3 0f 01 fd[ 	]*rmpquery[ 	]*
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-4-1.s b/gas/testsuite/gas/i386/x86-64-arch-4-1.s
new file mode 100644
index 00000000000..57a370fa752
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-4-1.s
@@ -0,0 +1,18 @@
+# Test -march=
+	.text
+
+	vaddpd	%zmm28, %zmm29, %zmm30	 # AVX512F
+	vbroadcastf32x8	(%rcx), %zmm30	 # AVX512DQ
+	vpmadd52luq	%zmm28, %zmm29, %zmm30	 # AVX512IFMA
+	vpconflictd	%zmm29, %zmm30	 # AVX512CD
+	vpabsb	%zmm29, %zmm30	 # AVX512BW
+	vaddpd	%xmm28, %xmm29, %xmm30	 # AVX512{F,VL}
+	vcvtne2ps2bf16	%zmm28, %zmm29, %zmm30	 #AVX512_BF16
+	vpermb	%zmm28, %zmm29, %zmm30	 # AVX512VBMI
+	vpcompressb	%zmm30, (%rcx){%k7}	 # AVX512VBMI2
+	vpdpwssd	%zmm17, %zmm18, %zmm18	 # AVX512VNNI
+	vpshufbitqmb	%zmm28, %zmm29, %k5	 # AVX512BITALG
+	vpopcntd	%zmm29, %zmm30	 # AVX512_VPOPCNTDQ
+	gf2p8mulb %xmm4, %xmm5
+# RMPQUERY
+	rmpquery
diff --git a/gas/testsuite/gas/i386/x86-64-arch-4-znver4.d b/gas/testsuite/gas/i386/x86-64-arch-4-znver4.d
new file mode 100644
index 00000000000..d64c96f0d40
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-4-znver4.d
@@ -0,0 +1,5 @@
+#source: x86-64-arch-4-1.s
+#as: -march=znver4
+#objdump: -dw
+#name: x86-64 arch 4 (znver4)
+#dump: x86-64-arch-4-1.d
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index fce05e07eea..8af1489a4e6 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -995,6 +995,7 @@ enum
   PREFIX_0F01_REG_5_MOD_3_RM_6,
   PREFIX_0F01_REG_5_MOD_3_RM_7,
   PREFIX_0F01_REG_7_MOD_3_RM_2,
+  PREFIX_0F01_REG_7_MOD_3_RM_5,
   PREFIX_0F01_REG_7_MOD_3_RM_6,
   PREFIX_0F01_REG_7_MOD_3_RM_7,
   PREFIX_0F09,
@@ -1265,6 +1266,7 @@ enum
   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
+  X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
@@ -3024,6 +3026,12 @@ static const struct dis386 prefix_table[][4] = {
     { "mcommit",	{ Skip_MODRM }, 0 },
   },
 
+  /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
+  {
+    { "rdpru", { Skip_MODRM }, 0 },
+    { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
+  },
+
   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
   {
     { "invlpgb",        { Skip_MODRM }, 0 },
@@ -4279,6 +4287,12 @@ static const struct dis386 x86_64_table[][2] = {
     { "stui",	{ Skip_MODRM }, 0 },
   },
 
+  /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
+  {
+    { Bad_Opcode },
+    { "rmpquery", { Skip_MODRM }, 0 },
+  },
+
   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
   {
     { Bad_Opcode },
@@ -8515,7 +8529,7 @@ static const struct dis386 rm_table[][8] = {
     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
     { "mwaitx",		{ { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
     { "clzero",		{ Skip_MODRM }, 0  },
-    { "rdpru",		{ Skip_MODRM }, 0  },
+    { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
   },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 33f13cec192..7c3e456a1e4 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -105,6 +105,8 @@ static initializer cpu_flag_init[] =
     "CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" },
   { "CPU_ZNVER3_FLAGS",
     "CPU_ZNVER2_FLAGS|CpuINVLPGB|CpuTLBSYNC|CpuVAES|CpuVPCLMULQDQ|CpuINVPCID|CpuSNP|CpuOSPKE" },
+  { "CPU_ZNVER4_FLAGS",
+    "CPU_ZNVER3_FLAGS|CpuAVX512F|CpuAVX512DQ|CpuAVX512IFMA|CpuAVX512CD|CpuAVX512BW|CpuAVX512VL|CpuAVX512_BF16|CpuAVX512VBMI|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_VPOPCNTDQ|CpuGFNI|CpuRMPQUERY" },
   { "CPU_BTVER1_FLAGS",
     "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME" },
   { "CPU_BTVER2_FLAGS",
@@ -341,6 +343,8 @@ static initializer cpu_flag_init[] =
     "CpuTLBSYNC" },
   { "CPU_SNP_FLAGS",
     "CpuSNP" },
+  { "CPU_RMPQUERY_FLAGS",
+    "CpuRMPQUERY" },
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -675,6 +679,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuINVLPGB),
   BITFIELD (CpuTLBSYNC),
   BITFIELD (CpuSNP),
+  BITFIELD (CpuRMPQUERY),
   BITFIELD (Cpu64),
   BITFIELD (CpuNo64),
 #ifdef CpuUnused
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index bc9ed61947e..a29336d8777 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -274,6 +274,8 @@ enum
   CpuTLBSYNC,
   /* SNP instructions required */
   CpuSNP,
+  /* RMPQUERY instruction required */
+  CpuRMPQUERY,
 
   /* NOTE: These last three items need to remain last and in this order. */
 
@@ -423,6 +425,7 @@ typedef union i386_cpu_flags
       unsigned int cpuinvlpgb:1;
       unsigned int cputlbsync:1;
       unsigned int cpusnp:1;
+      unsigned int cpurmpquery:1;
       /* NOTE: These last three fields need to remain last and in this order. */
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index e49d3dc98a2..e2686d7773c 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3071,6 +3071,14 @@ pvalidate, 0xf20f01ff, None, CpuSNP, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
 rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword }
 rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword }
 
+// RMPQUERY instruction
+
+rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
+rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword }
+
+// RMPQUERY instruction end
+
 // SNP instructions end
 
 // RDPRU instruction
-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread
* problems re: makeinfo '--split-size' arg?
@ 2003-04-28 17:50 cgd
  2003-04-28 18:55 ` Joseph S. Myers
  0 siblings, 1 reply; 13+ messages in thread
From: cgd @ 2003-04-28 17:50 UTC (permalink / raw)
  To: binutils, gcc, pfeifer

So, i just tried building the head of the recently-created binutils
release branch (for target mips-elf, host x86-linux), and ran into:

/path/.../makeinfo: unrecognized option `--split-size=5000000'


My makeinfo has version:

> makeinfo (GNU texinfo) 4.0
> 
> Copyright (C) 1999 Free Software Foundation, Inc.
> There is NO warranty.  You may redistribute this software
> under the terms of the GNU General Public License.
> For more information about these matters, see the files named COPYING.

And the toplevel 'Makefile.tpl' says:

# For an installed makeinfo, we require it to be from texinfo 4 or
# higher, else we use the "missing" dummy.


While I realize that i should probably be using a newer 'makeinfo', I
cannot easily do so at this time.

I suspect that the top-level Makefile should be modified so that
it uses 'missing' instead of makeinfo if the --split-size option isn't
supported.  (Looks like it was added in rev 4.1 of the texinfo
package.)


I suspect that a diff like the one below is in order.  I tried it, and
it seems to DTRT for the version of makeinfo that i have (which is all
i tried 8-).

If approved, could somebody else please check it in for me?  (I hacked
it into my Makefile.in by hand to test it, but i don't have autogen
and wouldn't want to check in an improperly-generated file, etc...)


thanks,

chris
--
2003-04-28  Chris Demetriou  <cgd@broadcom.com>

	* Makefile.tpl (MAKEINFO): Require makeinfo 4.1 and later.
        * Makefile.in: Regenerate.

Index: Makefile.tpl
===================================================================
RCS file: /cvs/src/src/Makefile.tpl,v
retrieving revision 1.56.4.1
diff -u -p -r1.56.4.1 Makefile.tpl
--- Makefile.tpl	28 Apr 2003 02:25:36 -0000	1.56.4.1
+++ Makefile.tpl	28 Apr 2003 17:49:39 -0000
@@ -194,13 +194,13 @@ M4 = `if [ -f $$r/m4/m4 ] ; \
 	then echo $$r/m4/m4 ; \
 	else echo ${DEFAULT_M4} ; fi`
 
-# For an installed makeinfo, we require it to be from texinfo 4 or
+# For an installed makeinfo, we require it to be from texinfo 4.1 or
 # higher, else we use the "missing" dummy.
 MAKEINFO=@MAKEINFO@
 USUAL_MAKEINFO = `if [ -f $$r/texinfo/makeinfo/makeinfo ] ; \
 	then echo $$r/texinfo/makeinfo/makeinfo ; \
 	else if (makeinfo --version \
-	  | egrep 'texinfo[^0-9]*([1-3][0-9]|[4-9])') >/dev/null 2>&1; \
+	  | egrep 'texinfo[^0-9]*([1-3][0-9]|4\.[1-9]|[5-9])') >/dev/null 2>&1; \
         then echo makeinfo; else echo $$s/missing makeinfo; fi; fi`
 
 # This just becomes part of the MAKEINFO definition passed down to

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PATCH]
@ 2001-12-05  5:44 Jakub Jelinek
  2001-12-06  2:26 ` [PATCH] Nick Clifton
  0 siblings, 1 reply; 13+ messages in thread
From: Jakub Jelinek @ 2001-12-05  5:44 UTC (permalink / raw)
  To: binutils

Hi!

The following patch does 2 things:
1) fixes ld segfault if for some reason (such as relocations against
   SHF_MERGE section) as SEC_MERGE section wasn't successfully merged
2) in preparation of .eh_frame optimizations I'm working on, this patch
   replaces all calls to _bfd_stab_section_offset with
   _bfd_elf_section_offset, so that in order to adjust reloc offsets
   for non-.stab sections all elf backends don't have to be changed again
   and again
Bootstrapped with --enable-targets-all --enable-bfd-64-bit, regression
tested. Ok to commit?

2001-12-05  Jakub Jelinek  <jakub@redhat.com>

	* elf.c (_bfd_elf_rela_local_sym): Only call
	_bfd_merged_section_offset if merge_info is non-NULL.
	(_bfd_elf_rel_local_sym, _bfd_elf_section_offset): New.
	* elf-bfd.h (_bfd_elf_rel_local_sym, _bfd_elf_section_offset): New
	prototypes.
	* elf32-arm.h (elf32_arm_final_link_relocate): Use
	_bfd_elf_section_offset.
	(elf32_arm_relocate_section): Use _bfd_elf_rel_local_sym.
	* elf32-i386.c (elf_i386_relocate_section): Use
	_bfd_elf_section_offset and _bfd_elf_rel_local_sym.
	* elf32-sh.c (sh_elf_relocate_section): Likewise.
	* elf32-sparc.c (elf32_sparc_relocate_section): Use
	_bfd_elf_section_offset.
	* elf32-cris.c (cris_elf_relocate_section): Likewise.
	* elf32-hppa.c (elf32_hppa_relocate_section): Likewise.
	* elf32-i370.c (i370_elf_relocate_section): Likewise.
	* elf32-m68k.c (elf_m68k_relocate_section): Likewise.
	* elf32-mips.c (mips_elf_create_dynamic_relocation): Likewise.
	* elf32-ppc.c (ppc_elf_relocate_section): Likewise.
	* elf32-s390.c (elf_s390_relocate_section): Likewise.
	* elf64-alpha.c (elf64_alpha_relocate_section): Likewise.
	* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
	* elf64-s390.c (elf_s390_relocate_section): Likewise.
	* elf64-sparc.c (sparc64_elf_relocate_section): Likewise.
	* elf64-x86-64.c (elf64_x86_64_relocate_section): Likewise.
	* elfxx-ia64.c (elfNN_ia64_install_dyn_reloc): Likewise.

--- bfd/elf.c.jj	Wed Dec  5 14:42:28 2001
+++ bfd/elf.c	Wed Dec  5 15:25:55 2001
@@ -6393,7 +6393,8 @@ _bfd_elf_rela_local_sym (abfd, sym, sec,
 		+ sec->output_offset
 		+ sym->st_value);
   if ((sec->flags & SEC_MERGE)
-      && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+      && ELF_ST_TYPE (sym->st_info) == STT_SECTION
+      && elf_section_data (sec)->merge_info)
     {
       asection *msec;
 
@@ -6408,3 +6409,37 @@ _bfd_elf_rela_local_sym (abfd, sym, sec,
     }
   return relocation;
 }
+
+bfd_vma
+_bfd_elf_rel_local_sym (abfd, sym, psec, addend)
+     bfd *abfd;
+     Elf_Internal_Sym *sym;
+     asection **psec;
+     bfd_vma addend;
+{     
+  asection *sec = *psec;
+
+  if (elf_section_data (sec)->merge_info == NULL)
+    return sym->st_value + addend;
+
+  return _bfd_merged_section_offset (abfd, psec,
+				     elf_section_data (sec)->merge_info,
+				     sym->st_value + addend, (bfd_vma) 0);
+}
+
+bfd_vma
+_bfd_elf_section_offset (abfd, info, sec, offset)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     asection *sec;
+     bfd_vma offset;
+{
+  struct bfd_elf_section_data *sec_data;
+
+  sec_data = elf_section_data (sec);
+  if (sec_data->stab_info != NULL)
+    return _bfd_stab_section_offset
+	   (abfd, &elf_hash_table (info)->stab_info,
+	    sec, &sec_data->stab_info, offset);
+  return offset;
+}
--- bfd/elf-bfd.h.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf-bfd.h	Wed Dec  5 15:01:37 2001
@@ -1142,6 +1142,10 @@ extern enum elf_reloc_type_class _bfd_el
   PARAMS ((const Elf_Internal_Rela *));
 extern bfd_vma _bfd_elf_rela_local_sym
   PARAMS ((bfd *, Elf_Internal_Sym *, asection *, Elf_Internal_Rela *));
+extern bfd_vma _bfd_elf_rel_local_sym
+  PARAMS ((bfd *, Elf_Internal_Sym *, asection **, bfd_vma));
+extern bfd_vma _bfd_elf_section_offset
+  PARAMS ((bfd *, struct bfd_link_info *, asection *, bfd_vma));
 
 extern unsigned long bfd_elf_hash
   PARAMS ((const char *));
--- bfd/elf32-arm.h.jj	Fri Nov 23 14:26:42 2001
+++ bfd/elf32-arm.h	Wed Dec  5 15:01:37 2001
@@ -1149,22 +1149,11 @@ elf32_arm_final_link_relocate (howto, in
 
 	  skip = false;
 
-	  if (elf_section_data (input_section)->stab_info == NULL)
-	    outrel.r_offset = rel->r_offset;
-	  else
-	    {
-	      bfd_vma off;
-
-	      off = (_bfd_stab_section_offset
-		     (output_bfd, &elf_hash_table (info)->stab_info,
-		      input_section,
-		      & elf_section_data (input_section)->stab_info,
-		      rel->r_offset));
-	      if (off == (bfd_vma) -1)
-		skip = true;
-	      outrel.r_offset = off;
-	    }
-
+	  outrel.r_offset =
+	    _bfd_elf_section_offset (output_bfd, info, input_section,
+				     rel->r_offset);
+	  if (outrel.r_offset == (bfd_vma) -1)
+	    skip = true;
 	  outrel.r_offset += (input_section->output_section->vma
 			      + input_section->output_offset);
 
@@ -1892,9 +1881,7 @@ elf32_arm_relocate_section (output_bfd, 
 		}
 	      msec = sec;
 	      addend =
-		_bfd_merged_section_offset (output_bfd, &msec,
-					    elf_section_data (sec)->merge_info,
-					    sym->st_value + addend, (bfd_vma) 0)
+		_bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
 		- relocation;
 	      addend += msec->output_section->vma + msec->output_offset;
 	      value = (value & ~ howto->dst_mask) | (addend & howto->dst_mask);
--- bfd/elf32-i386.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-i386.c	Wed Dec  5 15:01:37 2001
@@ -1789,9 +1789,7 @@ elf_i386_relocate_section (output_bfd, i
 	      addend = bfd_get_32 (input_bfd, contents + rel->r_offset);
 	      msec = sec;
 	      addend =
-		_bfd_merged_section_offset (output_bfd, &msec,
-					    elf_section_data (sec)->merge_info,
-					    sym->st_value + addend, (bfd_vma) 0)
+		_bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
 		- relocation;
 	      addend += msec->output_section->vma + msec->output_offset;
 	      bfd_put_32 (input_bfd, addend, contents + rel->r_offset);
@@ -2009,19 +2007,11 @@ elf_i386_relocate_section (output_bfd, i
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, htab->elf.stab_info, input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-sh.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-sh.c	Wed Dec  5 15:01:37 2001
@@ -3101,9 +3101,7 @@ sh_elf_relocate_section (output_bfd, inf
               addend = bfd_get_32 (input_bfd, contents + rel->r_offset);
               msec = sec;
               addend =
-		_bfd_merged_section_offset (output_bfd, &msec,
-					    elf_section_data (sec)->merge_info,
-					    sym->st_value + addend, (bfd_vma) 0)
+		_bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
 		- relocation;
 	      addend += msec->output_section->vma + msec->output_offset;
 	      bfd_put_32 (input_bfd, addend, contents + rel->r_offset);
@@ -3284,22 +3282,11 @@ sh_elf_relocate_section (output_bfd, inf
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-sparc.c.jj	Fri Nov 23 15:02:37 2001
+++ bfd/elf32-sparc.c	Wed Dec  5 15:01:37 2001
@@ -1448,22 +1448,11 @@ elf32_sparc_relocate_section (output_bfd
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-cris.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-cris.c	Wed Dec  5 15:01:37 2001
@@ -1283,22 +1283,11 @@ cris_elf_relocate_section (output_bfd, i
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-hppa.c.jj	Wed Dec  5 14:42:28 2001
+++ bfd/elf32-hppa.c	Wed Dec  5 15:01:37 2001
@@ -3949,23 +3949,11 @@ elf32_hppa_relocate_section (output_bfd,
 		 are copied into the output file to be resolved at run
 		 time.  */
 
-	      outrel.r_offset = rel->r_offset;
 	      outrel.r_addend = rel->r_addend;
-	      skip = false;
-	      if (elf_section_data (input_section)->stab_info != NULL)
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &htab->elf.stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      skip = (outrel.r_offset == (bfd_vma) -1);
 	      outrel.r_offset += (input_section->output_offset
 				  + input_section->output_section->vma);
 
--- bfd/elf32-i370.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-i370.c	Wed Dec  5 15:01:37 2001
@@ -1486,22 +1486,11 @@ i370_elf_relocate_section (output_bfd, i
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-m68k.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-m68k.c	Wed Dec  5 15:01:37 2001
@@ -1680,22 +1680,11 @@ elf_m68k_relocate_section (output_bfd, i
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-mips.c.jj	Wed Dec  5 14:42:28 2001
+++ bfd/elf32-mips.c	Wed Dec  5 15:01:37 2001
@@ -6358,29 +6358,10 @@ mips_elf_create_dynamic_relocation (outp
 	      < sreloc->_raw_size);
 
   skip = false;
-
-  /* We begin by assuming that the offset for the dynamic relocation
-     is the same as for the original relocation.  We'll adjust this
-     later to reflect the correct output offsets.  */
-  if (elf_section_data (input_section)->stab_info == NULL)
-    outrel.r_offset = rel->r_offset;
-  else
-    {
-      /* Except that in a stab section things are more complex.
-	 Because we compress stab information, the offset given in the
-	 relocation may not be the one we want; we must let the stabs
-	 machinery tell us the offset.  */
-      outrel.r_offset
-	= (_bfd_stab_section_offset
-	   (output_bfd, &elf_hash_table (info)->stab_info,
-	    input_section,
-	    &elf_section_data (input_section)->stab_info,
-	    rel->r_offset));
-      /* If we didn't need the relocation at all, this value will be
-	 -1.  */
-      if (outrel.r_offset == (bfd_vma) -1)
-	skip = true;
-    }
+  outrel.r_offset =
+    _bfd_elf_section_offset (output_bfd, info, input_section, rel->r_offset);
+  if (outrel.r_offset == (bfd_vma) -1)
+    skip = true;
 
   /* If we've decided to skip this relocation, just output an empty
      record.  Note that R_MIPS_NONE == 0, so that this call to memset
--- bfd/elf32-ppc.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-ppc.c	Wed Dec  5 15:01:37 2001
@@ -3210,22 +3210,11 @@ ppc_elf_relocate_section (output_bfd, in
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rel->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rel->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 
--- bfd/elf32-s390.c.jj	Fri Nov 23 14:26:41 2001
+++ bfd/elf32-s390.c	Wed Dec  5 15:01:37 2001
@@ -1891,19 +1891,11 @@ elf_s390_relocate_section (output_bfd, i
 
               skip = false;
 
-              if (elf_section_data (input_section)->stab_info == NULL)
-                outrel.r_offset = rel->r_offset;
-              else
-                {
-                  off = (_bfd_stab_section_offset
-                         (output_bfd, htab->elf.stab_info, input_section,
-                          &elf_section_data (input_section)->stab_info,
-                          rel->r_offset));
-                  if (off == (bfd_vma) -1)
-                    skip = true;
-                  outrel.r_offset = off;
-                }
-
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
               outrel.r_offset += (input_section->output_section->vma
                                   + input_section->output_offset);
 
--- bfd/elf64-alpha.c.jj	Wed Nov 28 21:24:58 2001
+++ bfd/elf64-alpha.c	Wed Dec  5 15:01:37 2001
@@ -3534,7 +3534,6 @@ elf64_alpha_relocate_section (output_bfd
 	case R_ALPHA_REFQUAD:
 	  {
 	    Elf_Internal_Rela outrel;
-	    boolean skip;
 
 	    /* Careful here to remember RELATIVE relocations for global
 	       variables for symbolic shared objects.  */
@@ -3569,25 +3568,10 @@ elf64_alpha_relocate_section (output_bfd
 		BFD_ASSERT(srel != NULL);
 	      }
 
-	    skip = false;
-
-	    if (elf_section_data (input_section)->stab_info == NULL)
-	      outrel.r_offset = rel->r_offset;
-	    else
-	      {
-		bfd_vma off;
-
-		off = (_bfd_stab_section_offset
-		       (output_bfd, &elf_hash_table (info)->stab_info,
-			input_section,
-			&elf_section_data (input_section)->stab_info,
-			rel->r_offset));
-		if (off == (bfd_vma) -1)
-		  skip = true;
-		outrel.r_offset = off;
-	      }
-
-	    if (! skip)
+	    outrel.r_offset =
+	      _bfd_elf_section_offset (output_bfd, info, input_section,
+				       rel->r_offset);
+	    if (outrel.r_offset != (bfd_vma) -1)
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
 	    else
--- bfd/elf64-ppc.c.jj	Fri Nov 23 14:26:42 2001
+++ bfd/elf64-ppc.c	Wed Dec  5 15:01:37 2001
@@ -3494,20 +3494,11 @@ ppc64_elf_relocate_section (output_bfd, 
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, htab->elf.stab_info, input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
--- bfd/elf64-s390.c.jj	Fri Nov 23 14:26:42 2001
+++ bfd/elf64-s390.c	Wed Dec  5 15:01:37 2001
@@ -1891,18 +1891,11 @@ elf_s390_relocate_section (output_bfd, i
 
               skip = false;
 
-              if (elf_section_data (input_section)->stab_info == NULL)
-                outrel.r_offset = rel->r_offset;
-              else
-                {
-                  off = (_bfd_stab_section_offset
-                         (output_bfd, htab->elf.stab_info, input_section,
-                          &elf_section_data (input_section)->stab_info,
-                          rel->r_offset));
-                  if (off == (bfd_vma) -1)
-                    skip = true;
-                  outrel.r_offset = off;
-                }
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rel->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 
               outrel.r_offset += (input_section->output_section->vma
                                   + input_section->output_offset);
--- bfd/elf64-sparc.c.jj	Fri Nov 23 15:06:45 2001
+++ bfd/elf64-sparc.c	Wed Dec  5 15:01:37 2001
@@ -2184,21 +2184,11 @@ sparc64_elf_relocate_section (output_bfd
 
 		skip = false;
 
-		if (elf_section_data (input_section)->stab_info == NULL)
-		  outrel.r_offset = rel->r_offset;
-		else
-		  {
-		    bfd_vma off;
-
-		    off = (_bfd_stab_section_offset
-			   (output_bfd, &elf_hash_table (info)->stab_info,
-			    input_section,
-			    &elf_section_data (input_section)->stab_info,
-			    rel->r_offset));
-		    if (off == MINUS_ONE)
-		      skip = true;
-		    outrel.r_offset = off;
-		  }
+		outrel.r_offset =
+		  _bfd_elf_section_offset (output_bfd, info, input_section,
+					   rel->r_offset);
+		if (outrel.r_offset == (bfd_vma) -1)
+		  skip = true;
 
 		outrel.r_offset += (input_section->output_section->vma
 				    + input_section->output_offset);
--- bfd/elf64-x86-64.c.jj	Fri Nov 23 14:26:42 2001
+++ bfd/elf64-x86-64.c	Wed Dec  5 15:01:37 2001
@@ -1473,21 +1473,11 @@ elf64_x86_64_relocate_section (output_bf
 
 	      skip = false;
 
-	      if (elf_section_data (input_section)->stab_info == NULL)
-		outrel.r_offset = rela->r_offset;
-	      else
-		{
-		  bfd_vma off;
-
-		  off = (_bfd_stab_section_offset
-			 (output_bfd, &elf_hash_table (info)->stab_info,
-			  input_section,
-			  &elf_section_data (input_section)->stab_info,
-			  rela->r_offset));
-		  if (off == (bfd_vma) -1)
-		    skip = true;
-		  outrel.r_offset = off;
-		}
+	      outrel.r_offset =
+		_bfd_elf_section_offset (output_bfd, info, input_section,
+					 rela->r_offset);
+	      if (outrel.r_offset == (bfd_vma) -1)
+		skip = true;
 
 	      outrel.r_offset += (input_section->output_section->vma
 				  + input_section->output_offset);
--- bfd/elfxx-ia64.c.jj	Wed Nov 28 21:24:59 2001
+++ bfd/elfxx-ia64.c	Wed Dec  5 15:01:38 2001
@@ -3014,33 +3014,19 @@ elfNN_ia64_install_dyn_reloc (abfd, info
 {
   Elf_Internal_Rela outrel;
 
-  outrel.r_offset = (sec->output_section->vma
-		     + sec->output_offset
-		     + offset);
+  offset += sec->output_section->vma + sec->output_offset;
 
   BFD_ASSERT (dynindx != -1);
   outrel.r_info = ELFNN_R_INFO (dynindx, type);
   outrel.r_addend = addend;
-
-  if (elf_section_data (sec)->stab_info != NULL)
+  outrel.r_offset = _bfd_elf_section_offset (abfd, info, sec, offset);
+  if (outrel.r_offset == (bfd_vma) -1)
     {
-      /* This may be NULL for linker-generated relocations, as it is
-	 inconvenient to pass all the bits around.  And this shouldn't
-	 happen.  */
-      BFD_ASSERT (info != NULL);
-
-      offset = (_bfd_stab_section_offset
-		(abfd, &elf_hash_table (info)->stab_info, sec,
-		 &elf_section_data (sec)->stab_info, offset));
-      if (offset == (bfd_vma) -1)
-	{
-	  /* Run for the hills.  We shouldn't be outputting a relocation
-	     for this.  So do what everyone else does and output a no-op.  */
-	  outrel.r_info = ELFNN_R_INFO (0, R_IA64_NONE);
-	  outrel.r_addend = 0;
-	  offset = 0;
-	}
-      outrel.r_offset = offset;
+      /* Run for the hills.  We shouldn't be outputting a relocation
+	 for this.  So do what everyone else does and output a no-op.  */
+      outrel.r_info = ELFNN_R_INFO (0, R_IA64_NONE);
+      outrel.r_addend = 0;
+      outrel.r_offset = 0;
     }
 
   bfd_elfNN_swap_reloca_out (abfd, &outrel,

	Jakub

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [PATCH]
@ 2000-02-09 20:39 Andrew Cagney
  0 siblings, 0 replies; 13+ messages in thread
From: Andrew Cagney @ 2000-02-09 20:39 UTC (permalink / raw)
  To: GDB Patches, BINUTILS Patches

FYI,

I've committed the following to the include directory.

Wed Feb  9 18:45:49 2000  Andrew Cagney  <cagney@b1.cygnus.com>

        * wait.h: Delete. No longer used by GDB.

Andrew

^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-10-31  9:37 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-04-02  4:56 [PATCH] Peter Bergner
2009-04-02  5:05 ` [PATCH] Fix up -Many handling PowerPC (was: [PATCH]) Peter Bergner
2009-04-02  7:01 ` [PATCH] Alan Modra
2009-04-02 13:32   ` [PATCH] Fix up -Many handling PowerPC (was: [PATCH]) Peter Bergner
  -- strict thread matches above, loose matches on Subject: below --
2022-10-28  7:20 [PATCH] Joshi, Tejas Sanjay
2022-10-28  8:15 ` [PATCH] Jan Beulich
2022-10-28 15:45   ` [PATCH] H.J. Lu
2022-10-31  4:37     ` [PATCH] Joshi, Tejas Sanjay
2022-10-31  9:37       ` [PATCH] Jan Beulich
2003-04-28 17:50 problems re: makeinfo '--split-size' arg? cgd
2003-04-28 18:55 ` Joseph S. Myers
     [not found]   ` <mailpost.1051556216.2781@news-sj1-1>
2003-05-01 17:27     ` cgd
2003-05-02  6:23       ` Gerald Pfeifer
2003-05-02 21:44         ` [patch] cgd
2001-12-05  5:44 [PATCH] Jakub Jelinek
2001-12-06  2:26 ` [PATCH] Nick Clifton
2000-02-09 20:39 [PATCH] Andrew Cagney

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