* [PATCH 0/4] Add support for V3 BPF atomic instructions
@ 2023-05-11 14:13 Jose E. Marchesi
2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Jose E. Marchesi @ 2023-05-11 14:13 UTC (permalink / raw)
To: binutils
Hello people!
The BPF v3 ISA introduces a whole new set of atomic instructions.
This patch series adds support for these to the GNU binutils.
The first patch in the series is preparatory, and it changes the
generic CGEN support in opcodes to allow base instructions longer than
32-bit, which is required when you have opcodes past that position, as
it happens with these new instructions. This is the part for which I
need an OK from a global maintainer.
Of course review of the BPF specific parts is also appreciated!
Salud!
Jose E. Marchesi (4):
opcodes: use CGEN_INSN_LGUINT for base instructions
cpu: add V3 BPF atomic instructions
gas: add tests for BPF V3 atomic instructions
gas: document V3 BPF atomic instructions in the GAS manual
cpu/ChangeLog | 4 +
cpu/bpf.cpu | 164 ++++++++++++++++---
gas/ChangeLog | 14 +-
gas/doc/c-bpf.texi | 56 ++++++-
gas/testsuite/gas/bpf/atomic-v3-be.d | 30 ++++
gas/testsuite/gas/bpf/atomic-v3.d | 30 ++++
gas/testsuite/gas/bpf/atomic-v3.s | 22 +++
gas/testsuite/gas/bpf/bpf.exp | 2 +
include/ChangeLog | 4 +
include/opcode/cgen.h | 10 +-
opcodes/ChangeLog | 26 +++
opcodes/bpf-desc.c | 182 +++++++++++++++++++++
opcodes/bpf-desc.h | 30 +++-
opcodes/bpf-dis.c | 2 +-
opcodes/bpf-opc.c | 232 ++++++++++++++++++++++++++-
opcodes/bpf-opc.h | 14 +-
opcodes/cgen-dis.c | 2 +-
opcodes/cgen-dis.in | 2 +-
opcodes/cgen-opc.c | 8 +-
opcodes/epiphany-dis.c | 2 +-
opcodes/fr30-dis.c | 2 +-
opcodes/frv-dis.c | 2 +-
opcodes/ip2k-dis.c | 2 +-
opcodes/iq2000-dis.c | 2 +-
opcodes/lm32-dis.c | 2 +-
opcodes/m32c-dis.c | 2 +-
opcodes/m32r-dis.c | 2 +-
opcodes/mep-dis.c | 2 +-
opcodes/mt-dis.c | 2 +-
opcodes/or1k-dis.c | 2 +-
opcodes/xstormy16-dis.c | 2 +-
31 files changed, 788 insertions(+), 70 deletions(-)
create mode 100644 gas/testsuite/gas/bpf/atomic-v3-be.d
create mode 100644 gas/testsuite/gas/bpf/atomic-v3.d
create mode 100644 gas/testsuite/gas/bpf/atomic-v3.s
--
2.30.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-05-11 14:13 [PATCH 0/4] Add support for V3 BPF atomic instructions Jose E. Marchesi @ 2023-05-11 14:13 ` Jose E. Marchesi 2023-05-11 16:05 ` Jan Beulich 2023-05-17 13:03 ` Nick Clifton 2023-05-11 14:13 ` [PATCH 2/4] cpu: add V3 BPF atomic instructions Jose E. Marchesi ` (2 subsequent siblings) 3 siblings, 2 replies; 10+ messages in thread From: Jose E. Marchesi @ 2023-05-11 14:13 UTC (permalink / raw) To: binutils This patch changes the opcodes CGEN support code in order to allow base instructions with opcodes past the least significative 32 bits. Note that the masks have been adapted in a previous patch. This patch has been regtested for all the current targets in binutils that are based on CGEN, namely: - bpf-unknown-none - lm32-elf - fr30-elf - ip2k-elf - iq2000-elf - m32c-elf - m32r-elf - mep-elf - mt-elf - or1k-elf - stormy16-elf" Also with --enable-cgen-maint and --enable-targets=all. No regressions observed. include/ChangeLog: 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h (CGEN_IVALUE): Make room for 64-bit base values. opcodes/ChangeLog: 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-dis.in (print_insn): Use CGEN_INSN_LGUINT for instruction base values. * cgen-dis.c (cgen_dis_lookup_insn): Likewise. * cgen-opc.c (cgen_macro_insn_count): Likewise. * epiphany-dis.c: Regenerate. * fr30-dis.c: Likewise. * frv-dis.c: Likewise. * ip2k-dis.c: Likewise. * iq2000-dis.c: Likewise. * lm32-dis.c: Likewise. * m32c-dis.c: Likewise. * m32r-dis.c: Likewise. * mep-dis.c: Likewise. * mt-dis.c: Likewise. * or1k-dis.c: Likewise. * xstormy16-dis.c: Likewise. --- include/ChangeLog | 4 ++++ include/opcode/cgen.h | 10 +++++----- opcodes/ChangeLog | 19 +++++++++++++++++++ opcodes/bpf-dis.c | 2 +- opcodes/cgen-dis.c | 2 +- opcodes/cgen-dis.in | 2 +- opcodes/cgen-opc.c | 8 ++++---- opcodes/epiphany-dis.c | 2 +- opcodes/fr30-dis.c | 2 +- opcodes/frv-dis.c | 2 +- opcodes/ip2k-dis.c | 2 +- opcodes/iq2000-dis.c | 2 +- opcodes/lm32-dis.c | 2 +- opcodes/m32c-dis.c | 2 +- opcodes/m32r-dis.c | 2 +- opcodes/mep-dis.c | 2 +- opcodes/mt-dis.c | 2 +- opcodes/or1k-dis.c | 2 +- opcodes/xstormy16-dis.c | 2 +- 19 files changed, 47 insertions(+), 24 deletions(-) diff --git a/include/ChangeLog b/include/ChangeLog index b157251bea8..d38f507f4e3 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * opcode/cgen.h (CGEN_IVALUE): Make room for 64-bit base values. + 2023-03-23 Frederic Cambus <fred@statdns.com> * elf/common.h (PT_OPENBSD_MUTABLE): Define. diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 6c0732b4b25..9d638f091f5 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -928,7 +928,7 @@ typedef struct typedef struct { /* The opcode portion of the base insn. */ - CGEN_INSN_INT base_value; + CGEN_INSN_LGUINT base_value; #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS /* Extra opcode values beyond base_value. */ @@ -1186,7 +1186,7 @@ extern CGEN_INSN_LIST * cgen_asm_lookup_insn instruction (the actually hashing done is up to the target). */ extern CGEN_INSN_LIST * cgen_dis_lookup_insn - (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); + (CGEN_CPU_DESC, const char *, CGEN_INSN_LGUINT); /* FIXME: delete these two */ #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) @@ -1449,7 +1449,7 @@ extern int CGEN_SYM (get_mach) (const char *); /* Operand index computation. */ extern const CGEN_INSN * cgen_lookup_insn (CGEN_CPU_DESC, const CGEN_INSN * insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + CGEN_INSN_LGUINT int_value_, unsigned char *bytes_value_, int length_, CGEN_FIELDS *fields_, int alias_p_); extern void cgen_get_insn_operands (CGEN_CPU_DESC, const CGEN_INSN * insn_, @@ -1461,10 +1461,10 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands /* Cover fns to bfd_get/set. */ -extern CGEN_INSN_INT cgen_get_insn_value +extern CGEN_INSN_LGUINT cgen_get_insn_value (CGEN_CPU_DESC, unsigned char *, int, int); extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_LGUINT, int); extern CGEN_INSN_INT cgen_get_base_insn_value (CGEN_CPU_DESC, unsigned char *, int); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 890931e6b8a..d954bb938aa 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,22 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * cgen-dis.in (print_insn): Use CGEN_INSN_LGUINT for instruction + base values. + * cgen-dis.c (cgen_dis_lookup_insn): Likewise. + * cgen-opc.c (cgen_macro_insn_count): Likewise. + * epiphany-dis.c: Regenerate. + * fr30-dis.c: Likewise. + * frv-dis.c: Likewise. + * ip2k-dis.c: Likewise. + * iq2000-dis.c: Likewise. + * lm32-dis.c: Likewise. + * m32c-dis.c: Likewise. + * m32r-dis.c: Likewise. + * mep-dis.c: Likewise. + * mt-dis.c: Likewise. + * or1k-dis.c: Likewise. + * xstormy16-dis.c: Likewise. + 2023-04-21 Tom Tromey <tromey@adacore.com> * i386-dis.c (OP_J): Check result of get16. diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index 0a345179569..a1f2c71fa5d 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -367,7 +367,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c index 90746a845ed..917ce0a8ecc 100644 --- a/opcodes/cgen-dis.c +++ b/opcodes/cgen-dis.c @@ -232,7 +232,7 @@ build_dis_hash_table (CGEN_CPU_DESC cd) /* Return the first entry in the hash list for INSN. */ CGEN_INSN_LIST * -cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) +cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_LGUINT value) { unsigned int hash; diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index c144c7eb450..16f888fa9c6 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -202,7 +202,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index 7141ffb6a3f..86d897580fa 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -355,13 +355,13 @@ cgen_macro_insn_count (CGEN_CPU_DESC cd) /* Cover function to read and properly byteswap an insn value. */ -CGEN_INSN_INT +CGEN_INSN_LGUINT cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, int endian) { int big_p = (endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; - CGEN_INSN_INT value = 0; + CGEN_INSN_LGUINT value = 0; if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) { @@ -397,7 +397,7 @@ void cgen_put_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, - CGEN_INSN_INT value, + CGEN_INSN_LGUINT value, int endian) { int big_p = (endian == CGEN_ENDIAN_BIG); @@ -446,7 +446,7 @@ cgen_put_insn_value (CGEN_CPU_DESC cd, const CGEN_INSN * cgen_lookup_insn (CGEN_CPU_DESC cd, const CGEN_INSN *insn, - CGEN_INSN_INT insn_int_value, + CGEN_INSN_LGUINT insn_int_value, /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ unsigned char *insn_bytes_value, int length, diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c index 72ea8bcc645..a77b1c24765 100644 --- a/opcodes/epiphany-dis.c +++ b/opcodes/epiphany-dis.c @@ -443,7 +443,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index f0918b8a49c..f200290fc3f 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -464,7 +464,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index 4740ac4509a..d3901c923be 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -561,7 +561,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index 87ff75b47c2..598b04fc129 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -453,7 +453,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c index 07fd2fc6557..3fc988d078c 100644 --- a/opcodes/iq2000-dis.c +++ b/opcodes/iq2000-dis.c @@ -354,7 +354,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c index b013eaec8a3..268d0f19da8 100644 --- a/opcodes/lm32-dis.c +++ b/opcodes/lm32-dis.c @@ -312,7 +312,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index 950198a15c3..c783510cf4d 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -1056,7 +1056,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 8cfd9fdd499..4bba1c1503c 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -444,7 +444,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c index 91ea29b7c39..0da8a9aa117 100644 --- a/opcodes/mep-dis.c +++ b/opcodes/mep-dis.c @@ -1366,7 +1366,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c index a2121989871..8efaac835a0 100644 --- a/opcodes/mt-dis.c +++ b/opcodes/mt-dis.c @@ -452,7 +452,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c index e70c6519973..e6170d608c7 100644 --- a/opcodes/or1k-dis.c +++ b/opcodes/or1k-dis.c @@ -339,7 +339,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 0de29d60248..a8da1e6285b 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -333,7 +333,7 @@ print_insn (CGEN_CPU_DESC cd, bfd_byte *buf, unsigned int buflen) { - CGEN_INSN_INT insn_value; + CGEN_INSN_LGUINT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; int basesize; -- 2.30.2 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi @ 2023-05-11 16:05 ` Jan Beulich 2023-05-17 13:03 ` Nick Clifton 1 sibling, 0 replies; 10+ messages in thread From: Jan Beulich @ 2023-05-11 16:05 UTC (permalink / raw) To: Jose E. Marchesi; +Cc: binutils On 11.05.2023 16:13, Jose E. Marchesi via Binutils wrote: > --- a/include/opcode/cgen.h > +++ b/include/opcode/cgen.h I will admit that I haven't looked much at cgen code before. Still two points: For one I'm somewhat surprised you get away without also changing CGEN_INSN_BYTES{,_PTR}. And then ... > @@ -928,7 +928,7 @@ typedef struct > typedef struct > { > /* The opcode portion of the base insn. */ > - CGEN_INSN_INT base_value; > + CGEN_INSN_LGUINT base_value; > > #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS > /* Extra opcode values beyond base_value. */ > @@ -1186,7 +1186,7 @@ extern CGEN_INSN_LIST * cgen_asm_lookup_insn > instruction (the actually hashing done is up to the target). */ > > extern CGEN_INSN_LIST * cgen_dis_lookup_insn > - (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); > + (CGEN_CPU_DESC, const char *, CGEN_INSN_LGUINT); > /* FIXME: delete these two */ > #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) > #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) > @@ -1449,7 +1449,7 @@ extern int CGEN_SYM (get_mach) (const char *); > /* Operand index computation. */ > extern const CGEN_INSN * cgen_lookup_insn > (CGEN_CPU_DESC, const CGEN_INSN * insn_, > - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, > + CGEN_INSN_LGUINT int_value_, unsigned char *bytes_value_, > int length_, CGEN_FIELDS *fields_, int alias_p_); > extern void cgen_get_insn_operands > (CGEN_CPU_DESC, const CGEN_INSN * insn_, > @@ -1461,10 +1461,10 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands > > /* Cover fns to bfd_get/set. */ > > -extern CGEN_INSN_INT cgen_get_insn_value > +extern CGEN_INSN_LGUINT cgen_get_insn_value > (CGEN_CPU_DESC, unsigned char *, int, int); > extern void cgen_put_insn_value > - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); > + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_LGUINT, int); > > extern CGEN_INSN_INT cgen_get_base_insn_value > (CGEN_CPU_DESC, unsigned char *, int); ... all the type adjustments are merely to scalars, not to pointers. Therefore it's not really clear to me why you need to change the types of local variables in at least one function for all the targets using cgen. I find it somewhat undesirable to force them all to now act on 64-bit quantities. I would even wonder if this need couldn't be abstracted enough (along the lines of CGEN_INSN_BYTES) such that only bpf would need to start dealing with 64-bit values. Jan ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi 2023-05-11 16:05 ` Jan Beulich @ 2023-05-17 13:03 ` Nick Clifton 2023-05-17 14:03 ` Jose E. Marchesi 1 sibling, 1 reply; 10+ messages in thread From: Nick Clifton @ 2023-05-17 13:03 UTC (permalink / raw) To: Jose E. Marchesi, binutils Hi Jose, > This patch changes the opcodes CGEN support code in order to allow > base instructions with opcodes past the least significative 32 bits. > > Note that the masks have been adapted in a previous patch. > > This patch has been regtested for all the current targets in binutils > that are based on CGEN, namely: > > - bpf-unknown-none > - lm32-elf > - fr30-elf > - ip2k-elf > - iq2000-elf > - m32c-elf > - m32r-elf > - mep-elf > - mt-elf > - or1k-elf > - stormy16-elf" > > Also with --enable-cgen-maint and --enable-targets=all. > No regressions observed. Patch approved - please apply. Cheers Nick ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-05-17 13:03 ` Nick Clifton @ 2023-05-17 14:03 ` Jose E. Marchesi 2023-07-21 22:34 ` David Faust 0 siblings, 1 reply; 10+ messages in thread From: Jose E. Marchesi @ 2023-05-17 14:03 UTC (permalink / raw) To: Nick Clifton; +Cc: binutils, Jan Beulich Hi Nick. > Hi Jose, > >> This patch changes the opcodes CGEN support code in order to allow >> base instructions with opcodes past the least significative 32 bits. >> Note that the masks have been adapted in a previous patch. >> This patch has been regtested for all the current targets in >> binutils >> that are based on CGEN, namely: >> - bpf-unknown-none >> - lm32-elf >> - fr30-elf >> - ip2k-elf >> - iq2000-elf >> - m32c-elf >> - m32r-elf >> - mep-elf >> - mt-elf >> - or1k-elf >> - stormy16-elf" >> Also with --enable-cgen-maint and --enable-targets=all. >> No regressions observed. > > Patch approved - please apply. Thanks. Before pushing I am looking at the CGEN_INSN_BYTES point raised by Jan, which made me realize that, even when I am pretty sure the path introduces no regressions, it may be incomplete because it won't cover targets that would have opcodes past the lowest 32-bits of the base instruction and that also define CGEN_INT_INSN_P (even if we currently don't have such targets.) ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-05-17 14:03 ` Jose E. Marchesi @ 2023-07-21 22:34 ` David Faust 2023-07-22 6:53 ` Jose E. Marchesi 0 siblings, 1 reply; 10+ messages in thread From: David Faust @ 2023-07-21 22:34 UTC (permalink / raw) To: Jose E. Marchesi; +Cc: binutils, Jan Beulich, Nick Clifton On 5/17/23 07:03, Jose E. Marchesi via Binutils wrote: > > Hi Nick. > >> Hi Jose, >> >>> This patch changes the opcodes CGEN support code in order to allow >>> base instructions with opcodes past the least significative 32 bits. >>> Note that the masks have been adapted in a previous patch. >>> This patch has been regtested for all the current targets in >>> binutils >>> that are based on CGEN, namely: >>> - bpf-unknown-none >>> - lm32-elf >>> - fr30-elf >>> - ip2k-elf >>> - iq2000-elf >>> - m32c-elf >>> - m32r-elf >>> - mep-elf >>> - mt-elf >>> - or1k-elf >>> - stormy16-elf" >>> Also with --enable-cgen-maint and --enable-targets=all. >>> No regressions observed. >> >> Patch approved - please apply. > > Thanks. > > Before pushing I am looking at the CGEN_INSN_BYTES point raised by Jan, > which made me realize that, even when I am pretty sure the path > introduces no regressions, it may be incomplete because it won't cover > targets that would have opcodes past the lowest 32-bits of the base > instruction and that also define CGEN_INT_INSN_P (even if we currently > don't have such targets.) With the recent changes to the BPF port to not use CGEN, this patch is no longer needed, right Jose? ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions 2023-07-21 22:34 ` David Faust @ 2023-07-22 6:53 ` Jose E. Marchesi 0 siblings, 0 replies; 10+ messages in thread From: Jose E. Marchesi @ 2023-07-22 6:53 UTC (permalink / raw) To: David Faust; +Cc: binutils, Jan Beulich, Nick Clifton > On 5/17/23 07:03, Jose E. Marchesi via Binutils wrote: >> >> Hi Nick. >> >>> Hi Jose, >>> >>>> This patch changes the opcodes CGEN support code in order to allow >>>> base instructions with opcodes past the least significative 32 bits. >>>> Note that the masks have been adapted in a previous patch. >>>> This patch has been regtested for all the current targets in >>>> binutils >>>> that are based on CGEN, namely: >>>> - bpf-unknown-none >>>> - lm32-elf >>>> - fr30-elf >>>> - ip2k-elf >>>> - iq2000-elf >>>> - m32c-elf >>>> - m32r-elf >>>> - mep-elf >>>> - mt-elf >>>> - or1k-elf >>>> - stormy16-elf" >>>> Also with --enable-cgen-maint and --enable-targets=all. >>>> No regressions observed. >>> >>> Patch approved - please apply. >> >> Thanks. >> >> Before pushing I am looking at the CGEN_INSN_BYTES point raised by Jan, >> which made me realize that, even when I am pretty sure the path >> introduces no regressions, it may be incomplete because it won't cover >> targets that would have opcodes past the lowest 32-bits of the base >> instruction and that also define CGEN_INT_INSN_P (even if we currently >> don't have such targets.) > > With the recent changes to the BPF port to not use CGEN, this patch > is no longer needed, right Jose? Correct. To no have to deal with these kind of tangents was a big motivation for the desCGENization of the port. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/4] cpu: add V3 BPF atomic instructions 2023-05-11 14:13 [PATCH 0/4] Add support for V3 BPF atomic instructions Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi @ 2023-05-11 14:13 ` Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 3/4] gas: add tests for BPF V3 " Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 4/4] gas: document V3 BPF atomic instructions in the GAS manual Jose E. Marchesi 3 siblings, 0 replies; 10+ messages in thread From: Jose E. Marchesi @ 2023-05-11 14:13 UTC (permalink / raw) To: binutils This patch adds a set of new atomic instructions that were introduced in the version 3 BPF ISA: Atomic operations: xor{w,dw} xand{w,dw} xxor{w,dw} Atomic fetch-and-operate: xfadd{w,dw} xfor{w,dw} xfand{w,dw} xfxor{w,dw} Other: xchg{w,dw} xcmp{w,dw} cpu/ChangeLog: 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu: Add BPF V3 atomic instructions, along with semantics. opcodes/ChangeLog: 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.h: Likewise. * bpf-opc.c: Likewise. --- cpu/ChangeLog | 4 + cpu/bpf.cpu | 164 +++++++++++++++++++++++++++----- opcodes/ChangeLog | 7 ++ opcodes/bpf-desc.c | 182 +++++++++++++++++++++++++++++++++++ opcodes/bpf-desc.h | 30 ++++-- opcodes/bpf-opc.c | 232 ++++++++++++++++++++++++++++++++++++++++++++- opcodes/bpf-opc.h | 14 ++- 7 files changed, 593 insertions(+), 40 deletions(-) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 23c89c99eab..78ed5bdb9c5 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,7 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * bpf.cpu: Add BPF V3 atomic instructions, along with semantics. + 2023-03-15 Nick Clifton <nickc@redhat.com> PR 30231 diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index 2ae74fc4c18..c252155eded 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -51,7 +51,7 @@ ;; Whereas the 128-bit instructions (at the moment there is only one ;; of such instructions, lddw) have the form: ;; -;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32 +;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32 ;; ;; In both formats `regs' is itself composed by two fields: ;; @@ -83,7 +83,7 @@ ;; ;; and another for big-endian with instructions like: ;; -;; code:8 dst:4 src:4 offset:16 imm:32 [unused:32 imm:32] +;; code:8 dst:4 src:4x offset:16 imm:32 [unused:32 imm:32] ;; ;; where `offset' and the immediate fields are encoded in ;; little-endian and big-endian byte-order, respectively. @@ -206,7 +206,19 @@ (type pc UDI) (get () (raw-reg h-pc)) (set (newval) (set (raw-reg h-pc) newval))) - + +;; r0 register is used by compare and exchange atomic operation +;; used in addressing by offset mode, so they compare/xchange +;; values in memory with r0. + +(define-hardware + (name h-r0) + (comment "r0 register") + (attrs all-isas) + (type register DI) + (get () (raw-reg h-r0)) + (set (newval) (set (raw-reg h-r0) newval))) + ;; A 64-bit h-sint to be used by the imm64 operand below. XXX this ;; shouldn't be needed, as h-sint is supposed to be able to hold ;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits @@ -234,6 +246,7 @@ (length x-length) (mode x-mode))) + ;; For arithmetic and jump instructions the 8-bit code field is ;; subdivided in: ;; @@ -274,11 +287,54 @@ (dwf f-op-mode "eBPF opcode mode" (all-isas) 0 8 7 3 UINT) (dwf f-op-size "eBPF opcode size" (all-isas) 0 8 4 2 UINT) +;; Atomic instructions abuse f-imm32 to hold extra opcodes. +;; These opcodes are structured like: +;; +;; +;; 31 imm32 0 +;; +-----------+-----+-----+ +;; | | op |flags| +;; +-----------+-----+-----+ +;; --4-- --4-- +;; +;; Where: +;; +;; OP is one of ADD, AND, OR, XOR, CHG, CMP. +;; FLAGS is either 0 or FETCH. + +(dwf f-op-atomic "eBPF atomic insn opcode" (all-isas) 32 64 31 32 UINT) + +(define-normal-insn-enum insn-atomic-op-le "eBPF atomic insn opcode" + ((ISA ebpfle xbpfle)) OP_ATOMIC_LE_ f-op-atomic + ((ADD #x00) + (OR #x40) + (AND #x50) + (XOR #xa0) + (FADD #x01) + (FOR #x41) + (FAND #x51) + (FXOR #xa1) + (CHG #xe1) + (CMP #xf1))) + +(define-normal-insn-enum insn-atomic-op-be "eBPF atomic insn opcode" + ((ISA ebpfbe xbpfbe)) OP_ATOMIC_BE_ f-op-atomic + ((ADD #x00000000) + (OR #x40000000) + (AND #x50000000) + (XOR #xa0000000) + (FADD #x01000000) + (FOR #x41000000) + (FAND #x51000000) + (FXOR #xa1000000) + (CHG #xe1000000) + (CMP #xf1000000))) + (define-normal-insn-enum insn-op-mode "eBPF load/store instruction modes" (all-isas) OP_MODE_ f-op-mode ((IMM #b000) (ABS #b001) (IND #b010) (MEM #b011) ;; #b100 and #b101 are used in classic BPF only, reserved in eBPF. - (XADD #b110))) + (ATOMIC #b110))) (define-normal-insn-enum insn-op-size "eBPF load/store instruction sizes" (all-isas) OP_SIZE_ f-op-size @@ -541,7 +597,7 @@ ;; variant for each ISA: ;; ;; LDDWle for the little-endian ISA -;; LDDWbe for the big-endian ISA +;; LDDWbe for the big-endian ISA (define-pmacro (define-lddw x-endian) (dni (.sym lddw x-endian) @@ -614,7 +670,7 @@ ())) (define-pmacro (define-ldind x-endian) - (begin + (begin (dlind "w" W x-endian SI) (dlind "h" H x-endian HI) (dlind "b" B x-endian QI) @@ -810,35 +866,91 @@ ;;; Atomic instructions -;; The atomic exchange-and-add instructions come in two flavors: one +;; The atomic exchange-and-op instructions come in two flavors: one ;; for swapping 64-bit quantities and another for 32-bit quantities. -(define-pmacro (sem-exchange-and-add x-endian x-mode) +;; Semantic routines for regular atomic operations. +(define-pmacro (sem-atomic-op x-semop x-endian x-mode) + (sequence VOID ((x-mode tmp)) + (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16))) + (set x-mode + (mem x-mode (add DI (.sym dst x-endian) offset16)) + (x-semop x-mode tmp (.sym src x-endian))))) + +;; Semantic routines for atomic operations that involve exchange. +(define-pmacro (sem-atomic-op-fetch x-semop x-endian x-mode) (sequence VOID ((x-mode tmp)) - ;; XXX acquire lock in simulator... as a hardware element? (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16))) (set x-mode (mem x-mode (add DI (.sym dst x-endian) offset16)) - (add x-mode tmp (.sym src x-endian))))) + (x-semop x-mode tmp (.sym src x-endian))) + (set x-mode (.sym src x-endian) tmp))) + +;; Semantic routine for the atomic exchange. +(define-pmacro (sem-exchange x-semop x-endian x-mode) + (sequence VOID ((x-mode tmp)) + (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16))) + (set x-mode (mem x-mode (add DI (.sym dst x-endian) offset16)) (.sym src x-endian)) + (set x-mode (.sym src x-endian) tmp))) + +;; Semantic routine for compare-and-exchange. +(define-pmacro (sem-cmp-exchange x-semop x-endian x-mode) + (sequence VOID ((x-mode tmp)) + (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16))) + (if (eq x-mode (reg h-r0) tmp) + (set x-mode (mem x-mode (add DI (.sym dst x-endian) offset16)) (.sym src x-endian))) + (set x-mode (reg h-r0) (zext tmp)))) + +;; Atomic operation without fetching. +(define-pmacro (dai x-basename x-suffix x-size x-op-code x-endian x-mode semproc semop) + (begin + (dni (.str "x" x-basename x-suffix x-endian) + (.str "x" x-basename x-suffix x-endian) + (endian-isas x-endian) + (.str "x" x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian) + (+ (.sym src x-endian) (.sym dst x-endian) + offset16 OP_MODE_ATOMIC x-size OP_CLASS_STX x-op-code) + (semproc semop x-endian x-mode) + ()))) + +(define-pmacro (dais x-basename x-op-code x-endian semproc semop) + (begin + (dai x-basename "dw" OP_SIZE_DW x-op-code x-endian DI semproc semop) + (dai x-basename "w" OP_SIZE_W x-op-code x-endian SI semproc semop))) (define-pmacro (define-atomic-insns x-endian) (begin - (dni (.str "xadddw" x-endian) - "xadddw" - (endian-isas x-endian) - (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian) - (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian) - offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) - (sem-exchange-and-add x-endian DI) - ()) - (dni (.str "xaddw" x-endian) - "xaddw" - (endian-isas x-endian) - (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian) - (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian) - offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) - (sem-exchange-and-add x-endian SI) - ()))) + (dais add + (.if (.eq x-endian le) OP_ATOMIC_LE_ADD OP_ATOMIC_BE_ADD) + x-endian sem-atomic-op add) + (dais fadd + (.if (.eq x-endian le) OP_ATOMIC_LE_FADD OP_ATOMIC_BE_FADD) + x-endian sem-atomic-op-fetch add) + (dais or + (.if (.eq x-endian le) OP_ATOMIC_LE_OR OP_ATOMIC_BE_OR) + x-endian sem-atomic-op or) + (dais for + (.if (.eq x-endian le) OP_ATOMIC_LE_FOR OP_ATOMIC_BE_FOR) + x-endian sem-atomic-op-fetch or) + (dais and + (.if (.eq x-endian le) OP_ATOMIC_LE_AND OP_ATOMIC_BE_AND) + x-endian sem-atomic-op and) + (dais fand + (.if (.eq x-endian le) OP_ATOMIC_LE_FAND OP_ATOMIC_BE_FAND) + x-endian sem-atomic-op-fetch and) + (dais xor + (.if (.eq x-endian le) OP_ATOMIC_LE_XOR OP_ATOMIC_BE_XOR) + x-endian sem-atomic-op xor) + (dais fxor + (.if (.eq x-endian le) OP_ATOMIC_LE_FXOR OP_ATOMIC_BE_FXOR) + x-endian sem-atomic-op-fetch xor) + ;; CHG and CMP have only "fetch" variants. + (dais chg + (.if (.eq x-endian le) OP_ATOMIC_LE_CHG OP_ATOMIC_BE_CHG) + x-endian sem-exchange ()) + (dais cmp + (.if (.eq x-endian le) OP_ATOMIC_LE_CMP OP_ATOMIC_BE_CMP) + x-endian sem-cmp-exchange ()))) (define-atomic-insns le) (define-atomic-insns be) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d954bb938aa..6debcbc653a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * bpf-desc.c: Regenerate. + * bpf-desc.h: Likewise. + * bpf-opc.h: Likewise. + * bpf-opc.c: Likewise. + 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-dis.in (print_insn): Use CGEN_INSN_LGUINT for instruction diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c index 7bef587da8b..5e18b0c7b40 100644 --- a/opcodes/bpf-desc.c +++ b/opcodes/bpf-desc.c @@ -177,6 +177,7 @@ const CGEN_HW_ENTRY bpf_cgen_hw_table[] = { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } }, { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, + { "h-r0", HW_H_R0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; @@ -197,6 +198,7 @@ const CGEN_IFLD bpf_cgen_ifld_table[] = { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, + { BPF_F_OP_ATOMIC, "f-op-atomic", 32, 64, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, @@ -1571,6 +1573,96 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] = BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, +/* xfadddw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFADDDWLE, "xfadddwle", "xfadddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfaddw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFADDWLE, "xfaddwle", "xfaddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xordw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XORDWLE, "xordwle", "xordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xorw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XORWLE, "xorwle", "xorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfordw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFORDWLE, "xfordwle", "xfordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xforw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFORWLE, "xforwle", "xforw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xanddw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XANDDWLE, "xanddwle", "xanddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xandw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XANDWLE, "xandwle", "xandw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfanddw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFANDDWLE, "xfanddwle", "xfanddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfandw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFANDWLE, "xfandwle", "xfandw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xxordw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XXORDWLE, "xxordwle", "xxordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xxorw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XXORWLE, "xxorwle", "xxorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfxordw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFXORDWLE, "xfxordwle", "xfxordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xfxorw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XFXORWLE, "xfxorwle", "xfxorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xchgdw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XCHGDWLE, "xchgdwle", "xchgdw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xchgw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XCHGWLE, "xchgwle", "xchgw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xcmpdw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XCMPDWLE, "xcmpdwle", "xcmpdw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, +/* xcmpw [$dstle+$offset16],$srcle */ + { + BPF_INSN_XCMPWLE, "xcmpwle", "xcmpw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } + }, /* xadddw [$dstbe+$offset16],$srcbe */ { BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64, @@ -1581,6 +1673,96 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] = BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, +/* xfadddw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFADDDWBE, "xfadddwbe", "xfadddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfaddw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFADDWBE, "xfaddwbe", "xfaddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xordw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XORDWBE, "xordwbe", "xordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xorw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XORWBE, "xorwbe", "xorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfordw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFORDWBE, "xfordwbe", "xfordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xforw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFORWBE, "xforwbe", "xforw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xanddw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XANDDWBE, "xanddwbe", "xanddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xandw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XANDWBE, "xandwbe", "xandw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfanddw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFANDDWBE, "xfanddwbe", "xfanddw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfandw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFANDWBE, "xfandwbe", "xfandw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xxordw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XXORDWBE, "xxordwbe", "xxordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xxorw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XXORWBE, "xxorwbe", "xxorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfxordw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFXORDWBE, "xfxordwbe", "xfxordw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xfxorw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XFXORWBE, "xfxorwbe", "xfxorw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xchgdw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XCHGDWBE, "xchgdwbe", "xchgdw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xchgw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XCHGWBE, "xchgwbe", "xchgw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xcmpdw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XCMPDWBE, "xcmpdwbe", "xcmpdw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, +/* xcmpw [$dstbe+$offset16],$srcbe */ + { + BPF_INSN_XCMPWBE, "xcmpwbe", "xcmpw", 64, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } + }, /* brkpt */ { BPF_INSN_BRKPT, "brkpt", "brkpt", 64, diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h index a4b207629b6..2ecce2c4ea4 100644 --- a/opcodes/bpf-desc.h +++ b/opcodes/bpf-desc.h @@ -50,7 +50,7 @@ extern "C" { #define CGEN_INT_INSN_P 0 /* Maximum number of syntax elements in an instruction. */ -#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16 +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands @@ -85,10 +85,24 @@ typedef enum insn_op_class { , OP_CLASS_ALU, OP_CLASS_JMP, OP_CLASS_JMP32, OP_CLASS_ALU64 } INSN_OP_CLASS; +/* Enum declaration for eBPF atomic insn opcode. */ +typedef enum insn_atomic_op_le { + OP_ATOMIC_LE_ADD = 0, OP_ATOMIC_LE_OR = 64, OP_ATOMIC_LE_AND = 80, OP_ATOMIC_LE_XOR = 160 + , OP_ATOMIC_LE_FADD = 1, OP_ATOMIC_LE_FOR = 65, OP_ATOMIC_LE_FAND = 81, OP_ATOMIC_LE_FXOR = 161 + , OP_ATOMIC_LE_CHG = 225, OP_ATOMIC_LE_CMP = 241 +} INSN_ATOMIC_OP_LE; + +/* Enum declaration for eBPF atomic insn opcode. */ +typedef enum insn_atomic_op_be { + OP_ATOMIC_BE_ADD = 0, OP_ATOMIC_BE_OR = 1073741824, OP_ATOMIC_BE_AND = 1342177280, OP_ATOMIC_BE_XOR = 0xa0000000 + , OP_ATOMIC_BE_FADD = 16777216, OP_ATOMIC_BE_FOR = 1090519040, OP_ATOMIC_BE_FAND = 1358954496, OP_ATOMIC_BE_FXOR = 0xa1000000 + , OP_ATOMIC_BE_CHG = 0xe1000000, OP_ATOMIC_BE_CMP = 0xf1000000 +} INSN_ATOMIC_OP_BE; + /* Enum declaration for eBPF load/store instruction modes. */ typedef enum insn_op_mode { OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3 - , OP_MODE_XADD = 6 + , OP_MODE_ATOMIC = 6 } INSN_OP_MODE; /* Enum declaration for eBPF load/store instruction sizes. */ @@ -140,10 +154,10 @@ typedef enum cgen_ifld_attr { /* Enum declaration for bpf ifield types. */ typedef enum ifield_type { BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC - , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE - , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS - , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B - , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX + , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_OP_ATOMIC + , BPF_F_DSTLE, BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE + , BPF_F_REGS, BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A + , BPF_F_IMM64_B, BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX } IFIELD_TYPE; #define MAX_IFLD ((int) BPF_F_MAX) @@ -171,8 +185,8 @@ typedef enum cgen_hw_attr { /* Enum declaration for bpf hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR - , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64 - , HW_MAX + , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_R0 + , HW_H_SINT64, HW_MAX } CGEN_HW_TYPE; #define MAX_HW ((int) HW_MAX) diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index 1cc06f7cbf6..cc69a021ed6 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -149,6 +149,14 @@ static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = { 64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; +static const CGEN_IFMT ifmt_xadddwle ATTRIBUTE_UNUSED = { + 64, 64, 0xffffffff000000ff, { { F (F_OP_ATOMIC) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xadddwbe ATTRIBUTE_UNUSED = { + 64, 64, 0xffffffff000000ff, { { F (F_OP_ATOMIC) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } +}; + #undef F #define A(a) (1 << CGEN_INSN_##a) @@ -1680,25 +1688,241 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, - & ifmt_ldxwle, { 0xdb } + & ifmt_xadddwle, { 0xdb } }, /* xaddw [$dstle+$offset16],$srcle */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, - & ifmt_ldxwle, { 0xc3 } + & ifmt_xadddwle, { 0xc3 } + }, +/* xfadddw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x1000000db } + }, +/* xfaddw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x1000000c3 } + }, +/* xordw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x40000000db } + }, +/* xorw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x40000000c3 } + }, +/* xfordw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x41000000db } + }, +/* xforw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x41000000c3 } + }, +/* xanddw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x50000000db } + }, +/* xandw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x50000000c3 } + }, +/* xfanddw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x51000000db } + }, +/* xfandw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0x51000000c3 } + }, +/* xxordw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xa0000000db } + }, +/* xxorw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xa0000000c3 } + }, +/* xfxordw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xa1000000db } + }, +/* xfxorw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xa1000000c3 } + }, +/* xchgdw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xe1000000db } + }, +/* xchgw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xe1000000c3 } + }, +/* xcmpdw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xf1000000db } + }, +/* xcmpw [$dstle+$offset16],$srcle */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } }, + & ifmt_xadddwle, { 0xf1000000c3 } }, /* xadddw [$dstbe+$offset16],$srcbe */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, - & ifmt_ldxwbe, { 0xdb } + & ifmt_xadddwbe, { 0xdb } }, /* xaddw [$dstbe+$offset16],$srcbe */ { { 0, 0, 0, 0 }, { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, - & ifmt_ldxwbe, { 0xc3 } + & ifmt_xadddwbe, { 0xc3 } + }, +/* xfadddw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x1000000000000db } + }, +/* xfaddw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x1000000000000c3 } + }, +/* xordw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x40000000000000db } + }, +/* xorw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x40000000000000c3 } + }, +/* xfordw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x41000000000000db } + }, +/* xforw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x41000000000000c3 } + }, +/* xanddw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x50000000000000db } + }, +/* xandw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x50000000000000c3 } + }, +/* xfanddw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x51000000000000db } + }, +/* xfandw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0x51000000000000c3 } + }, +/* xxordw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xa0000000000000db } + }, +/* xxorw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xa0000000000000c3 } + }, +/* xfxordw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xa1000000000000db } + }, +/* xfxorw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xa1000000000000c3 } + }, +/* xchgdw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xe1000000000000db } + }, +/* xchgw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xe1000000000000c3 } + }, +/* xcmpdw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xf1000000000000db } + }, +/* xcmpw [$dstbe+$offset16],$srcbe */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } }, + & ifmt_xadddwbe, { 0xf1000000000000c3 } }, /* brkpt */ { diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h index f838afebb4a..b8496b0a3f5 100644 --- a/opcodes/bpf-opc.h +++ b/opcodes/bpf-opc.h @@ -111,8 +111,17 @@ typedef enum cgen_insn_type { , BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_CALLLE , BPF_INSN_CALLBE, BPF_INSN_CALLRLE, BPF_INSN_CALLRBE, BPF_INSN_JA - , BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE - , BPF_INSN_XADDWBE, BPF_INSN_BRKPT + , BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE, BPF_INSN_XFADDDWLE + , BPF_INSN_XFADDWLE, BPF_INSN_XORDWLE, BPF_INSN_XORWLE, BPF_INSN_XFORDWLE + , BPF_INSN_XFORWLE, BPF_INSN_XANDDWLE, BPF_INSN_XANDWLE, BPF_INSN_XFANDDWLE + , BPF_INSN_XFANDWLE, BPF_INSN_XXORDWLE, BPF_INSN_XXORWLE, BPF_INSN_XFXORDWLE + , BPF_INSN_XFXORWLE, BPF_INSN_XCHGDWLE, BPF_INSN_XCHGWLE, BPF_INSN_XCMPDWLE + , BPF_INSN_XCMPWLE, BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE, BPF_INSN_XFADDDWBE + , BPF_INSN_XFADDWBE, BPF_INSN_XORDWBE, BPF_INSN_XORWBE, BPF_INSN_XFORDWBE + , BPF_INSN_XFORWBE, BPF_INSN_XANDDWBE, BPF_INSN_XANDWBE, BPF_INSN_XFANDDWBE + , BPF_INSN_XFANDWBE, BPF_INSN_XXORDWBE, BPF_INSN_XXORWBE, BPF_INSN_XFXORDWBE + , BPF_INSN_XFXORWBE, BPF_INSN_XCHGDWBE, BPF_INSN_XCHGWBE, BPF_INSN_XCMPDWBE + , BPF_INSN_XCMPWBE, BPF_INSN_BRKPT } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ @@ -132,6 +141,7 @@ struct cgen_fields long f_op_class; long f_op_mode; long f_op_size; + long f_op_atomic; long f_dstle; long f_srcle; long f_dstbe; -- 2.30.2 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/4] gas: add tests for BPF V3 atomic instructions 2023-05-11 14:13 [PATCH 0/4] Add support for V3 BPF atomic instructions Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 2/4] cpu: add V3 BPF atomic instructions Jose E. Marchesi @ 2023-05-11 14:13 ` Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 4/4] gas: document V3 BPF atomic instructions in the GAS manual Jose E. Marchesi 3 siblings, 0 replies; 10+ messages in thread From: Jose E. Marchesi @ 2023-05-11 14:13 UTC (permalink / raw) To: binutils 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/atomic-v3.s: New file. * testsuite/gas/bpf/atomic-v3.d: Likewise. * testsuite/gas/bpf/atomic-v3-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run atomic-v3 and atomic-v3-be. --- gas/ChangeLog | 9 ++++++++- gas/testsuite/gas/bpf/atomic-v3-be.d | 30 ++++++++++++++++++++++++++++ gas/testsuite/gas/bpf/atomic-v3.d | 30 ++++++++++++++++++++++++++++ gas/testsuite/gas/bpf/atomic-v3.s | 22 ++++++++++++++++++++ gas/testsuite/gas/bpf/bpf.exp | 2 ++ 5 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/bpf/atomic-v3-be.d create mode 100644 gas/testsuite/gas/bpf/atomic-v3.d create mode 100644 gas/testsuite/gas/bpf/atomic-v3.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 966f1c5de83..a16647bb4a4 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,8 +1,15 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * testsuite/gas/bpf/atomic-v3.s: New file. + * testsuite/gas/bpf/atomic-v3.d: Likewise. + * testsuite/gas/bpf/atomic-v3-be.d: Likewise. + * testsuite/gas/bpf/bpf.exp: Run atomic-v3 and atomic-v3-be. + 2023-04-27 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.dump: New file. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. - * testsuite/gas/bpf/mem.d: #dump mem.dump. + * testsuite/gas/bpf/mem.d: #dump mem.dump. * testsuite/gas/bpf/lddw.dump: New file. * testsuite/gas/bpf/lddw-pseudoc.d: Likewise. * testsuite/gas/bpf/lddw.d: #dump lddw.dump. diff --git a/gas/testsuite/gas/bpf/atomic-v3-be.d b/gas/testsuite/gas/bpf/atomic-v3-be.d new file mode 100644 index 00000000000..6648bc669b3 --- /dev/null +++ b/gas/testsuite/gas/bpf/atomic-v3-be.d @@ -0,0 +1,30 @@ +#as: --EB +#objdump: -dr +#source: atomic-v3.s +#name: eBPF V3 atomic instructions, big-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2 + 8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2 + 10: db 12 1e ef 00 00 00 40 xordw \[%r1\+0x1eef\],%r2 + 18: c3 12 1e ef 00 00 00 40 xorw \[%r1\+0x1eef\],%r2 + 20: db 12 1e ef 00 00 00 50 xanddw \[%r1\+0x1eef\],%r2 + 28: c3 12 1e ef 00 00 00 50 xandw \[%r1\+0x1eef\],%r2 + 30: db 12 1e ef 00 00 00 a0 xxordw \[%r1\+0x1eef\],%r2 + 38: c3 12 1e ef 00 00 00 a0 xxorw \[%r1\+0x1eef\],%r2 + 40: db 12 1e ef 00 00 00 01 xfadddw \[%r1\+0x1eef\],%r2 + 48: c3 12 1e ef 00 00 00 01 xfaddw \[%r1\+0x1eef\],%r2 + 50: db 12 1e ef 00 00 00 41 xfordw \[%r1\+0x1eef\],%r2 + 58: c3 12 1e ef 00 00 00 41 xforw \[%r1\+0x1eef\],%r2 + 60: db 12 1e ef 00 00 00 51 xfanddw \[%r1\+0x1eef\],%r2 + 68: c3 12 1e ef 00 00 00 51 xfandw \[%r1\+0x1eef\],%r2 + 70: db 12 1e ef 00 00 00 a1 xfxordw \[%r1\+0x1eef\],%r2 + 78: c3 12 1e ef 00 00 00 a1 xfxorw \[%r1\+0x1eef\],%r2 + 80: db 12 1e ef 00 00 00 e1 xchgdw \[%r1\+0x1eef\],%r2 + 88: c3 12 1e ef 00 00 00 e1 xchgw \[%r1\+0x1eef\],%r2 + 90: db 12 1e ef 00 00 00 f1 xcmpdw \[%r1\+0x1eef\],%r2 + 98: c3 12 1e ef 00 00 00 f1 xcmpw \[%r1\+0x1eef\],%r2 diff --git a/gas/testsuite/gas/bpf/atomic-v3.d b/gas/testsuite/gas/bpf/atomic-v3.d new file mode 100644 index 00000000000..23649c7e801 --- /dev/null +++ b/gas/testsuite/gas/bpf/atomic-v3.d @@ -0,0 +1,30 @@ +#as: --EL +#objdump: -dr +#source: atomic-v3.s +#name: eBPF V3 atomic instructions, litle-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2 + 8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2 + 10: db 21 ef 1e 40 00 00 00 xordw \[%r1\+0x1eef\],%r2 + 18: c3 21 ef 1e 40 00 00 00 xorw \[%r1\+0x1eef\],%r2 + 20: db 21 ef 1e 50 00 00 00 xanddw \[%r1\+0x1eef\],%r2 + 28: c3 21 ef 1e 50 00 00 00 xandw \[%r1\+0x1eef\],%r2 + 30: db 21 ef 1e a0 00 00 00 xxordw \[%r1\+0x1eef\],%r2 + 38: c3 21 ef 1e a0 00 00 00 xxorw \[%r1\+0x1eef\],%r2 + 40: db 21 ef 1e 01 00 00 00 xfadddw \[%r1\+0x1eef\],%r2 + 48: c3 21 ef 1e 01 00 00 00 xfaddw \[%r1\+0x1eef\],%r2 + 50: db 21 ef 1e 41 00 00 00 xfordw \[%r1\+0x1eef\],%r2 + 58: c3 21 ef 1e 41 00 00 00 xforw \[%r1\+0x1eef\],%r2 + 60: db 21 ef 1e 51 00 00 00 xfanddw \[%r1\+0x1eef\],%r2 + 68: c3 21 ef 1e 51 00 00 00 xfandw \[%r1\+0x1eef\],%r2 + 70: db 21 ef 1e a1 00 00 00 xfxordw \[%r1\+0x1eef\],%r2 + 78: c3 21 ef 1e a1 00 00 00 xfxorw \[%r1\+0x1eef\],%r2 + 80: db 21 ef 1e e1 00 00 00 xchgdw \[%r1\+0x1eef\],%r2 + 88: c3 21 ef 1e e1 00 00 00 xchgw \[%r1\+0x1eef\],%r2 + 90: db 21 ef 1e f1 00 00 00 xcmpdw \[%r1\+0x1eef\],%r2 + 98: c3 21 ef 1e f1 00 00 00 xcmpw \[%r1\+0x1eef\],%r2 diff --git a/gas/testsuite/gas/bpf/atomic-v3.s b/gas/testsuite/gas/bpf/atomic-v3.s new file mode 100644 index 00000000000..a17e95b6793 --- /dev/null +++ b/gas/testsuite/gas/bpf/atomic-v3.s @@ -0,0 +1,22 @@ + # eBPF v3 atomic instructions + .text + xadddw [%r1+0x1eef], %r2 + xaddw [%r1+0x1eef], %r2 + xordw [%r1+0x1eef], %r2 + xorw [%r1+0x1eef], %r2 + xanddw [%r1+0x1eef], %r2 + xandw [%r1+0x1eef], %r2 + xxordw [%r1+0x1eef], %r2 + xxorw [%r1+0x1eef], %r2 + xfadddw [%r1+0x1eef], %r2 + xfaddw [%r1+0x1eef], %r2 + xfordw [%r1+0x1eef], %r2 + xforw [%r1+0x1eef], %r2 + xfanddw [%r1+0x1eef], %r2 + xfandw [%r1+0x1eef], %r2 + xfxordw [%r1+0x1eef], %r2 + xfxorw [%r1+0x1eef], %r2 + xchgdw [%r1+0x1eef], %r2 + xchgw [%r1+0x1eef], %r2 + xcmpdw [%r1+0x1eef], %r2 + xcmpw [%r1+0x1eef], %r2 diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp index 5d91805f478..041abdf7e35 100644 --- a/gas/testsuite/gas/bpf/bpf.exp +++ b/gas/testsuite/gas/bpf/bpf.exp @@ -34,6 +34,7 @@ if {[istarget bpf*-*-*]} { run_dump_test exit run_dump_test atomic run_dump_test atomic-pseudoc + run_dump_test atomic-v3 run_dump_test data run_dump_test pseudoc-normal @@ -48,6 +49,7 @@ if {[istarget bpf*-*-*]} { run_dump_test call-be run_dump_test exit-be run_dump_test atomic-be + run_dump_test atomic-v3-be run_dump_test data-be run_dump_test pseudoc-normal-be -- 2.30.2 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/4] gas: document V3 BPF atomic instructions in the GAS manual 2023-05-11 14:13 [PATCH 0/4] Add support for V3 BPF atomic instructions Jose E. Marchesi ` (2 preceding siblings ...) 2023-05-11 14:13 ` [PATCH 3/4] gas: add tests for BPF V3 " Jose E. Marchesi @ 2023-05-11 14:13 ` Jose E. Marchesi 3 siblings, 0 replies; 10+ messages in thread From: Jose E. Marchesi @ 2023-05-11 14:13 UTC (permalink / raw) To: binutils gas/ChangeLog: 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Opcodes): Document the V3 BPF atomic instructions. --- gas/ChangeLog | 5 +++++ gas/doc/c-bpf.texi | 56 +++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index a16647bb4a4..987b0c8704f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> + + * doc/c-bpf.texi (BPF Opcodes): Document the V3 BPF atomic + instructions. + 2023-05-10 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/atomic-v3.s: New file. diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 0756796adc9..917e0dc1628 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -377,14 +377,60 @@ Terminate the eBPF program. @subsubsection Atomic instructions -Atomic exchange-and-add instructions are provided in two flavors: one -for swapping 64-bit quantities and another for 32-bit quantities. +BPF provides a set of instructions to perform arithmetic and logical +operations on stored data atomically. These are: @table @code -@item xadddw [%d+offset16],%s -Exchange-and-add a 64-bit value at the specified location. @item xaddw [%d+offset16],%s -Exchange-and-add a 32-bit value at the specified location. +@itemx xadddw [%d+offset16],%s +Add @code{%s} to the 32 or 64 bit signed integer stored in the +specified memory location and store the result, atomically. +@item xorw [%d+offset16],%s +@itemx xordw [%d+offset16],%s +Perform a bit-wise or operation between @code{%s} and the 32 or 64 bit +signed integer stored in the specified memory location and store the +result, atomically. +@item xxorw [%d+offset16],%s +@itemx xxordw [%d+offset16],%s +Perform a bit-wise xor operation between @code{%s} and the 32 or 64 bit +signed integer stored in the specified memory location and store the +result, atomically. +@end table + +@noindent +Additionally, the following instructions allow to perform arithmetic +and logical operations on stored data and then fetching the original +stored value in a register, atomically: + +@table @code +@item xfaddw [%d+offset16],%s +@itemx xfadddw [%d+offset16],%s +Add @code{%s} to the 32 or 64 bit signed integer stored in the +specified memory location, store the result, and set @code{%s} to the +value originally stored in the memory location, atomically. +@item xforw [%d+offset16],%s +@itemx xfordw [%d+offset16],%s +Perform a bit-wise or operation between @code{%s} and the 32 or 64 bit +signed integer stored in the specified memory location, store the +result, and set @code{%s} to the value originally stored in the memory +location, atomically. +@item xfxorw [%d+offset16],%s +@itemx xfxordw [%d+offset16],%s +Perform a bit-wise xor operation between @code{%s} and the 32 or 64 +bit signed integer stored in the specified memory location, store the +result, and set @code{%s} to the value originally stored in the memory +location, atomically. +@item xchgw [%d+offset16],%s +@itemx xchgdw [%d+offset16],%s +Exchange the 32 or 64 bit values in @code{%s} and the specified memory +location, atomically. +@item xcmpw [%d+offset16],%s +@itemx xcmpdw [%d+offset16],%s +Compare and exchange operation. Compare the 32 or 64 bit value stored +in the specified memory location to the contents of the @code{%r0} +register. If they are equal, store @code{%s} in the memory location. +In any case, update @code{%r0} with the original contents of the +memory location. @end table @node BPF Pseudo-C Syntax -- 2.30.2 ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-07-22 6:54 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-05-11 14:13 [PATCH 0/4] Add support for V3 BPF atomic instructions Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 1/4] opcodes: use CGEN_INSN_LGUINT for base instructions Jose E. Marchesi 2023-05-11 16:05 ` Jan Beulich 2023-05-17 13:03 ` Nick Clifton 2023-05-17 14:03 ` Jose E. Marchesi 2023-07-21 22:34 ` David Faust 2023-07-22 6:53 ` Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 2/4] cpu: add V3 BPF atomic instructions Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 3/4] gas: add tests for BPF V3 " Jose E. Marchesi 2023-05-11 14:13 ` [PATCH 4/4] gas: document V3 BPF atomic instructions in the GAS manual Jose E. Marchesi
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