From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 00/18] x86: new .insn directive
Date: Mon, 6 Mar 2023 10:01:24 +0100 [thread overview]
Message-ID: <27acf170-e736-7616-b4a3-c76ea7bdbe32@suse.com> (raw)
In-Reply-To: <SA1PR11MB5946C160DEBE198D5431927AECB19@SA1PR11MB5946.namprd11.prod.outlook.com>
On 05.03.2023 11:07, Jiang, Haochen wrote:
>> 01: introduce .insn directive
>> 02: parse VEX and alike specifiers for .insn
>> 03: parse special opcode modifiers for .insn
>> 04: use set_rex_vrex() also for short-form handling
>> 05: move more disp processing out of md_assemble()
>> 06: adjust REX-prefix part of SSE2AVX test
>> 07: re-work build_modrm_byte()'s register assignment
>> 08: VexVVVV is now merely a boolean
>> 09: drop "shimm" special case template expansions
>> 10: AT&T: restrict recognition of the "absolute branch" prefix character
>> 11: process instruction operands for .insn
>> 12: decouple broadcast type and bytes fields
>> 13: handle EVEX Disp8 for .insn
>> 14: allow for multiple immediates in output_disp()
>> 15: handle immediate operands for .insn
>> 16: document .insn
>> 17: convert testcases to use .insn
>> 18: .insn example - VEX-encoded instructions of original Xeon Phi
>
> Since this is a complex feature, do you have a branch for those interested
> to test so that we could all give back some comments and see if there is
> something missing?
>
> I could also do that from scratch but I suppose it is much more easier since
> you have a branch.
No, sorry, my normal work env continues to be quilt based, and hence I'm not
really maintaining private git branches.
Jan
prev parent reply other threads:[~2023-03-06 9:01 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-03 12:54 Jan Beulich
2023-03-03 12:56 ` [PATCH 01/18] x86: introduce " Jan Beulich
2023-03-03 12:57 ` [PATCH 02/18] x86: parse VEX and alike specifiers for .insn Jan Beulich
2023-03-03 12:57 ` [PATCH 03/18] x86: parse special opcode modifiers " Jan Beulich
2023-03-03 12:58 ` [PATCH 04/18] x86: use set_rex_vrex() also for short-form handling Jan Beulich
2023-03-03 12:58 ` [PATCH 05/18] x86: move more disp processing out of md_assemble() Jan Beulich
2023-03-03 12:59 ` [PATCH 06/18] x86-64: adjust REX-prefix part of SSE2AVX test Jan Beulich
2023-03-03 13:00 ` [PATCH 07/18] x86: re-work build_modrm_byte()'s register assignment Jan Beulich
2023-03-03 13:00 ` [PATCH 08/18] x86: VexVVVV is now merely a boolean Jan Beulich
2023-03-03 13:01 ` [PATCH 09/18] x86: drop "shimm" special case template expansions Jan Beulich
2023-03-03 13:01 ` [PATCH 10/18] x86/AT&T: restrict recognition of the "absolute branch" prefix character Jan Beulich
2023-03-03 13:02 ` [PATCH 11/18] x86: process instruction operands for .insn Jan Beulich
2023-03-03 13:03 ` [PATCH 12/18] x86: decouple broadcast type and bytes fields Jan Beulich
2023-03-03 13:03 ` [PATCH 13/18] x86: handle EVEX Disp8 for .insn Jan Beulich
2023-03-03 13:04 ` [PATCH 14/18] x86: allow for multiple immediates in output_disp() Jan Beulich
2023-03-03 13:05 ` [PATCH 15/18] x86: handle immediate operands for .insn Jan Beulich
2023-03-03 13:05 ` [PATCH 16/18] x86: document .insn Jan Beulich
2023-03-03 13:06 ` [PATCH 17/18] x86: convert testcases to use .insn Jan Beulich
2023-03-03 13:06 ` [PATCH RFC 18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi Jan Beulich
2023-03-03 16:50 ` [PATCH 00/18] x86: new .insn directive H.J. Lu
2023-03-06 9:26 ` Jan Beulich
2023-03-07 20:33 ` H.J. Lu
2023-03-08 7:54 ` Jan Beulich
2023-03-08 8:09 ` Jiang, Haochen
2023-03-09 6:52 ` Kong, Lingling
2023-03-05 10:07 ` Jiang, Haochen
2023-03-06 9:01 ` Jan Beulich [this message]
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