public inbox for binutils@sourceware.org
 help / color / mirror / Atom feed
From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>,
	"Jiang, Haochen" <haochen.jiang@intel.com>
Subject: [PATCH 05/18] x86: move more disp processing out of md_assemble()
Date: Fri, 3 Mar 2023 13:58:33 +0100	[thread overview]
Message-ID: <34990244-84ae-bd27-04c3-1632ad5d7841@suse.com> (raw)
In-Reply-To: <764b9e03-18bd-6945-692f-a250522196ca@suse.com>

Put it in optimize_disp() such that it can then be re-used by s_insn().
The movement makes it necessary (or at least very desirable, to avoid
introducing a fragile cast) to convert to local variable to "unsigned",
which in turn requires an adjustment to the pre-existing loop header.

Having the caller pass in the specific template under consideration has
another benefit then: We can replace the two uses of current_templates
in the function as well, thus no longer looking at just some "related"
template. (This may allow further tightening, but if so that's to be the
subject of another change.)
---
Split from subsequent patch just to keep the other one's size under
control.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -166,7 +166,7 @@ static void swap_operands (void);
 static void swap_2_operands (unsigned int, unsigned int);
 static enum flag_code i386_addressing_mode (void);
 static void optimize_imm (void);
-static void optimize_disp (void);
+static bool optimize_disp (const insn_template *t);
 static const insn_template *match_template (char);
 static int check_string (void);
 static int process_suffix (void);
@@ -4995,42 +4995,8 @@ md_assemble (char *line)
   if (i.imm_operands)
     optimize_imm ();
 
-  if (i.disp_operands && !want_disp32 (t)
-      && (!t->opcode_modifier.jump
-	  || i.jumpabsolute || i.types[0].bitfield.baseindex))
-    {
-      for (j = 0; j < i.operands; ++j)
-	{
-	  const expressionS *exp = i.op[j].disps;
-
-	  if (!operand_type_check (i.types[j], disp))
-	    continue;
-
-	  if (exp->X_op != O_constant)
-	    continue;
-
-	  /* Since displacement is signed extended to 64bit, don't allow
-	     disp32 if it is out of range.  */
-	  if (fits_in_signed_long (exp->X_add_number))
-	    continue;
-
-	  i.types[j].bitfield.disp32 = 0;
-	  if (i.types[j].bitfield.baseindex)
-	    {
-	      as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"),
-		      (uint64_t) exp->X_add_number);
-	      return;
-	    }
-	}
-    }
-
-  /* Don't optimize displacement for movabs since it only takes 64bit
-     displacement.  */
-  if (i.disp_operands
-      && i.disp_encoding <= disp_encoding_8bit
-      && (flag_code != CODE_64BIT
-	  || strcmp (mnemonic, "movabs") != 0))
-    optimize_disp ();
+  if (i.disp_operands && !optimize_disp (t))
+    return;
 
   /* Next, we find a template that matches the given insn,
      making sure the overlap of the given operands types is consistent
@@ -6164,12 +6130,47 @@ optimize_imm (void)
 }
 
 /* Try to use the smallest displacement type too.  */
-static void
-optimize_disp (void)
+static bool
+optimize_disp (const insn_template *t)
 {
-  int op;
+  unsigned int op;
 
-  for (op = i.operands; --op >= 0;)
+  if (!want_disp32 (t)
+      && (!t->opcode_modifier.jump
+	  || i.jumpabsolute || i.types[0].bitfield.baseindex))
+    {
+      for (op = 0; op < i.operands; ++op)
+	{
+	  const expressionS *exp = i.op[op].disps;
+
+	  if (!operand_type_check (i.types[op], disp))
+	    continue;
+
+	  if (exp->X_op != O_constant)
+	    continue;
+
+	  /* Since displacement is signed extended to 64bit, don't allow
+	     disp32 if it is out of range.  */
+	  if (fits_in_signed_long (exp->X_add_number))
+	    continue;
+
+	  i.types[op].bitfield.disp32 = 0;
+	  if (i.types[op].bitfield.baseindex)
+	    {
+	      as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"),
+		      (uint64_t) exp->X_add_number);
+	      return false;
+	    }
+	}
+    }
+
+  /* Don't optimize displacement for movabs since it only takes 64bit
+     displacement.  */
+  if (i.disp_encoding > disp_encoding_8bit
+      || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs))
+    return true;
+
+  for (op = i.operands; op-- > 0;)
     if (operand_type_check (i.types[op], disp))
       {
 	if (i.op[op].disps->X_op == O_constant)
@@ -6198,8 +6199,8 @@ optimize_disp (void)
 	    /* Optimize 64-bit displacement to 32-bit for 64-bit BFD.  */
 	    if ((flag_code != CODE_64BIT
 		 ? i.types[op].bitfield.disp32
-		 : want_disp32 (current_templates->start)
-		   && (!current_templates->start->opcode_modifier.jump
+		 : want_disp32 (t)
+		   && (!t->opcode_modifier.jump
 		       || i.jumpabsolute || i.types[op].bitfield.baseindex))
 		&& fits_in_unsigned_long (op_disp))
 	      {
@@ -6235,6 +6236,8 @@ optimize_disp (void)
 	  /* We only support 64bit displacement on constants.  */
 	  i.types[op].bitfield.disp64 = 0;
       }
+
+  return true;
 }
 
 /* Return 1 if there is a match in broadcast bytes between operand


  parent reply	other threads:[~2023-03-03 12:58 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 12:54 [PATCH 00/18] x86: new .insn directive Jan Beulich
2023-03-03 12:56 ` [PATCH 01/18] x86: introduce " Jan Beulich
2023-03-03 12:57 ` [PATCH 02/18] x86: parse VEX and alike specifiers for .insn Jan Beulich
2023-03-03 12:57 ` [PATCH 03/18] x86: parse special opcode modifiers " Jan Beulich
2023-03-03 12:58 ` [PATCH 04/18] x86: use set_rex_vrex() also for short-form handling Jan Beulich
2023-03-03 12:58 ` Jan Beulich [this message]
2023-03-03 12:59 ` [PATCH 06/18] x86-64: adjust REX-prefix part of SSE2AVX test Jan Beulich
2023-03-03 13:00 ` [PATCH 07/18] x86: re-work build_modrm_byte()'s register assignment Jan Beulich
2023-03-03 13:00 ` [PATCH 08/18] x86: VexVVVV is now merely a boolean Jan Beulich
2023-03-03 13:01 ` [PATCH 09/18] x86: drop "shimm" special case template expansions Jan Beulich
2023-03-03 13:01 ` [PATCH 10/18] x86/AT&T: restrict recognition of the "absolute branch" prefix character Jan Beulich
2023-03-03 13:02 ` [PATCH 11/18] x86: process instruction operands for .insn Jan Beulich
2023-03-03 13:03 ` [PATCH 12/18] x86: decouple broadcast type and bytes fields Jan Beulich
2023-03-03 13:03 ` [PATCH 13/18] x86: handle EVEX Disp8 for .insn Jan Beulich
2023-03-03 13:04 ` [PATCH 14/18] x86: allow for multiple immediates in output_disp() Jan Beulich
2023-03-03 13:05 ` [PATCH 15/18] x86: handle immediate operands for .insn Jan Beulich
2023-03-03 13:05 ` [PATCH 16/18] x86: document .insn Jan Beulich
2023-03-03 13:06 ` [PATCH 17/18] x86: convert testcases to use .insn Jan Beulich
2023-03-03 13:06 ` [PATCH RFC 18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi Jan Beulich
2023-03-03 16:50 ` [PATCH 00/18] x86: new .insn directive H.J. Lu
2023-03-06  9:26   ` Jan Beulich
2023-03-07 20:33     ` H.J. Lu
2023-03-08  7:54       ` Jan Beulich
2023-03-08  8:09         ` Jiang, Haochen
2023-03-09  6:52           ` Kong, Lingling
2023-03-05 10:07 ` Jiang, Haochen
2023-03-06  9:01   ` Jan Beulich

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=34990244-84ae-bd27-04c3-1632ad5d7841@suse.com \
    --to=jbeulich@suse.com \
    --cc=binutils@sourceware.org \
    --cc=haochen.jiang@intel.com \
    --cc=hjl.tools@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).