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From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>,
	"Jiang, Haochen" <haochen.jiang@intel.com>
Subject: Re: [PATCH 00/18] x86: new .insn directive
Date: Tue, 7 Mar 2023 12:33:42 -0800	[thread overview]
Message-ID: <CAMe9rOqO0t8F-oAcW51Ko=02N3Qe+6AuTvmoBq+RG3EkfSKWxw@mail.gmail.com> (raw)
In-Reply-To: <b0bd32d4-4a80-c8f4-1dfe-fe6315859e9f@suse.com>

On Mon, Mar 6, 2023 at 1:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 03.03.2023 17:50, H.J. Lu wrote:
> > X86 encoding scheme is quite complex.  It may get even more complex in
> > the future.
>
> Indeed. Also some complexities did exist only transiently, like AMD's
> DREX. MVEX is mentioned in the series, and I'm not sure whether to
> call this "historic" as well. However, ...
>
> >  I suggest we wait for a while so that we can get clear pictures
> > what the future encoding scheme looks like.
>
> ... I have to admit that I'm puzzled by this suggestion. The rate at
> which new encoding schemes appear is pretty low. So unless you know
> of something to see the (public) light of day soon, I wonder what
> meaning you assign to "a while". The plan certainly is for this work
> to land well in time for 2.40, unless there are clear technical
> issues speaking against it. In no event do I plan to wait very long
> with committing not directly .insn-related changes in the series,
> like patches 06 ... 09 or even 10, and maybe 04 as well as 12.
>
> I shall perhaps also add that I view entirely new encoding schemes
> as less of a problem - support for them can be added to .insn
> handling incrementally. What could be more problematic are changes
> to one of the existing schemes.
>

We will evaluate if these changes will cause any potential issues for
the future.


-- 
H.J.

  reply	other threads:[~2023-03-07 20:34 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03 12:54 Jan Beulich
2023-03-03 12:56 ` [PATCH 01/18] x86: introduce " Jan Beulich
2023-03-03 12:57 ` [PATCH 02/18] x86: parse VEX and alike specifiers for .insn Jan Beulich
2023-03-03 12:57 ` [PATCH 03/18] x86: parse special opcode modifiers " Jan Beulich
2023-03-03 12:58 ` [PATCH 04/18] x86: use set_rex_vrex() also for short-form handling Jan Beulich
2023-03-03 12:58 ` [PATCH 05/18] x86: move more disp processing out of md_assemble() Jan Beulich
2023-03-03 12:59 ` [PATCH 06/18] x86-64: adjust REX-prefix part of SSE2AVX test Jan Beulich
2023-03-03 13:00 ` [PATCH 07/18] x86: re-work build_modrm_byte()'s register assignment Jan Beulich
2023-03-03 13:00 ` [PATCH 08/18] x86: VexVVVV is now merely a boolean Jan Beulich
2023-03-03 13:01 ` [PATCH 09/18] x86: drop "shimm" special case template expansions Jan Beulich
2023-03-03 13:01 ` [PATCH 10/18] x86/AT&T: restrict recognition of the "absolute branch" prefix character Jan Beulich
2023-03-03 13:02 ` [PATCH 11/18] x86: process instruction operands for .insn Jan Beulich
2023-03-03 13:03 ` [PATCH 12/18] x86: decouple broadcast type and bytes fields Jan Beulich
2023-03-03 13:03 ` [PATCH 13/18] x86: handle EVEX Disp8 for .insn Jan Beulich
2023-03-03 13:04 ` [PATCH 14/18] x86: allow for multiple immediates in output_disp() Jan Beulich
2023-03-03 13:05 ` [PATCH 15/18] x86: handle immediate operands for .insn Jan Beulich
2023-03-03 13:05 ` [PATCH 16/18] x86: document .insn Jan Beulich
2023-03-03 13:06 ` [PATCH 17/18] x86: convert testcases to use .insn Jan Beulich
2023-03-03 13:06 ` [PATCH RFC 18/18] x86: .insn example - VEX-encoded instructions of original Xeon Phi Jan Beulich
2023-03-03 16:50 ` [PATCH 00/18] x86: new .insn directive H.J. Lu
2023-03-06  9:26   ` Jan Beulich
2023-03-07 20:33     ` H.J. Lu [this message]
2023-03-08  7:54       ` Jan Beulich
2023-03-08  8:09         ` Jiang, Haochen
2023-03-09  6:52           ` Kong, Lingling
2023-03-05 10:07 ` Jiang, Haochen
2023-03-06  9:01   ` Jan Beulich

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