* [PATCH v1] LoongArch: Scan all illegal operand instructions without interruption
@ 2024-03-05 11:35 Lulu Cai
2024-03-05 18:43 ` WANG Xuerui
0 siblings, 1 reply; 3+ messages in thread
From: Lulu Cai @ 2024-03-05 11:35 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang, Lulu Cai
Currently, gas will exit immediately and report an error when
it sees illegal operands, and will not process the remaining
instructions. Replace as_fatal with as_bad to check for all
illegal operands.
Add test cases for illegal operands of some instructions.
---
gas/config/tc-loongarch.c | 11 +-
.../gas/loongarch/check_bstrins-pick.d | 18 +++
.../gas/loongarch/check_bstrins-pick.s | 9 ++
gas/testsuite/gas/loongarch/illegal-oprand.l | 113 +++++++++++++++++
gas/testsuite/gas/loongarch/illegal-oprand.s | 117 ++++++++++++++++++
gas/testsuite/gas/loongarch/loongarch.exp | 4 +
gas/testsuite/gas/loongarch/lvz-lbt.d | 2 +-
gas/testsuite/gas/loongarch/lvz-lbt.s | 2 +-
8 files changed, 269 insertions(+), 7 deletions(-)
create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.d
create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.s
create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.l
create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.s
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index de92366eda4..d76d7894657 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -946,8 +946,8 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip)
/* For AMO insn amswap.[wd], amadd.[wd], etc. */
if (ip->args[0] != 0
&& (ip->args[0] == ip->args[1] || ip->args[0] == ip->args[2]))
- as_fatal (_("AMO insns require rd != base && rd != rt"
- " when rd isn't $r0"));
+ as_bad (_("AMO insns require rd != rj && rd != rk"
+ " when rd isn't r0"));
}
else if ((ip->insn->mask == 0xffe08000
/* bstrins.w rd, rj, msbw, lsbw */
@@ -958,12 +958,13 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip)
{
/* For bstr(ins|pick).[wd]. */
if (ip->args[2] < ip->args[3])
- as_fatal (_("bstr(ins|pick).[wd] require msbd >= lsbd"));
+ as_bad (_("bstr(ins|pick).[wd] require msbd >= lsbd"));
}
else if (ip->insn->mask != 0 && (ip->insn_bin & 0xfe0003c0) == 0x04000000
/* csrxchg rd, rj, csr_num */
- && (strcmp ("csrxchg", ip->name) == 0))
- as_fatal (_("csrxchg require rj != $r0 && rj != $r1"));
+ && (strcmp ("csrxchg", ip->name) == 0
+ || strcmp ("gcsrxchg", ip->name) == 0))
+ as_bad (_("g?csrxchg require rj != r0 && rj != r1"));
return ret;
}
diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.d b/gas/testsuite/gas/loongarch/check_bstrins-pick.d
new file mode 100644
index 00000000000..7575be1926e
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -d
+#skip: loongarch32-*-*
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <.*>:
+ 0: 00682041 bstrins\.w \$ra, \$tp, 0x8, 0x8
+ 4: 00882041 bstrins\.d \$ra, \$tp, 0x8, 0x8
+ 8: 0068a041 bstrpick\.w \$ra, \$tp, 0x8, 0x8
+ c: 00c82041 bstrpick\.d \$ra, \$tp, 0x8, 0x8
+ 10: 00680041 bstrins\.w \$ra, \$tp, 0x8, 0x0
+ 14: 00880041 bstrins\.d \$ra, \$tp, 0x8, 0x0
+ 18: 00688041 bstrpick\.w \$ra, \$tp, 0x8, 0x0
+ 1c: 00c80041 bstrpick\.d \$ra, \$tp, 0x8, 0x0
diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.s b/gas/testsuite/gas/loongarch/check_bstrins-pick.s
new file mode 100644
index 00000000000..0decaf98ea5
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.s
@@ -0,0 +1,9 @@
+bstrins.w $r1,$r2,8,8
+bstrins.d $r1,$r2,8,8
+bstrpick.w $r1,$r2,8,8
+bstrpick.d $r1,$r2,8,8
+
+bstrins.w $r1,$r2,8,0
+bstrins.d $r1,$r2,8,0
+bstrpick.w $r1,$r2,8,0
+bstrpick.d $r1,$r2,8,0
diff --git a/gas/testsuite/gas/loongarch/illegal-oprand.l b/gas/testsuite/gas/loongarch/illegal-oprand.l
new file mode 100644
index 00000000000..e6553abe7b4
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/illegal-oprand.l
@@ -0,0 +1,113 @@
+.*: Assembler messages:
+.*:2: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:3: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:4: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:5: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:6: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:7: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:8: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:9: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:10: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:11: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:12: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:13: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:14: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:15: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:16: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:17: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:18: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:19: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:20: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:21: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:22: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:23: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:24: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:25: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:26: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:27: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:28: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:29: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:30: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:31: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:32: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:33: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:34: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:35: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:36: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:37: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:38: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:39: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:40: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:41: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:42: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:43: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:44: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:45: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:46: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:47: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:48: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:49: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:50: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:51: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:52: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:53: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:54: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:55: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:56: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:57: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:58: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:59: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:60: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:61: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:62: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:63: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:64: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:65: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:66: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:67: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:68: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:69: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:70: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:71: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:72: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:73: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:74: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:75: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:76: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:77: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:78: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:79: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:80: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:81: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:82: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:83: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:84: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:85: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:86: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:87: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:88: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:89: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:90: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:91: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:92: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:93: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:94: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:95: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:96: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:97: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:98: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:99: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:100: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:101: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:102: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:103: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:104: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:105: Error: AMO insns require rd != rj && rd != rk when rd isn't r0
+.*:108: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd
+.*:109: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd
+.*:110: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd
+.*:111: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd
+.*:114: Error: g\?csrxchg require rj != r0 && rj != r1
+.*:115: Error: g\?csrxchg require rj != r0 && rj != r1
+.*:116: Error: g\?csrxchg require rj != r0 && rj != r1
+.*:117: Error: g\?csrxchg require rj != r0 && rj != r1
diff --git a/gas/testsuite/gas/loongarch/illegal-oprand.s b/gas/testsuite/gas/loongarch/illegal-oprand.s
new file mode 100644
index 00000000000..3860539d242
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/illegal-oprand.s
@@ -0,0 +1,117 @@
+# Illegal operand of atomic memory access instruction.
+amcas.b $r1,$r1,$r2
+amcas.b $r1,$r2,$r1
+amcas.h $r1,$r1,$r2
+amcas.h $r1,$r2,$r1
+amcas.w $r1,$r1,$r2
+amcas.w $r1,$r2,$r1
+amcas.d $r1,$r1,$r2
+amcas.d $r1,$r2,$r1
+amcas_db.b $r1,$r1,$r2
+amcas_db.b $r1,$r2,$r1
+amcas_db.h $r1,$r1,$r2
+amcas_db.h $r1,$r2,$r1
+amcas_db.w $r1,$r1,$r2
+amcas_db.w $r1,$r2,$r1
+amcas_db.d $r1,$r1,$r2
+amcas_db.d $r1,$r2,$r1
+amswap.b $r1,$r1,$r2
+amswap.b $r1,$r2,$r1
+amswap.h $r1,$r1,$r2
+amswap.h $r1,$r2,$r1
+amadd.b $r1,$r1,$r2
+amadd.b $r1,$r2,$r1
+amadd.h $r1,$r1,$r2
+amadd.h $r1,$r2,$r1
+amswap_db.b $r1,$r1,$r2
+amswap_db.b $r1,$r2,$r1
+amswap_db.h $r1,$r1,$r2
+amswap_db.h $r1,$r2,$r1
+amadd_db.b $r1,$r1,$r2
+amadd_db.b $r1,$r2,$r1
+amadd_db.h $r1,$r1,$r2
+amadd_db.h $r1,$r2,$r1
+amswap.w $r1,$r1,$r2
+amswap.w $r1,$r2,$r1
+amswap.d $r1,$r1,$r2
+amswap.d $r1,$r2,$r1
+amadd.w $r1,$r1,$r2
+amadd.w $r1,$r2,$r1
+amadd.d $r1,$r1,$r2
+amadd.d $r1,$r2,$r1
+amand.w $r1,$r1,$r2
+amand.w $r1,$r2,$r1
+amand.d $r1,$r1,$r2
+amand.d $r1,$r2,$r1
+amor.w $r1,$r1,$r2
+amor.w $r1,$r2,$r1
+amor.d $r1,$r1,$r2
+amor.d $r1,$r2,$r1
+amxor.w $r1,$r1,$r2
+amxor.w $r1,$r2,$r1
+amxor.d $r1,$r1,$r2
+amxor.d $r1,$r2,$r1
+ammax.w $r1,$r1,$r2
+ammax.w $r1,$r2,$r1
+ammax.d $r1,$r1,$r2
+ammax.d $r1,$r2,$r1
+ammin.w $r1,$r1,$r2
+ammin.w $r1,$r2,$r1
+ammin.d $r1,$r1,$r2
+ammin.d $r1,$r2,$r1
+ammax.wu $r1,$r1,$r2
+ammax.wu $r1,$r2,$r1
+ammax.du $r1,$r1,$r2
+ammax.du $r1,$r2,$r1
+ammin.wu $r1,$r1,$r2
+ammin.wu $r1,$r2,$r1
+ammin.du $r1,$r1,$r2
+ammin.du $r1,$r2,$r1
+amswap_db.w $r1,$r1,$r2
+amswap_db.w $r1,$r2,$r1
+amswap_db.d $r1,$r1,$r2
+amswap_db.d $r1,$r2,$r1
+amadd_db.w $r1,$r1,$r2
+amadd_db.w $r1,$r2,$r1
+amadd_db.d $r1,$r1,$r2
+amadd_db.d $r1,$r2,$r1
+amand_db.w $r1,$r1,$r2
+amand_db.w $r1,$r2,$r1
+amand_db.d $r1,$r1,$r2
+amand_db.d $r1,$r2,$r1
+amor_db.w $r1,$r1,$r2
+amor_db.w $r1,$r2,$r1
+amor_db.d $r1,$r1,$r2
+amor_db.d $r1,$r2,$r1
+amxor_db.w $r1,$r1,$r2
+amxor_db.w $r1,$r2,$r1
+amxor_db.d $r1,$r1,$r2
+amxor_db.d $r1,$r2,$r1
+ammax_db.w $r1,$r1,$r2
+ammax_db.w $r1,$r2,$r1
+ammax_db.d $r1,$r1,$r2
+ammax_db.d $r1,$r2,$r1
+ammin_db.w $r1,$r1,$r2
+ammin_db.w $r1,$r2,$r1
+ammin_db.d $r1,$r1,$r2
+ammin_db.d $r1,$r2,$r1
+ammax_db.wu $r1,$r1,$r2
+ammax_db.wu $r1,$r2,$r1
+ammax_db.du $r1,$r1,$r2
+ammax_db.du $r1,$r2,$r1
+ammin_db.wu $r1,$r1,$r2
+ammin_db.wu $r1,$r2,$r1
+ammin_db.du $r1,$r1,$r2
+ammin_db.du $r1,$r2,$r1
+
+# Illegal operand of bstr(ins|pick).[wd]
+bstrins.w $r1,$r2,0,8
+bstrins.d $r1,$r2,0,8
+bstrpick.w $r1,$r2,0,8
+bstrpick.d $r1,$r2,0,8
+
+# Illegal operand of csrxchg/gcsrxchg
+csrxchg $r0,$r0,1
+csrxchg $r0,$r1,1
+gcsrxchg $r0,$r0,1
+gcsrxchg $r0,$r1,1
diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp
index 422b858917e..8a7c9c141a5 100644
--- a/gas/testsuite/gas/loongarch/loongarch.exp
+++ b/gas/testsuite/gas/loongarch/loongarch.exp
@@ -32,4 +32,8 @@ if [istarget loongarch*-*-*] {
run_list_test "align"
run_list_test "reg-s9"
+
+ if [istarget loongarch64-*-*] {
+ run_list_test "illegal-oprand"
+ }
}
diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.d b/gas/testsuite/gas/loongarch/lvz-lbt.d
index f89707762dc..760066a023a 100644
--- a/gas/testsuite/gas/loongarch/lvz-lbt.d
+++ b/gas/testsuite/gas/loongarch/lvz-lbt.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]*0:[ ]*05000400[ ]*gcsrrd[ ]*\$zero,[ ]*0x1[ ]*
[ ]*4:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]*
-[ ]*8:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*8:[ ]*05000440[ ]*gcsrxchg[ ]*\$zero,[ ]*\$tp,[ ]*0x1[ ]*
[ ]*c:[ ]*06482401[ ]*gtlbflush[ ]*
[ ]*10:[ ]*002b8001[ ]*hvcl[ ]*0x1[ ]*
[ ]*14:[ ]*00000820[ ]*movgr2scr[ ]*\$scr0,[ ]*\$ra[ ]*
diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.s b/gas/testsuite/gas/loongarch/lvz-lbt.s
index 64469a4362d..2e5089e4e5d 100644
--- a/gas/testsuite/gas/loongarch/lvz-lbt.s
+++ b/gas/testsuite/gas/loongarch/lvz-lbt.s
@@ -1,6 +1,6 @@
gcsrrd $r0, 1
gcsrwr $r0, 1
-gcsrxchg $r0, $r1, 1
+gcsrxchg $r0, $r2, 1
gtlbflush
hvcl 1
movgr2scr $scr0, $r1
--
2.36.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] LoongArch: Scan all illegal operand instructions without interruption
2024-03-05 11:35 [PATCH v1] LoongArch: Scan all illegal operand instructions without interruption Lulu Cai
@ 2024-03-05 18:43 ` WANG Xuerui
2024-03-06 1:58 ` Lulu Cai
0 siblings, 1 reply; 3+ messages in thread
From: WANG Xuerui @ 2024-03-05 18:43 UTC (permalink / raw)
To: Lulu Cai, binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang
On 3/5/24 19:35, Lulu Cai wrote:
> Currently, gas will exit immediately and report an error when
> it sees illegal operands, and will not process the remaining
> instructions. Replace as_fatal with as_bad to check for all
> illegal operands.
>
> Add test cases for illegal operands of some instructions.
> ---
> gas/config/tc-loongarch.c | 11 +-
> .../gas/loongarch/check_bstrins-pick.d | 18 +++
> .../gas/loongarch/check_bstrins-pick.s | 9 ++
> gas/testsuite/gas/loongarch/illegal-oprand.l | 113 +++++++++++++++++
> gas/testsuite/gas/loongarch/illegal-oprand.s | 117 ++++++++++++++++++
The filename contains a typo: "operand" instead of "oprand".
> gas/testsuite/gas/loongarch/loongarch.exp | 4 +
> gas/testsuite/gas/loongarch/lvz-lbt.d | 2 +-
> gas/testsuite/gas/loongarch/lvz-lbt.s | 2 +-
> 8 files changed, 269 insertions(+), 7 deletions(-)
> create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.d
> create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.s
> create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.l
> create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.s
Other than that, the code changes LGTM, thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] LoongArch: Scan all illegal operand instructions without interruption
2024-03-05 18:43 ` WANG Xuerui
@ 2024-03-06 1:58 ` Lulu Cai
0 siblings, 0 replies; 3+ messages in thread
From: Lulu Cai @ 2024-03-06 1:58 UTC (permalink / raw)
To: WANG Xuerui, binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
maskray, luweining, wanglei, hejinyang
On 3/6/24 2:43 AM, WANG Xuerui wrote:
> On 3/5/24 19:35, Lulu Cai wrote:
>> Currently, gas will exit immediately and report an error when
>> it sees illegal operands, and will not process the remaining
>> instructions. Replace as_fatal with as_bad to check for all
>> illegal operands.
>>
>> Add test cases for illegal operands of some instructions.
>> ---
>> gas/config/tc-loongarch.c | 11 +-
>> .../gas/loongarch/check_bstrins-pick.d | 18 +++
>> .../gas/loongarch/check_bstrins-pick.s | 9 ++
>> gas/testsuite/gas/loongarch/illegal-oprand.l | 113 +++++++++++++++++
>> gas/testsuite/gas/loongarch/illegal-oprand.s | 117 ++++++++++++++++++
>
> The filename contains a typo: "operand" instead of "oprand".
>
Thanks for the reminder, I will revise it later.
>> gas/testsuite/gas/loongarch/loongarch.exp | 4 +
>> gas/testsuite/gas/loongarch/lvz-lbt.d | 2 +-
>> gas/testsuite/gas/loongarch/lvz-lbt.s | 2 +-
>> 8 files changed, 269 insertions(+), 7 deletions(-)
>> create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.d
>> create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.s
>> create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.l
>> create mode 100644 gas/testsuite/gas/loongarch/illegal-oprand.s
> Other than that, the code changes LGTM, thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-03-06 1:58 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2024-03-05 11:35 [PATCH v1] LoongArch: Scan all illegal operand instructions without interruption Lulu Cai
2024-03-05 18:43 ` WANG Xuerui
2024-03-06 1:58 ` Lulu Cai
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