* [PATCH 0/2] x86: adjust disassembling of selector-access insns
@ 2023-07-14 10:01 Jan Beulich
2023-07-14 10:02 ` [PATCH 1/2] x86: simplify disassembly of LAR/LSL Jan Beulich
2023-07-14 10:02 ` [PATCH 2/2] x86: adjust disassembly of insns operating on selector values Jan Beulich
0 siblings, 2 replies; 6+ messages in thread
From: Jan Beulich @ 2023-07-14 10:01 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
While the first patch is merely simplifying things (back), the latter
(slightly RFC) improves consistency on the disassembler side along the
lines of earlier improvements (c9f5b96bdab0 "x86: correct handling of
LAR and LSL") and ones done only on the assembler side (5eeeafe0a688
"x86: have insns acting on segment selector values allow for consistent
operands").
1: simplify disassembly of LAR/LSL
2: adjust disassembly of insns operating on selector values
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] x86: simplify disassembly of LAR/LSL
2023-07-14 10:01 [PATCH 0/2] x86: adjust disassembling of selector-access insns Jan Beulich
@ 2023-07-14 10:02 ` Jan Beulich
2023-07-14 10:02 ` [PATCH 2/2] x86: adjust disassembly of insns operating on selector values Jan Beulich
1 sibling, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2023-07-14 10:02 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
For whatever reason in c9f5b96bdab0 ("x86: correct handling of LAR and
LSL") I didn't realize that we can easily use Sv instead of going
through mod_table[]. Redo this aspect of that change.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -867,8 +867,6 @@ enum
MOD_0F01_REG_3,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
- MOD_0F02,
- MOD_0F03,
MOD_0F12_PREFIX_0,
MOD_0F16_PREFIX_0,
MOD_0F18_REG_0,
@@ -2018,8 +2016,8 @@ static const struct dis386 dis386_twobyt
/* 00 */
{ REG_TABLE (REG_0F00 ) },
{ REG_TABLE (REG_0F01 ) },
- { MOD_TABLE (MOD_0F02) },
- { MOD_TABLE (MOD_0F03) },
+ { "larS", { Gv, Sv }, 0 },
+ { "lslS", { Gv, Sv }, 0 },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
@@ -7895,16 +7893,6 @@ static const struct dis386 mod_table[][2
{ RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
- /* MOD_0F02 */
- { "larS", { Gv, Mw }, 0 },
- { "larS", { Gv, Ev }, 0 },
- },
- {
- /* MOD_0F03 */
- { "lslS", { Gv, Mw }, 0 },
- { "lslS", { Gv, Ev }, 0 },
- },
- {
/* MOD_0F12_PREFIX_0 */
{ "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
{ "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] x86: adjust disassembly of insns operating on selector values
2023-07-14 10:01 [PATCH 0/2] x86: adjust disassembling of selector-access insns Jan Beulich
2023-07-14 10:02 ` [PATCH 1/2] x86: simplify disassembly of LAR/LSL Jan Beulich
@ 2023-07-14 10:02 ` Jan Beulich
2023-07-17 2:04 ` Jiang, Haochen
1 sibling, 1 reply; 6+ messages in thread
From: Jan Beulich @ 2023-07-14 10:02 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
Bring disassembly back in line with what the assembler accepts, thus
also making it self-consistent (with, in particular selector load/store
insns). While there further add D to all affected insns except ARPL
(where S is used, matching LAR/LSL), to also behave correctly in suffix-
always mode.
While there also hook up the Intel variant of the LKGS test.
---
For ARPL it may be worth to consider to slightly deviate from the
overall goal of having consistent output.
--- a/gas/testsuite/gas/i386/i386.d
+++ b/gas/testsuite/gas/i386/i386.d
@@ -61,45 +61,45 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%eax\)
-[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
-[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
-[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
-[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
+[ ]*[a-f0-9]+: 63 ca arpl %ecx,%edx
+[ ]*[a-f0-9]+: 63 ca arpl %ecx,%edx
+[ ]*[a-f0-9]+: 63 0a arpl %ecx,\(%edx\)
+[ ]*[a-f0-9]+: 63 0a arpl %ecx,\(%edx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
-[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
-[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
-[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
-[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
-[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
-[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 d1 arpl %edx,%ecx
+[ ]*[a-f0-9]+: 63 d1 arpl %edx,%ecx
+[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %edx,\(%ecx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
@@ -107,16 +107,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
#pass
--- a/gas/testsuite/gas/i386/i386-intel.d
+++ b/gas/testsuite/gas/i386/i386-intel.d
@@ -62,45 +62,45 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[eax\],eax
-[ ]*[a-f0-9]+: 63 ca arpl dx,cx
-[ ]*[a-f0-9]+: 63 ca arpl dx,cx
-[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
-[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
+[ ]*[a-f0-9]+: 63 ca arpl edx,ecx
+[ ]*[a-f0-9]+: 63 ca arpl edx,ecx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],ecx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],ecx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
-[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
-[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
-[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
-[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
-[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
-[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 d1 arpl ecx,edx
+[ ]*[a-f0-9]+: 63 d1 arpl ecx,edx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],edx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
@@ -108,16 +108,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
#pass
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -102,7 +102,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 60 [ ]*pusha
[ ]*[a-f0-9]+: 61 [ ]*popa
[ ]*[a-f0-9]+: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\)
-[ ]*[a-f0-9]+: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\)
+[ ]*[a-f0-9]+: 63 90 90 90 90 90 [ ]*arpl %edx,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 68 90 90 90 90 [ ]*push \$0x90909090
[ ]*[a-f0-9]+: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 6a 90 [ ]*push \$0xffffff90
--- a/gas/testsuite/gas/i386/intel-intel.d
+++ b/gas/testsuite/gas/i386/intel-intel.d
@@ -103,7 +103,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 60 + pusha
[ ]*[a-f0-9]+: 61 + popa
[ ]*[a-f0-9]+: 62 90 90 90 90 90 + bound edx,QWORD PTR \[eax-0x6f6f6f70\]
-[ ]*[a-f0-9]+: 63 90 90 90 90 90 + arpl WORD PTR \[eax-0x6f6f6f70\],dx
+[ ]*[a-f0-9]+: 63 90 90 90 90 90 + arpl WORD PTR \[eax-0x6f6f6f70\],edx
[ ]*[a-f0-9]+: 68 90 90 90 90 + push 0x90909090
[ ]*[a-f0-9]+: 69 90 90 90 90 90 90 90 90 90 imul edx,DWORD PTR \[eax-0x6f6f6f70\],0x90909090
[ ]*[a-f0-9]+: 6a 90 + push 0xffffff90
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -101,7 +101,7 @@ Disassembly of section .text:
123: 60 [ ]*pusha
124: 61 [ ]*popa
125: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\)
- 12b: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\)
+ 12b: 63 90 90 90 90 90 [ ]*arpl %edx,-0x6f6f6f70\(%eax\)
131: 68 90 90 90 90 [ ]*push \$0x90909090
136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx
140: 6a 90 [ ]*push \$0xffffff90
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -102,7 +102,7 @@ Disassembly of section .text:
*[0-9a-f]+: 60[ ]+pusha
*[0-9a-f]+: 61[ ]+popa
*[0-9a-f]+: 62 90 90 90 90 90[ ]+bound[ ]+edx,(QWORD PTR )?\[eax-0x6f6f6f70\]
- *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],edx
*[0-9a-f]+: 68 90 90 90 90[ ]+push[ ]+0x90909090
*[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imul[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0x90909090
*[0-9a-f]+: 6a 90[ ]+push[ ]+0xffffff90
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -102,7 +102,7 @@ Disassembly of section .text:
*[0-9a-f]+: 60[ ]+pushal
*[0-9a-f]+: 61[ ]+popal
*[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\)
- *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpll[ ]+%edx,-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090
*[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[ ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90
@@ -248,7 +248,7 @@ Disassembly of section .text:
*[0-9a-f]+: fc[ ]+cld
*[0-9a-f]+: fd[ ]+std
*[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
- *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -437,6 +437,7 @@ run_dump_test "x86-64-amx-complex-bad"
run_list_test "x86-64-amx-complex-inval"
run_dump_test "x86-64-fred"
run_dump_test "x86-64-lkgs"
+run_dump_test "x86-64-lkgs-intel"
run_list_test "x86-64-lkgs-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
--- a/gas/testsuite/gas/i386/x86-64-lkgs.d
+++ b/gas/testsuite/gas/i386/x86-64-lkgs.d
@@ -8,16 +8,16 @@
Disassembly of section \.text:
0+ <_start>:
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\)
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\)
\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\)
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\)
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\)
--- a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
@@ -8,16 +8,16 @@
Disassembly of section \.text:
0+ <_start>:
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\]
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\]
\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\]
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\]
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\]
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -266,9 +266,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
@@ -278,17 +278,17 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
@@ -298,9 +298,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %edx
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
@@ -311,19 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
-[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %edx
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %edx
[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
-[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
+[ ]*[a-f0-9]+: 0f 00 ea verw %edx
[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
#pass
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -266,9 +266,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
@@ -278,17 +278,17 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
@@ -298,9 +298,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
-[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt edx
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
@@ -311,19 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
-[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
+[ ]*[a-f0-9]+: 0f 00 da ltr edx
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
-[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
+[ ]*[a-f0-9]+: 0f 00 e2 verr edx
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
-[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
+[ ]*[a-f0-9]+: 0f 00 ea verw edx
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
#pass
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2625,10 +2625,10 @@ static const struct dis386 reg_table[][8
{
{ "sldtD", { Sv }, 0 },
{ "strD", { Sv }, 0 },
- { "lldt", { Ew }, 0 },
- { "ltr", { Ew }, 0 },
- { "verr", { Ew }, 0 },
- { "verw", { Ew }, 0 },
+ { "lldtD", { Sv }, 0 },
+ { "ltrD", { Sv }, 0 },
+ { "verrD", { Sv }, 0 },
+ { "verwD", { Sv }, 0 },
{ X86_64_TABLE (X86_64_0F00_REG_6) },
{ Bad_Opcode },
},
@@ -2875,7 +2875,7 @@ static const struct dis386 prefix_table[
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "lkgs", { Ew }, 0 },
+ { "lkgsD", { Sv }, 0 },
},
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
@@ -4017,7 +4017,7 @@ static const struct dis386 x86_64_table[
/* X86_64_63 */
{
- { "arpl", { Ew, Gw }, 0 },
+ { "arplS", { Sv, Gv }, 0 },
{ "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 2/2] x86: adjust disassembly of insns operating on selector values
2023-07-14 10:02 ` [PATCH 2/2] x86: adjust disassembly of insns operating on selector values Jan Beulich
@ 2023-07-17 2:04 ` Jiang, Haochen
2023-07-17 7:08 ` Jan Beulich
0 siblings, 1 reply; 6+ messages in thread
From: Jiang, Haochen @ 2023-07-17 2:04 UTC (permalink / raw)
To: Beulich, Jan, Binutils; +Cc: H.J. Lu
> --- a/gas/testsuite/gas/i386/opcode-suffix.d
> +++ b/gas/testsuite/gas/i386/opcode-suffix.d
> @@ -102,7 +102,7 @@ Disassembly of section .text:
> *[0-9a-f]+: 60[ ]+pushal
> *[0-9a-f]+: 61[ ]+popal
> *[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\)
> - *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\)
> + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpll[ ]+%edx,-
> 0x6f6f6f70\(%eax\)
> *[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090
> *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[
> ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx
> *[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90
> @@ -248,7 +248,7 @@ Disassembly of section .text:
> *[0-9a-f]+: fc[ ]+cld
> *[0-9a-f]+: fd[ ]+std
> *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
> - *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
> + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
H.J. is on vacation till Wednesday but I suppose H.J. has this question in my patch
before and he might raise again if he is here.
Is this suffix needed since m16 is the only allowed memory here?
Thx,
Haochen
> *[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\)
> *[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx
> *[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] x86: adjust disassembly of insns operating on selector values
2023-07-17 2:04 ` Jiang, Haochen
@ 2023-07-17 7:08 ` Jan Beulich
2023-07-21 1:20 ` H.J. Lu
0 siblings, 1 reply; 6+ messages in thread
From: Jan Beulich @ 2023-07-17 7:08 UTC (permalink / raw)
To: Jiang, Haochen; +Cc: H.J. Lu, Binutils
On 17.07.2023 04:04, Jiang, Haochen wrote:
>> --- a/gas/testsuite/gas/i386/opcode-suffix.d
>> +++ b/gas/testsuite/gas/i386/opcode-suffix.d
>> @@ -102,7 +102,7 @@ Disassembly of section .text:
>> *[0-9a-f]+: 60[ ]+pushal
>> *[0-9a-f]+: 61[ ]+popal
>> *[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\)
>> - *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\)
>> + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpll[ ]+%edx,-
>> 0x6f6f6f70\(%eax\)
>> *[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090
>> *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[
>> ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx
>> *[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90
>> @@ -248,7 +248,7 @@ Disassembly of section .text:
>> *[0-9a-f]+: fc[ ]+cld
>> *[0-9a-f]+: fd[ ]+std
>> *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
>> - *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
>> + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
>
> H.J. is on vacation till Wednesday but I suppose H.J. has this question in my patch
> before and he might raise again if he is here.
>
> Is this suffix needed since m16 is the only allowed memory here?
All suffixes should be appended in suffix-always mode. The question
of whether one can be omitted arises only in the default mode, where
optional suffixes are left off (for clarity / ease of reading). Plus
please recall that the changes here are for consistency, and e.g. in
*[0-9a-f]+: 8c 90 90 90 90 90[ ]+movw[ ]+%ss,-0x6f6f6f70\(%eax\)
the suffix is also present, no matter that only m16 is possible.
In any event I'm not intending to commit this before the end of the
week, so H.J. will have a chance to voice his opinion.
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] x86: adjust disassembly of insns operating on selector values
2023-07-17 7:08 ` Jan Beulich
@ 2023-07-21 1:20 ` H.J. Lu
0 siblings, 0 replies; 6+ messages in thread
From: H.J. Lu @ 2023-07-21 1:20 UTC (permalink / raw)
To: Jan Beulich; +Cc: Jiang, Haochen, Binutils
On Mon, Jul 17, 2023 at 12:08 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 17.07.2023 04:04, Jiang, Haochen wrote:
> >> --- a/gas/testsuite/gas/i386/opcode-suffix.d
> >> +++ b/gas/testsuite/gas/i386/opcode-suffix.d
> >> @@ -102,7 +102,7 @@ Disassembly of section .text:
> >> *[0-9a-f]+: 60[ ]+pushal
> >> *[0-9a-f]+: 61[ ]+popal
> >> *[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\)
> >> - *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\)
> >> + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpll[ ]+%edx,-
> >> 0x6f6f6f70\(%eax\)
> >> *[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090
> >> *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[
> >> ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx
> >> *[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90
> >> @@ -248,7 +248,7 @@ Disassembly of section .text:
> >> *[0-9a-f]+: fc[ ]+cld
> >> *[0-9a-f]+: fd[ ]+std
> >> *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
> >> - *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
> >> + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
> >
> > H.J. is on vacation till Wednesday but I suppose H.J. has this question in my patch
> > before and he might raise again if he is here.
> >
> > Is this suffix needed since m16 is the only allowed memory here?
>
> All suffixes should be appended in suffix-always mode. The question
> of whether one can be omitted arises only in the default mode, where
> optional suffixes are left off (for clarity / ease of reading). Plus
> please recall that the changes here are for consistency, and e.g. in
>
> *[0-9a-f]+: 8c 90 90 90 90 90[ ]+movw[ ]+%ss,-0x6f6f6f70\(%eax\)
>
> the suffix is also present, no matter that only m16 is possible.
>
> In any event I'm not intending to commit this before the end of the
> week, so H.J. will have a chance to voice his opinion.
>
> Jan
Personally, I don't think this change is necessary. But I am not
against it.
--
H.J.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-07-21 1:21 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-14 10:01 [PATCH 0/2] x86: adjust disassembling of selector-access insns Jan Beulich
2023-07-14 10:02 ` [PATCH 1/2] x86: simplify disassembly of LAR/LSL Jan Beulich
2023-07-14 10:02 ` [PATCH 2/2] x86: adjust disassembly of insns operating on selector values Jan Beulich
2023-07-17 2:04 ` Jiang, Haochen
2023-07-17 7:08 ` Jan Beulich
2023-07-21 1:20 ` H.J. Lu
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