* [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion
@ 2024-04-10 15:29 Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Victor Do Nascimento @ 2024-04-10 15:29 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
The addition of the novel FP8 8-bit floating-point data-type, as
highlighted in "Arm A-Profile Architecture Developments 2023" [1],
(both in its E5M2 and E4M3 formats) and its associated data-processing
operations has led to the requirement that we be able to convert
between FP8 and existing data-types as well as scale resulting
floating-point values.
The following conversions are made possible as a result of the FP8
extension:
- FP8 to BFloat16
- FP8 to half-precision
- Half-precision to FP8
- single-precision to FP8
Scaling instructions allow FP8 values to be scaled by integer powers
of two.
Such conversion and scaling instructions are added not only in the
context of the advanced SIMD architectural extension, but are also
supported for the SVE2 and SME2 architectural extensions.
SME2 FP8 support:
-----------------
In the presence of SME2 support, the FP8 extension adds the following
SME2 multi-vector instructions:
- FP8 convert instructions.
- Floating-point scaling instructions.
SVE2 FP8 convert instructions:
------------------------------
- In the presence of the SVE2 extension, these convert instructions
require that the streaming SVE mode is not enabled.
- In the presence of the SME2 extension, these convert instructions
require that the streaming SVE mode be enabled.
N.B. Due to the collaborative nature of FP8 feature implementation,
this patch series does not add the FPMR register. Upstreaming of this
patch-series should be deferred until the register implementation has
been upstreamed.
Regtested on aarch64-linux-gnu, no new regressions.
[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
Victor Do Nascimento (4):
aarch64: fp8 convert and scale - add feature flags and related
structures
aarch64: fp8 convert and scale - Add advsimd insn variants
aarch64: fp8 convert and scale - add sve2 insn variants
aarch64: fp8 convert and scale - add sme2 insn variants
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/advsimd-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/advsimd-fp8-fail.l | 262 ++++++
gas/testsuite/gas/aarch64/advsimd-fp8-fail.s | 121 +++
gas/testsuite/gas/aarch64/advsimd-fp8.d | 120 +++
gas/testsuite/gas/aarch64/advsimd-fp8.s | 76 ++
gas/testsuite/gas/aarch64/sme2-24-invalid.l | 4 +-
gas/testsuite/gas/aarch64/sme2-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/sme2-fp8-fail.l | 273 ++++++
gas/testsuite/gas/aarch64/sme2-fp8-fail.s | 106 +++
.../gas/aarch64/sme2-fp8-streaming.d | 4 +
gas/testsuite/gas/aarch64/sme2-fp8.d | 128 +++
gas/testsuite/gas/aarch64/sme2-fp8.s | 112 +++
gas/testsuite/gas/aarch64/sve2-fp8-dump | 53 ++
gas/testsuite/gas/aarch64/sve2-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/sve2-fp8-fail.l | 161 ++++
gas/testsuite/gas/aarch64/sve2-fp8-fail.s | 42 +
gas/testsuite/gas/aarch64/sve2-fp8.d | 3 +
gas/testsuite/gas/aarch64/sve2-fp8.s | 48 +
include/opcode/aarch64.h | 2 +
opcodes/aarch64-dis-2.c | 817 ++++++++++++++----
opcodes/aarch64-tbl.h | 95 ++
23 files changed, 2251 insertions(+), 185 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.s
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.s
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-dump
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.s
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
@ 2024-04-10 15:29 ` Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Victor Do Nascimento @ 2024-04-10 15:29 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
From: Victor Do Nascimento <vicdon01@e133397.arm.com>
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-tbl.h | 18 ++++++++++++++++++
4 files changed, 23 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6ad4fae8b0e..20188b9aed2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10477,6 +10477,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
{"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
+ {"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 3756948bfb8..4da18077f1b 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -291,6 +291,8 @@ automatically cause those extensions to be disabled.
@tab Enable the XS memory attribute extension.
@item @code{cpa} @tab
@tab Enable the Checked Pointer Arithmetic extension.
+@item @code{fp8} @tab
+ @tab Enable the Floating Point 8 (FP8) extension.
@end multitable
@multitable @columnfractions .20 .80
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2fca9528c20..a50554a4dc7 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -232,6 +232,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_CPA,
/* FAMINMAX instructions. */
AARCH64_FEATURE_FAMINMAX,
+ /* FP8 instructions. */
+ AARCH64_FEATURE_FP8,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 356d303bc1a..7e603462a37 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2669,6 +2669,13 @@ static const aarch64_feature_set aarch64_feature_faminmax_sve2 =
AARCH64_FEATURES (2, FAMINMAX, SVE2);
static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
AARCH64_FEATURES (3, SVE2, FAMINMAX, SME2);
+static const aarch64_feature_set aarch64_feature_fp8 =
+ AARCH64_FEATURE (FP8);
+static const aarch64_feature_set aarch64_feature_fp8_sve2 =
+ AARCH64_FEATURES (2, FP8, SVE2);
+static const aarch64_feature_set aarch64_feature_fp8_sme2 =
+ AARCH64_FEATURES (2, FP8, SME2);
+
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2740,6 +2747,9 @@ static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
#define FAMINMAX &aarch64_feature_faminmax
#define FAMINMAX_SVE2 &aarch64_feature_faminmax_sve2
#define FAMINMAX_SME2 &aarch64_feature_faminmax_sme2
+#define FP8 &aarch64_feature_fp8
+#define FP8_SVE2 &aarch64_feature_fp8_sve2
+#define FP8_SME2 &aarch64_feature_fp8_sme2
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2925,6 +2935,14 @@ static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
#define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \
{ NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \
F_STRICT | 0, 0, 1, NULL }
+#define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, FP8_SVE2, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define FP8_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, FP8_SME2, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
@ 2024-04-10 15:29 ` Victor Do Nascimento
2024-05-17 15:43 ` Richard Earnshaw (lists)
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
` (2 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Victor Do Nascimento @ 2024-04-10 15:29 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Add the advanced SIMD variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
FP8 convert to BFloat16 (vector):
---------------------------------
- bf1cvtl V<d>.8H, V<n>.8B
- bf2cvtl V<d>.8H, V<n>.8B
- bf1cvtl2 V<d>.8H, V<n>.16B
- bf2cvtl2 V<d>.8H, V<n>.16B
FP8 convert to half-precision (vector):
---------------------------------------
- f1cvtl V<d>.8H, V<n>.8B
- f2cvtl V<d>.8H, V<n>.8B
- f1cvtl2 V<d>.8H, V<n>.16B
- f2cvtl2 V<d>.8H, V<n>.16B
Single-precision to FP8 convert and narrow (vector):
----------------------------------------------------
- fcvtn V<d>.8B, V<n>.4S, V<m>.4S
- fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S
Half-precision to FP8 convert and narrow (vector):
--------------------------------------------------
- fcvtn V<d>.8B, V<n>.4H, V<m>.4H
- fcvtn V<d>.16B, V<n>.8H, V<m>.8H
Floating-point adjust exponent by vector:
-----------------------------------------
- fscale V<d>.4H, V<n>.4H, V<m>.4H
- fscale V<d>.8H, V<n>.8H, V<m>.8H
- fscale V<d>.2S, V<n>.2S, V<m>.2S
- fscale V<d>.4S, V<n>.4S, V<m>.4S
- fscale V<d>.2d, V<n>.2d, V<m>.2d
---
gas/testsuite/gas/aarch64/advsimd-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/advsimd-fp8-fail.l | 262 +++++++++++++++++++
gas/testsuite/gas/aarch64/advsimd-fp8-fail.s | 121 +++++++++
gas/testsuite/gas/aarch64/advsimd-fp8.d | 120 +++++++++
gas/testsuite/gas/aarch64/advsimd-fp8.s | 76 ++++++
opcodes/aarch64-dis-2.c | 215 ++++++++++++---
opcodes/aarch64-tbl.h | 41 +++
7 files changed, 801 insertions(+), 36 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.s
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
new file mode 100644
index 00000000000..aaf00968c23
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8 -mno-verbose-error
+#error_output: advsimd-fp8-fail.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
new file mode 100644
index 00000000000..eea5a0b060f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
@@ -0,0 +1,262 @@
+[^:]+: Assembler messages:
+[^:]+:9: Error: operand mismatch -- `bf1cvtl v0.16b,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `bf1cvtl v0.8b,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvtl v0.4h,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtl v0.2s,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtl v0.4s,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `bf1cvtl v0.2d,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `bf1cvtl v0,v1.8b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `bf1cvtl v0.8h,v1.4h'
+[^:]+:27: Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `bf1cvtl v0.8h,v1.2s'
+[^:]+:27: Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `bf1cvtl v0.8h,v1.16b'
+[^:]+:27: Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `bf1cvtl v0.8h,v1.8h'
+[^:]+:27: Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `bf1cvtl v0.8h,v1.4s'
+[^:]+:27: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bf1cvtl v0.8h,v1.2d'
+[^:]+:27: Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `bf1cvtl v0.8h,v0'
+[^:]+:27: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtl v0.16b,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `bf2cvtl v0.8b,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvtl v0.4h,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtl v0.2s,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtl v0.4s,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `bf2cvtl v0.2d,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `bf2cvtl v0,v1.8b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `bf2cvtl v0.8h,v1.4h'
+[^:]+:28: Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `bf2cvtl v0.8h,v1.2s'
+[^:]+:28: Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `bf2cvtl v0.8h,v1.16b'
+[^:]+:28: Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `bf2cvtl v0.8h,v1.8h'
+[^:]+:28: Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `bf2cvtl v0.8h,v1.4s'
+[^:]+:28: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bf2cvtl v0.8h,v1.2d'
+[^:]+:28: Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `bf2cvtl v0.8h,v0'
+[^:]+:28: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtl v0.16b,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `f1cvtl v0.8b,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvtl v0.4h,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtl v0.2s,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtl v0.4s,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `f1cvtl v0.2d,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `f1cvtl v0,v1.8b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `f1cvtl v0.8h,v1.4h'
+[^:]+:29: Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `f1cvtl v0.8h,v1.2s'
+[^:]+:29: Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `f1cvtl v0.8h,v1.16b'
+[^:]+:29: Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `f1cvtl v0.8h,v1.8h'
+[^:]+:29: Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `f1cvtl v0.8h,v1.4s'
+[^:]+:29: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `f1cvtl v0.8h,v1.2d'
+[^:]+:29: Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `f1cvtl v0.8h,v0'
+[^:]+:29: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtl v0.16b,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `f2cvtl v0.8b,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvtl v0.4h,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtl v0.2s,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtl v0.4s,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `f2cvtl v0.2d,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `f2cvtl v0,v1.8b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `f2cvtl v0.8h,v1.4h'
+[^:]+:30: Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `f2cvtl v0.8h,v1.2s'
+[^:]+:30: Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `f2cvtl v0.8h,v1.16b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `f2cvtl v0.8h,v1.8h'
+[^:]+:30: Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `f2cvtl v0.8h,v1.4s'
+[^:]+:30: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `f2cvtl v0.8h,v1.2d'
+[^:]+:30: Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `f2cvtl v0.8h,v0'
+[^:]+:30: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bf1cvtl2 v0.16b,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bf1cvtl2 v0.8b,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `bf1cvtl2 v0.4h,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `bf1cvtl2 v0.2s,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `bf1cvtl2 v0.4s,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `bf1cvtl2 v0.2d,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `bf1cvtl2 v0,v1.16b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.8b'
+[^:]+:56: Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.4h'
+[^:]+:56: Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.2s'
+[^:]+:56: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.8h'
+[^:]+:56: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.4s'
+[^:]+:56: Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.2d'
+[^:]+:56: Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `bf1cvtl2 v0.8h,v1'
+[^:]+:56: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bf2cvtl2 v0.16b,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bf2cvtl2 v0.8b,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `bf2cvtl2 v0.4h,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `bf2cvtl2 v0.2s,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `bf2cvtl2 v0.4s,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `bf2cvtl2 v0.2d,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `bf2cvtl2 v0,v1.16b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.8b'
+[^:]+:57: Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.4h'
+[^:]+:57: Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.2s'
+[^:]+:57: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.8h'
+[^:]+:57: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.4s'
+[^:]+:57: Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.2d'
+[^:]+:57: Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `bf2cvtl2 v0.8h,v1'
+[^:]+:57: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `f1cvtl2 v0.16b,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `f1cvtl2 v0.8b,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `f1cvtl2 v0.4h,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `f1cvtl2 v0.2s,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `f1cvtl2 v0.4s,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `f1cvtl2 v0.2d,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `f1cvtl2 v0,v1.16b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.8b'
+[^:]+:58: Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.4h'
+[^:]+:58: Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.2s'
+[^:]+:58: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.8h'
+[^:]+:58: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.4s'
+[^:]+:58: Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.2d'
+[^:]+:58: Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `f1cvtl2 v0.8h,v1'
+[^:]+:58: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `f2cvtl2 v0.16b,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `f2cvtl2 v0.8b,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `f2cvtl2 v0.4h,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `f2cvtl2 v0.2s,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `f2cvtl2 v0.4s,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `f2cvtl2 v0.2d,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `f2cvtl2 v0,v1.16b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.8b'
+[^:]+:59: Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.4h'
+[^:]+:59: Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.2s'
+[^:]+:59: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.8h'
+[^:]+:59: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.4s'
+[^:]+:59: Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.2d'
+[^:]+:59: Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `f2cvtl2 v0.8h,v1'
+[^:]+:59: Info: macro invoked from here
+[^:]+:64: Error: operand mismatch -- `fscale v0.8b,v0.8b,v0.8b'
+[^:]+:65: Error: operand mismatch -- `fscale v0.16b,v0.16b,v0.16b'
+[^:]+:72: Error: operand mismatch -- `fcvtn v0.4h,v1.4h,v2.4h'
+[^:]+:73: Error: operand mismatch -- `fcvtn v0.2s,v1.4h,v2.4h'
+[^:]+:74: Error: operand mismatch -- `fcvtn v0.16b,v1.4h,v2.4h'
+[^:]+:75: Error: operand mismatch -- `fcvtn v0.8h,v1.4h,v2.4h'
+[^:]+:76: Error: operand mismatch -- `fcvtn v0.4s,v1.4h,v2.4h'
+[^:]+:77: Error: operand mismatch -- `fcvtn v0.2d,v1.4h,v2.4h'
+[^:]+:79: Error: operand mismatch -- `fcvtn v0.8b,v1.8h,v2.8h'
+[^:]+:80: Error: operand mismatch -- `fcvtn v0.4h,v1.8h,v2.8h'
+[^:]+:81: Error: operand mismatch -- `fcvtn v0.2s,v1.8h,v2.8h'
+[^:]+:83: Error: operand mismatch -- `fcvtn v0.8h,v1.8h,v2.8h'
+[^:]+:84: Error: operand mismatch -- `fcvtn v0.4s,v1.8h,v2.8h'
+[^:]+:85: Error: operand mismatch -- `fcvtn v0.2d,v1.8h,v2.8h'
+[^:]+:88: Error: operand mismatch -- `fcvtn v0.8b,v1.8b,v2.8b'
+[^:]+:90: Error: operand mismatch -- `fcvtn v0.8b,v1.2s,v2.2s'
+[^:]+:91: Error: operand mismatch -- `fcvtn v0.8b,v1.16b,v2.16b'
+[^:]+:92: Error: operand mismatch -- `fcvtn v0.8b,v1.8h,v2.8h'
+[^:]+:94: Error: operand mismatch -- `fcvtn v0.8b,v1.2d,v2.2d'
+[^:]+:96: Error: operand mismatch -- `fcvtn v0.16b,v1.8b,v2.8b'
+[^:]+:97: Error: operand mismatch -- `fcvtn v0.16b,v1.4h,v2.4h'
+[^:]+:98: Error: operand mismatch -- `fcvtn v0.16b,v1.2s,v2.2s'
+[^:]+:99: Error: operand mismatch -- `fcvtn v0.16b,v1.16b,v2.16b'
+[^:]+:101: Error: operand mismatch -- `fcvtn v0.16b,v1.4s,v2.4s'
+[^:]+:102: Error: operand mismatch -- `fcvtn v0.16b,v1.2d,v2.2d'
+[^:]+:107: Error: operand mismatch -- `fcvtn v0.4h,v1.4s,v2.4s'
+[^:]+:108: Error: operand mismatch -- `fcvtn v0.2s,v1.4s,v2.4s'
+[^:]+:109: Error: operand mismatch -- `fcvtn v0.16b,v1.4s,v2.4s'
+[^:]+:110: Error: operand mismatch -- `fcvtn v0.8h,v1.4s,v2.4s'
+[^:]+:111: Error: operand mismatch -- `fcvtn v0.4s,v1.4s,v2.4s'
+[^:]+:112: Error: operand mismatch -- `fcvtn v0.2d,v1.4s,v2.4s'
+[^:]+:115: Error: operand mismatch -- `fcvtn2 v0.16b,v1.8b,v2.8b'
+[^:]+:116: Error: operand mismatch -- `fcvtn2 v0.16b,v1.4h,v2.4h'
+[^:]+:117: Error: operand mismatch -- `fcvtn2 v0.16b,v1.2d,v2.2d'
+[^:]+:118: Error: operand mismatch -- `fcvtn2 v0.16b,v1.16b,v2.16b'
+[^:]+:119: Error: operand mismatch -- `fcvtn2 v0.16b,v1.8h,v2.8h'
+[^:]+:121: Error: operand mismatch -- `fcvtn2 v0.16b,v1.2d,v2.2d'
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
new file mode 100644
index 00000000000..71ebf3c5e32
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
@@ -0,0 +1,121 @@
+ /* advsimd-fp8-fail.s Test file for error-checking AArch64 8-bit
+ floating-point vector instructions. */
+
+ /* Instructions convert the elements from the lower half of the source
+ vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+
+ .macro cvrt_lowerhalf, op
+ /* Check the number and width of destination vector elements. */
+ \op v0.16b, v1.8b
+ \op v0.8b, v1.8b
+ \op v0.4h, v1.8b
+ \op v0.8h, v1.8b /* Valid. */
+ \op v0.2s, v1.8b
+ \op v0.4s, v1.8b
+ \op v0.2d, v1.8b
+ \op v0, v1.8b
+ /* Check the number and width of source vector elements. */
+ \op v0.8h, v1.4h
+ \op v0.8h, v1.2s
+ \op v0.8h, v1.16b
+ \op v0.8h, v1.8h
+ \op v0.8h, v1.4s
+ \op v0.8h, v1.2d
+ \op v0.8h, v0
+ .endm
+
+ cvrt_lowerhalf bf1cvtl
+ cvrt_lowerhalf bf2cvtl
+ cvrt_lowerhalf f1cvtl
+ cvrt_lowerhalf f2cvtl
+
+ /* Instructions convert the elements from the upper half of the source
+ vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+
+ .macro cvrt_upperhalf, op
+ /* Check the number and width of destination vector elements. */
+ \op v0.16b, v1.16b
+ \op v0.8b, v1.16b
+ \op v0.4h, v1.16b
+ \op v0.8h, v1.16b /* Valid. */
+ \op v0.2s, v1.16b
+ \op v0.4s, v1.16b
+ \op v0.2d, v1.16b
+ \op v0, v1.16b
+ /* Check the number and width of source vector elements. */
+ \op v0.8h, v1.8b
+ \op v0.8h, v1.4h
+ \op v0.8h, v1.2s
+ \op v0.8h, v1.16b /* Valid. */
+ \op v0.8h, v1.8h
+ \op v0.8h, v1.4s
+ \op v0.8h, v1.2d
+ \op v0.8h, v1
+ .endm
+
+ cvrt_upperhalf bf1cvtl2
+ cvrt_upperhalf bf2cvtl2
+ cvrt_upperhalf f1cvtl2
+ cvrt_upperhalf f2cvtl2
+
+ /* Floating-point adjust exponent by vector. */
+
+ /* Check invalid vector element number and width combinations. */
+ fscale v0.8b, v0.8b, v0.8b
+ fscale v0.16b, v0.16b, v0.16b
+
+ /* Half and single-precision to FP8 convert and narrow. */
+
+ /* Half-precision variant. */
+ /* Check the number and width of destination vector elements. */
+ fcvtn v0.8b, v1.4h, v2.4h /* Valid. */
+ fcvtn v0.4h, v1.4h, v2.4h
+ fcvtn v0.2s, v1.4h, v2.4h
+ fcvtn v0.16b, v1.4h, v2.4h
+ fcvtn v0.8h, v1.4h, v2.4h
+ fcvtn v0.4s, v1.4h, v2.4h
+ fcvtn v0.2d, v1.4h, v2.4h
+
+ fcvtn v0.8b, v1.8h, v2.8h
+ fcvtn v0.4h, v1.8h, v2.8h
+ fcvtn v0.2s, v1.8h, v2.8h
+ fcvtn v0.16b, v1.8h, v2.8h /* Valid. */
+ fcvtn v0.8h, v1.8h, v2.8h
+ fcvtn v0.4s, v1.8h, v2.8h
+ fcvtn v0.2d, v1.8h, v2.8h
+
+ /* Check the number and width of source vector elements. */
+ fcvtn v0.8b, v1.8b, v2.8b
+ fcvtn v0.8b, v1.4h, v2.4h /* Valid. */
+ fcvtn v0.8b, v1.2s, v2.2s
+ fcvtn v0.8b, v1.16b, v2.16b
+ fcvtn v0.8b, v1.8h, v2.8h
+ fcvtn v0.8b, v1.4s, v2.4s /* Valid. */
+ fcvtn v0.8b, v1.2d, v2.2d
+
+ fcvtn v0.16b, v1.8b, v2.8b
+ fcvtn v0.16b, v1.4h, v2.4h
+ fcvtn v0.16b, v1.2s, v2.2s
+ fcvtn v0.16b, v1.16b, v2.16b
+ fcvtn v0.16b, v1.8h, v2.8h /* Valid. */
+ fcvtn v0.16b, v1.4s, v2.4s
+ fcvtn v0.16b, v1.2d, v2.2d
+
+ /* Single-precision variant. */
+ /* Check the number and width of destination vector elements. */
+ fcvtn v0.8b, v1.4s, v2.4s /* Valid. */
+ fcvtn v0.4h, v1.4s, v2.4s
+ fcvtn v0.2s, v1.4s, v2.4s
+ fcvtn v0.16b, v1.4s, v2.4s
+ fcvtn v0.8h, v1.4s, v2.4s
+ fcvtn v0.4s, v1.4s, v2.4s
+ fcvtn v0.2d, v1.4s, v2.4s
+
+ /* Check the number and width of source vector elements. */
+ fcvtn2 v0.16b, v1.8b, v2.8b
+ fcvtn2 v0.16b, v1.4h, v2.4h
+ fcvtn2 v0.16b, v1.2d, v2.2d
+ fcvtn2 v0.16b, v1.16b, v2.16b
+ fcvtn2 v0.16b, v1.8h, v2.8h
+ fcvtn2 v0.16b, v1.4s, v2.4s /* Valid. */
+ fcvtn2 v0.16b, v1.2d, v2.2d
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8.d b/gas/testsuite/gas/aarch64/advsimd-fp8.d
new file mode 100644
index 00000000000..b4592a7cf91
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8.d
@@ -0,0 +1,120 @@
+#as: -march=armv8.5-a+fp8
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+: 2ea17800 bf1cvtl v0.8h, v0.8b
+[ ]*[0-9a-f]+: 2ea17801 bf1cvtl v1.8h, v0.8b
+[ ]*[0-9a-f]+: 2ea17820 bf1cvtl v0.8h, v1.8b
+[ ]*[0-9a-f]+: 2ea17821 bf1cvtl v1.8h, v1.8b
+[ ]*[0-9a-f]+: 2ea17a30 bf1cvtl v16.8h, v17.8b
+[ ]*[0-9a-f]+: 2ee17800 bf2cvtl v0.8h, v0.8b
+[ ]*[0-9a-f]+: 2ee17801 bf2cvtl v1.8h, v0.8b
+[ ]*[0-9a-f]+: 2ee17820 bf2cvtl v0.8h, v1.8b
+[ ]*[0-9a-f]+: 2ee17821 bf2cvtl v1.8h, v1.8b
+[ ]*[0-9a-f]+: 2ee17a30 bf2cvtl v16.8h, v17.8b
+[ ]*[0-9a-f]+: 2e217800 f1cvtl v0.8h, v0.8b
+[ ]*[0-9a-f]+: 2e217801 f1cvtl v1.8h, v0.8b
+[ ]*[0-9a-f]+: 2e217820 f1cvtl v0.8h, v1.8b
+[ ]*[0-9a-f]+: 2e217821 f1cvtl v1.8h, v1.8b
+[ ]*[0-9a-f]+: 2e217a30 f1cvtl v16.8h, v17.8b
+[ ]*[0-9a-f]+: 2e617800 f2cvtl v0.8h, v0.8b
+[ ]*[0-9a-f]+: 2e617801 f2cvtl v1.8h, v0.8b
+[ ]*[0-9a-f]+: 2e617820 f2cvtl v0.8h, v1.8b
+[ ]*[0-9a-f]+: 2e617821 f2cvtl v1.8h, v1.8b
+[ ]*[0-9a-f]+: 2e617a30 f2cvtl v16.8h, v17.8b
+[ ]*[0-9a-f]+: 6ea17800 bf1cvtl2 v0.8h, v0.16b
+[ ]*[0-9a-f]+: 6ea17801 bf1cvtl2 v1.8h, v0.16b
+[ ]*[0-9a-f]+: 6ea17820 bf1cvtl2 v0.8h, v1.16b
+[ ]*[0-9a-f]+: 6ea17821 bf1cvtl2 v1.8h, v1.16b
+[ ]*[0-9a-f]+: 6ea17a30 bf1cvtl2 v16.8h, v17.16b
+[ ]*[0-9a-f]+: 6ee17800 bf2cvtl2 v0.8h, v0.16b
+[ ]*[0-9a-f]+: 6ee17801 bf2cvtl2 v1.8h, v0.16b
+[ ]*[0-9a-f]+: 6ee17820 bf2cvtl2 v0.8h, v1.16b
+[ ]*[0-9a-f]+: 6ee17821 bf2cvtl2 v1.8h, v1.16b
+[ ]*[0-9a-f]+: 6ee17a30 bf2cvtl2 v16.8h, v17.16b
+[ ]*[0-9a-f]+: 6e217800 f1cvtl2 v0.8h, v0.16b
+[ ]*[0-9a-f]+: 6e217801 f1cvtl2 v1.8h, v0.16b
+[ ]*[0-9a-f]+: 6e217820 f1cvtl2 v0.8h, v1.16b
+[ ]*[0-9a-f]+: 6e217821 f1cvtl2 v1.8h, v1.16b
+[ ]*[0-9a-f]+: 6e217a30 f1cvtl2 v16.8h, v17.16b
+[ ]*[0-9a-f]+: 6e617800 f2cvtl2 v0.8h, v0.16b
+[ ]*[0-9a-f]+: 6e617801 f2cvtl2 v1.8h, v0.16b
+[ ]*[0-9a-f]+: 6e617820 f2cvtl2 v0.8h, v1.16b
+[ ]*[0-9a-f]+: 6e617821 f2cvtl2 v1.8h, v1.16b
+[ ]*[0-9a-f]+: 6e617a30 f2cvtl2 v16.8h, v17.16b
+[ ]*[0-9a-f]+: 2ec03c00 fscale v0.4h, v0.4h, v0.4h
+[ ]*[0-9a-f]+: 2ec03c01 fscale v1.4h, v0.4h, v0.4h
+[ ]*[0-9a-f]+: 2ec03c20 fscale v0.4h, v1.4h, v0.4h
+[ ]*[0-9a-f]+: 2ec13c00 fscale v0.4h, v0.4h, v1.4h
+[ ]*[0-9a-f]+: 2ec03c21 fscale v1.4h, v1.4h, v0.4h
+[ ]*[0-9a-f]+: 2ec13c20 fscale v0.4h, v1.4h, v1.4h
+[ ]*[0-9a-f]+: 2ec13c21 fscale v1.4h, v1.4h, v1.4h
+[ ]*[0-9a-f]+: 2ed23e30 fscale v16.4h, v17.4h, v18.4h
+[ ]*[0-9a-f]+: 6ec03c00 fscale v0.8h, v0.8h, v0.8h
+[ ]*[0-9a-f]+: 6ec03c01 fscale v1.8h, v0.8h, v0.8h
+[ ]*[0-9a-f]+: 6ec03c20 fscale v0.8h, v1.8h, v0.8h
+[ ]*[0-9a-f]+: 6ec13c00 fscale v0.8h, v0.8h, v1.8h
+[ ]*[0-9a-f]+: 6ec03c21 fscale v1.8h, v1.8h, v0.8h
+[ ]*[0-9a-f]+: 6ec13c20 fscale v0.8h, v1.8h, v1.8h
+[ ]*[0-9a-f]+: 6ec13c21 fscale v1.8h, v1.8h, v1.8h
+[ ]*[0-9a-f]+: 6ed23e30 fscale v16.8h, v17.8h, v18.8h
+[ ]*[0-9a-f]+: 2ea0fc00 fscale v0.2s, v0.2s, v0.2s
+[ ]*[0-9a-f]+: 2ea0fc01 fscale v1.2s, v0.2s, v0.2s
+[ ]*[0-9a-f]+: 2ea0fc20 fscale v0.2s, v1.2s, v0.2s
+[ ]*[0-9a-f]+: 2ea1fc00 fscale v0.2s, v0.2s, v1.2s
+[ ]*[0-9a-f]+: 2ea0fc21 fscale v1.2s, v1.2s, v0.2s
+[ ]*[0-9a-f]+: 2ea1fc20 fscale v0.2s, v1.2s, v1.2s
+[ ]*[0-9a-f]+: 2ea1fc21 fscale v1.2s, v1.2s, v1.2s
+[ ]*[0-9a-f]+: 2eb2fe30 fscale v16.2s, v17.2s, v18.2s
+[ ]*[0-9a-f]+: 6ea0fc00 fscale v0.4s, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 6ea0fc01 fscale v1.4s, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 6ea0fc20 fscale v0.4s, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 6ea1fc00 fscale v0.4s, v0.4s, v1.4s
+[ ]*[0-9a-f]+: 6ea0fc21 fscale v1.4s, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 6ea1fc20 fscale v0.4s, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 6ea1fc21 fscale v1.4s, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 6eb2fe30 fscale v16.4s, v17.4s, v18.4s
+[ ]*[0-9a-f]+: 6ee0fc00 fscale v0.2d, v0.2d, v0.2d
+[ ]*[0-9a-f]+: 6ee0fc01 fscale v1.2d, v0.2d, v0.2d
+[ ]*[0-9a-f]+: 6ee0fc20 fscale v0.2d, v1.2d, v0.2d
+[ ]*[0-9a-f]+: 6ee1fc00 fscale v0.2d, v0.2d, v1.2d
+[ ]*[0-9a-f]+: 6ee0fc21 fscale v1.2d, v1.2d, v0.2d
+[ ]*[0-9a-f]+: 6ee1fc20 fscale v0.2d, v1.2d, v1.2d
+[ ]*[0-9a-f]+: 6ee1fc21 fscale v1.2d, v1.2d, v1.2d
+[ ]*[0-9a-f]+: 6ef2fe30 fscale v16.2d, v17.2d, v18.2d
+[ ]*[0-9a-f]+: 0e40f400 fcvtn v0.8b, v0.4h, v0.4h
+[ ]*[0-9a-f]+: 0e40f401 fcvtn v1.8b, v0.4h, v0.4h
+[ ]*[0-9a-f]+: 0e40f420 fcvtn v0.8b, v1.4h, v0.4h
+[ ]*[0-9a-f]+: 0e41f400 fcvtn v0.8b, v0.4h, v1.4h
+[ ]*[0-9a-f]+: 0e40f421 fcvtn v1.8b, v1.4h, v0.4h
+[ ]*[0-9a-f]+: 0e41f420 fcvtn v0.8b, v1.4h, v1.4h
+[ ]*[0-9a-f]+: 0e41f421 fcvtn v1.8b, v1.4h, v1.4h
+[ ]*[0-9a-f]+: 0e52f630 fcvtn v16.8b, v17.4h, v18.4h
+[ ]*[0-9a-f]+: 4e40f400 fcvtn v0.16b, v0.8h, v0.8h
+[ ]*[0-9a-f]+: 4e40f401 fcvtn v1.16b, v0.8h, v0.8h
+[ ]*[0-9a-f]+: 4e40f420 fcvtn v0.16b, v1.8h, v0.8h
+[ ]*[0-9a-f]+: 4e41f400 fcvtn v0.16b, v0.8h, v1.8h
+[ ]*[0-9a-f]+: 4e40f421 fcvtn v1.16b, v1.8h, v0.8h
+[ ]*[0-9a-f]+: 4e41f420 fcvtn v0.16b, v1.8h, v1.8h
+[ ]*[0-9a-f]+: 4e41f421 fcvtn v1.16b, v1.8h, v1.8h
+[ ]*[0-9a-f]+: 4e52f630 fcvtn v16.16b, v17.8h, v18.8h
+[ ]*[0-9a-f]+: 0e00f400 fcvtn v0.8b, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 0e00f401 fcvtn v1.8b, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 0e00f420 fcvtn v0.8b, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 0e01f400 fcvtn v0.8b, v0.4s, v1.4s
+[ ]*[0-9a-f]+: 0e00f421 fcvtn v1.8b, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 0e01f420 fcvtn v0.8b, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 0e01f421 fcvtn v1.8b, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 0e12f630 fcvtn v16.8b, v17.4s, v18.4s
+[ ]*[0-9a-f]+: 4e00f400 fcvtn2 v0.16b, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 4e00f401 fcvtn2 v1.16b, v0.4s, v0.4s
+[ ]*[0-9a-f]+: 4e00f420 fcvtn2 v0.16b, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 4e01f400 fcvtn2 v0.16b, v0.4s, v1.4s
+[ ]*[0-9a-f]+: 4e00f421 fcvtn2 v1.16b, v1.4s, v0.4s
+[ ]*[0-9a-f]+: 4e01f420 fcvtn2 v0.16b, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 4e01f421 fcvtn2 v1.16b, v1.4s, v1.4s
+[ ]*[0-9a-f]+: 4e12f630 fcvtn2 v16.16b, v17.4s, v18.4s
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8.s b/gas/testsuite/gas/aarch64/advsimd-fp8.s
new file mode 100644
index 00000000000..e49f38d420a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8.s
@@ -0,0 +1,76 @@
+ /* advsimd-fp8.s Test file for AArch64 8-bit floating-point vector
+ instructions. */
+
+ /* Instructions convert the elements from the lower half of the source
+ vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+
+ .macro cvrt_lowerhalf, op
+ \op v0.8h, v0.8b
+ \op v1.8h, v0.8b
+ \op v0.8h, v1.8b
+ \op v1.8h, v1.8b
+ \op v16.8h, v17.8b
+ .endm
+
+ cvrt_lowerhalf bf1cvtl
+ cvrt_lowerhalf bf2cvtl
+ cvrt_lowerhalf f1cvtl
+ cvrt_lowerhalf f2cvtl
+
+ /* Instructions convert the elements from the upper half of the source
+ vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+
+ .macro cvrt_upperhalf, op
+ \op v0.8h, v0.16b
+ \op v1.8h, v0.16b
+ \op v0.8h, v1.16b
+ \op v1.8h, v1.16b
+ \op v16.8h, v17.16b
+ .endm
+
+ cvrt_upperhalf bf1cvtl2
+ cvrt_upperhalf bf2cvtl2
+ cvrt_upperhalf f1cvtl2
+ cvrt_upperhalf f2cvtl2
+
+ /* Floating-point adjust exponent by vector. */
+
+ .macro fscale_gen, op_var
+ fscale v0.\op_var, v0.\op_var, v0.\op_var
+ fscale v1.\op_var, v0.\op_var, v0.\op_var
+ fscale v0.\op_var, v1.\op_var, v0.\op_var
+ fscale v0.\op_var, v0.\op_var, v1.\op_var
+ fscale v1.\op_var, v1.\op_var, v0.\op_var
+ fscale v0.\op_var, v1.\op_var, v1.\op_var
+ fscale v1.\op_var, v1.\op_var, v1.\op_var
+ fscale v16.\op_var, v17.\op_var, v18.\op_var
+ .endm
+
+ /* Half-precision variant. */
+ fscale_gen 4h
+ fscale_gen 8h
+ /* Single-precision variant. */
+ fscale_gen 2s
+ fscale_gen 4s
+ fscale_gen 2d
+
+ /* Half and single-precision to FP8 convert and narrow. */
+
+ .macro fcvtn_to_fp8, op, sd, ss
+ \op v0.\sd, v0.\ss, v0.\ss
+ \op v1.\sd, v0.\ss, v0.\ss
+ \op v0.\sd, v1.\ss, v0.\ss
+ \op v0.\sd, v0.\ss, v1.\ss
+ \op v1.\sd, v1.\ss, v0.\ss
+ \op v0.\sd, v1.\ss, v1.\ss
+ \op v1.\sd, v1.\ss, v1.\ss
+ \op v16.\sd, v17.\ss, v18.\ss
+ .endm
+
+ /* Half-precision variant. */
+ fcvtn_to_fp8 fcvtn 8b, 4h
+ fcvtn_to_fp8 fcvtn 16b, 8h
+
+ /* Single-precision variant. */
+ fcvtn_to_fp8 fcvtn, 8b, 4s
+ fcvtn_to_fp8 fcvtn2, 16b, 4s
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 46aa21bf98f..2268bf6983a 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10334,7 +10334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3333;
+ return 3346;
}
else
{
@@ -10342,7 +10342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3334;
+ return 3347;
}
}
}
@@ -11260,7 +11260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3335;
+ return 3348;
}
else
{
@@ -11268,7 +11268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3336;
+ return 3349;
}
}
}
@@ -11353,7 +11353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3337;
+ return 3350;
}
else
{
@@ -11460,7 +11460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3339;
+ return 3352;
}
else
{
@@ -11665,7 +11665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3338;
+ return 3351;
}
else
{
@@ -11706,7 +11706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3340;
+ return 3353;
}
else
{
@@ -13364,7 +13364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3342;
+ return 3355;
}
}
else
@@ -13394,7 +13394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3341;
+ return 3354;
}
}
}
@@ -25607,21 +25607,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x0011100x0xxxxxxx1101xxxxxxxxxx
- fmax. */
- return 302;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x0011100x0xxxxxx01101xxxxxxxxxx
+ fmax. */
+ return 302;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x0011101x0xxxxxx01101xxxxxxxxxx
+ fmin. */
+ return 314;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x0011101x0xxxxxxx1101xxxxxxxxxx
- fmin. */
- return 314;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110x00xxxxxx11101xxxxxxxxxx
+ fcvtn. */
+ return 3341;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110x00xxxxxx11101xxxxxxxxxx
+ fcvtn2. */
+ return 3342;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x10xxxxxx11101xxxxxxxxxx
+ fcvtn. */
+ return 3343;
+ }
}
}
}
@@ -26007,11 +26040,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx101110x10xxxxx0x1111xxxxxxxxxx
- fdiv. */
- return 355;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx101110010xxxxx0x1111xxxxxxxxxx
+ fdiv. */
+ return 355;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx101110110xxxxx0x1111xxxxxxxxxx
+ fscale. */
+ return 3344;
+ }
}
}
}
@@ -27382,11 +27426,99 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx101110xx1xxxxx011110xxxxxxxxxx
- sqneg. */
- return 218;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx101110xx1xxxx0011110xxxxxxxxxx
+ sqneg. */
+ return 218;
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0101110001xxxx1011110xxxxxxxxxx
+ f1cvtl. */
+ return 3337;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101110001xxxx1011110xxxxxxxxxx
+ f1cvtl2. */
+ return 3338;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0101110101xxxx1011110xxxxxxxxxx
+ bf1cvtl. */
+ return 3333;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101110101xxxx1011110xxxxxxxxxx
+ bf1cvtl2. */
+ return 3334;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0101110011xxxx1011110xxxxxxxxxx
+ f2cvtl. */
+ return 3339;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101110011xxxx1011110xxxxxxxxxx
+ f2cvtl2. */
+ return 3340;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0101110111xxxx1011110xxxxxxxxxx
+ bf2cvtl. */
+ return 3335;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101110111xxxx1011110xxxxxxxxxx
+ bf2cvtl2. */
+ return 3336;
+ }
+ }
+ }
+ }
}
}
}
@@ -29367,11 +29499,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx011101x1xxxxx111111xxxxxxxxxx
- frsqrts. */
- return 315;
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0011101x1xxxxx111111xxxxxxxxxx
+ frsqrts. */
+ return 315;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx1011101x1xxxxx111111xxxxxxxxxx
+ fscale. */
+ return 3345;
+ }
}
}
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7e603462a37..f876c1b342f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2368,6 +2368,34 @@
QLF3(X,X,NIL), \
}
+#define QL_V3_BSS_LOWER \
+{ \
+ QLF3(V_8B, V_4S, V_4S), \
+}
+
+#define QL_V3_BSS_FULL \
+{ \
+ QLF3(V_16B, V_4S, V_4S), \
+}
+
+#define QL_V3_BHH \
+{ \
+ QLF3(V_8B, V_4H, V_4H), \
+ QLF3(V_16B, V_8H, V_8H), \
+}
+
+/* e.g. BF1CVTL <Vd>.8H, <Vn>.8B. */
+#define QL_V2FP8B8H \
+{ \
+ QLF2(V_8H, V_8B), \
+}
+
+/* e.g. BF1CVTL2 <Vd>.8H, <Vn>.16B. */
+#define QL_V28H16B \
+{ \
+ QLF2(V_8H, V_16B), \
+}
+
/* e.g. UDOT <Vd>.2S, <Vn>.8B, <Vm>.8B. */
#define QL_V3DOT \
{ \
@@ -6459,6 +6487,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
+ FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
+ FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0),
+ FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
+ FP8_INSN("bf2cvtl2", 0x6ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0),
+ FP8_INSN("f1cvtl", 0x2e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
+ FP8_INSN("f1cvtl2", 0x6e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0),
+ FP8_INSN("f2cvtl", 0x2e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2FP8B8H, 0),
+ FP8_INSN("f2cvtl2", 0x6e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V28H16B, 0),
+ FP8_INSN("fcvtn", 0xe00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3_BSS_LOWER, 0),
+ FP8_INSN("fcvtn2", 0x4e00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3_BSS_FULL, 0),
+ FP8_INSN("fcvtn", 0xe40f400, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3_BHH, F_SIZEQ),
+ FP8_INSN("fscale", 0x2ec03c00, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_VSHIFT_H, F_SIZEQ),
+ FP8_INSN("fscale", 0x2ea0fc00, 0xbfa0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
/* Checked Pointer Arithmetic Instructions. */
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 insn variants
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
@ 2024-04-10 15:29 ` Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 " Victor Do Nascimento
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
4 siblings, 0 replies; 7+ messages in thread
From: Victor Do Nascimento @ 2024-04-10 15:29 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
From: Victor Do Nascimento <vicdon01@e133397.arm.com>
Add the SVE2 variant of the FP8 convert and scale instructions,
enabled at assembly-time using the `+sve2+fp8' architectural
extension flag. More specifically, support is added for the
following instructions:
FP8 convert to BFloat16 (bottom/top):
-------------------------------------
- bf1cvt Z<d>.H, Z<n>.B
- bf2cvt Z<d>.H, Z<n>.B
- bf1cvtlt Z<d>.H, Z<n>.B
- bf2cvtlt Z<d>.H, Z<n>.B
FP8 convert to half-precision (bottom/top):
-------------------------------------------
- f1cvt Z<d>.H, Z<n>.B
- f2cvt Z<d>.H, Z<n>.B
- f1cvtlt Z<d>.H, Z<n>.B
- f2cvtlt Z<d>.H, Z<n>.B
BFloat16/half-precision convert, narrow and
interleave to FP8:
-------------------------------------------
- bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
- fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
Single-precision convert, narrow and interleave
to FP8 (bottom/top):
-----------------------------------------------
- fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S }
- fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }
---
.../gas/aarch64/sme2-fp8-streaming.d | 4 +
gas/testsuite/gas/aarch64/sve2-fp8-dump | 53 +++++
gas/testsuite/gas/aarch64/sve2-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/sve2-fp8-fail.l | 161 +++++++++++++++
gas/testsuite/gas/aarch64/sve2-fp8-fail.s | 42 ++++
gas/testsuite/gas/aarch64/sve2-fp8.d | 3 +
gas/testsuite/gas/aarch64/sve2-fp8.s | 48 +++++
opcodes/aarch64-dis-2.c | 194 +++++++++++++++---
opcodes/aarch64-tbl.h | 20 ++
9 files changed, 496 insertions(+), 31 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-dump
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.s
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d b/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
new file mode 100644
index 00000000000..16ed6b88bcd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
@@ -0,0 +1,4 @@
+#as: -march=armv8.5-a+fp8+sme2
+#objdump: -dr
+#source: sve2-fp8.s
+#dump: sve2-fp8-dump
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-dump b/gas/testsuite/gas/aarch64/sve2-fp8-dump
new file mode 100644
index 00000000000..570ff9c4da4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-dump
@@ -0,0 +1,53 @@
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+: 65083800 bf1cvt z0.h, z0.b
+[ ]*[0-9a-f]+: 65083801 bf1cvt z1.h, z0.b
+[ ]*[0-9a-f]+: 65083820 bf1cvt z0.h, z1.b
+[ ]*[0-9a-f]+: 65083bfe bf1cvt z30.h, z31.b
+[ ]*[0-9a-f]+: 65083c00 bf2cvt z0.h, z0.b
+[ ]*[0-9a-f]+: 65083c01 bf2cvt z1.h, z0.b
+[ ]*[0-9a-f]+: 65083c20 bf2cvt z0.h, z1.b
+[ ]*[0-9a-f]+: 65083ffe bf2cvt z30.h, z31.b
+[ ]*[0-9a-f]+: 65093800 bf1cvtlt z0.h, z0.b
+[ ]*[0-9a-f]+: 65093801 bf1cvtlt z1.h, z0.b
+[ ]*[0-9a-f]+: 65093820 bf1cvtlt z0.h, z1.b
+[ ]*[0-9a-f]+: 65093bfe bf1cvtlt z30.h, z31.b
+[ ]*[0-9a-f]+: 65093c00 bf2cvtlt z0.h, z0.b
+[ ]*[0-9a-f]+: 65093c01 bf2cvtlt z1.h, z0.b
+[ ]*[0-9a-f]+: 65093c20 bf2cvtlt z0.h, z1.b
+[ ]*[0-9a-f]+: 65093ffe bf2cvtlt z30.h, z31.b
+[ ]*[0-9a-f]+: 65083000 f1cvt z0.h, z0.b
+[ ]*[0-9a-f]+: 65083001 f1cvt z1.h, z0.b
+[ ]*[0-9a-f]+: 65083020 f1cvt z0.h, z1.b
+[ ]*[0-9a-f]+: 650833fe f1cvt z30.h, z31.b
+[ ]*[0-9a-f]+: 65083400 f2cvt z0.h, z0.b
+[ ]*[0-9a-f]+: 65083401 f2cvt z1.h, z0.b
+[ ]*[0-9a-f]+: 65083420 f2cvt z0.h, z1.b
+[ ]*[0-9a-f]+: 650837fe f2cvt z30.h, z31.b
+[ ]*[0-9a-f]+: 65093000 f1cvtlt z0.h, z0.b
+[ ]*[0-9a-f]+: 65093001 f1cvtlt z1.h, z0.b
+[ ]*[0-9a-f]+: 65093020 f1cvtlt z0.h, z1.b
+[ ]*[0-9a-f]+: 650933fe f1cvtlt z30.h, z31.b
+[ ]*[0-9a-f]+: 65093400 f2cvtlt z0.h, z0.b
+[ ]*[0-9a-f]+: 65093401 f2cvtlt z1.h, z0.b
+[ ]*[0-9a-f]+: 65093420 f2cvtlt z0.h, z1.b
+[ ]*[0-9a-f]+: 650937fe f2cvtlt z30.h, z31.b
+[ ]*[0-9a-f]+: 650a3800 bfcvtn z0.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: 650a3801 bfcvtn z1.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: 650a3840 bfcvtn z0.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: 650a3bdd bfcvtn z29.b, {z30.h-z31.h}
+[ ]*[0-9a-f]+: 650a3000 fcvtn z0.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: 650a3001 fcvtn z1.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: 650a3040 fcvtn z0.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: 650a33dd fcvtn z29.b, {z30.h-z31.h}
+[ ]*[0-9a-f]+: 650a3400 fcvtnb z0.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+: 650a3401 fcvtnb z1.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+: 650a3440 fcvtnb z0.b, {z2.s-z3.s}
+[ ]*[0-9a-f]+: 650a37dd fcvtnb z29.b, {z30.s-z31.s}
+[ ]*[0-9a-f]+: 650a3c00 fcvtnt z0.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+: 650a3c01 fcvtnt z1.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+: 650a3c40 fcvtnt z0.b, {z2.s-z3.s}
+[ ]*[0-9a-f]+: 650a3fdd fcvtnt z29.b, {z30.s-z31.s}
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.d b/gas/testsuite/gas/aarch64/sve2-fp8-fail.d
new file mode 100644
index 00000000000..f20d457b5ae
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8+sve2 -mno-verbose-error
+#error_output: sve2-fp8-fail.l
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.l b/gas/testsuite/gas/aarch64/sve2-fp8-fail.l
new file mode 100644
index 00000000000..ab48ff464d7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.l
@@ -0,0 +1,161 @@
+[^:]+: Assembler messages:
+[^:]+:6: Error: operand mismatch -- `bf1cvt z0.b,z1.b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvt z0.s,z1.b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvt z0.d,z1.b'
+[^:]+:30: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf1cvt z0.h,z1.h'
+[^:]+:30: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvt z0.h,z1.s'
+[^:]+:30: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvt z0.h,z1.d'
+[^:]+:30: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf1cvt z0.h,p0,z1.d'
+[^:]+:30: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf1cvt z0.h,p0/z,z1.d'
+[^:]+:30: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf2cvt z0.b,z1.b'
+[^:]+:31: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvt z0.s,z1.b'
+[^:]+:31: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvt z0.d,z1.b'
+[^:]+:31: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf2cvt z0.h,z1.h'
+[^:]+:31: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvt z0.h,z1.s'
+[^:]+:31: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvt z0.h,z1.d'
+[^:]+:31: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf2cvt z0.h,p0,z1.d'
+[^:]+:31: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf2cvt z0.h,p0/z,z1.d'
+[^:]+:31: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf1cvtlt z0.b,z1.b'
+[^:]+:32: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvtlt z0.s,z1.b'
+[^:]+:32: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvtlt z0.d,z1.b'
+[^:]+:32: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf1cvtlt z0.h,z1.h'
+[^:]+:32: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtlt z0.h,z1.s'
+[^:]+:32: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtlt z0.h,z1.d'
+[^:]+:32: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf1cvtlt z0.h,p0,z1.d'
+[^:]+:32: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf1cvtlt z0.h,p0/z,z1.d'
+[^:]+:32: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf2cvtlt z0.b,z1.b'
+[^:]+:33: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvtlt z0.s,z1.b'
+[^:]+:33: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtlt z0.d,z1.b'
+[^:]+:33: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf2cvtlt z0.h,z1.h'
+[^:]+:33: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtlt z0.h,z1.s'
+[^:]+:33: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtlt z0.h,z1.d'
+[^:]+:33: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf2cvtlt z0.h,p0,z1.d'
+[^:]+:33: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf2cvtlt z0.h,p0/z,z1.d'
+[^:]+:33: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f1cvt z0.b,z1.b'
+[^:]+:34: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvt z0.s,z1.b'
+[^:]+:34: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvt z0.d,z1.b'
+[^:]+:34: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f1cvt z0.h,z1.h'
+[^:]+:34: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvt z0.h,z1.s'
+[^:]+:34: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvt z0.h,z1.d'
+[^:]+:34: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f1cvt z0.h,p0,z1.d'
+[^:]+:34: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f1cvt z0.h,p0/z,z1.d'
+[^:]+:34: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f2cvt z0.b,z1.b'
+[^:]+:35: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvt z0.s,z1.b'
+[^:]+:35: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvt z0.d,z1.b'
+[^:]+:35: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f2cvt z0.h,z1.h'
+[^:]+:35: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvt z0.h,z1.s'
+[^:]+:35: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvt z0.h,z1.d'
+[^:]+:35: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f2cvt z0.h,p0,z1.d'
+[^:]+:35: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f2cvt z0.h,p0/z,z1.d'
+[^:]+:35: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f1cvtlt z0.b,z1.b'
+[^:]+:36: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvtlt z0.s,z1.b'
+[^:]+:36: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtlt z0.d,z1.b'
+[^:]+:36: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f1cvtlt z0.h,z1.h'
+[^:]+:36: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtlt z0.h,z1.s'
+[^:]+:36: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtlt z0.h,z1.d'
+[^:]+:36: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f1cvtlt z0.h,p0,z1.d'
+[^:]+:36: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f1cvtlt z0.h,p0/z,z1.d'
+[^:]+:36: Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f2cvtlt z0.b,z1.b'
+[^:]+:37: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvtlt z0.s,z1.b'
+[^:]+:37: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtlt z0.d,z1.b'
+[^:]+:37: Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f2cvtlt z0.h,z1.h'
+[^:]+:37: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtlt z0.h,z1.s'
+[^:]+:37: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtlt z0.h,z1.d'
+[^:]+:37: Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f2cvtlt z0.h,p0,z1.d'
+[^:]+:37: Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f2cvtlt z0.h,p0/z,z1.d'
+[^:]+:37: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bfcvtn z1.h,{z0.h-z1.h}'
+[^:]+:39: Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `bfcvtn z0.s,{z0.h-z1.h}'
+[^:]+:39: Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `bfcvtn z7.d,{z0.h-z1.h}'
+[^:]+:39: Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `bfcvtn z0.b,{z1.h-z2.h}'
+[^:]+:39: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtn z1.h,{z0.h-z1.h}'
+[^:]+:40: Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtn z0.s,{z0.h-z1.h}'
+[^:]+:40: Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtn z7.d,{z0.h-z1.h}'
+[^:]+:40: Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtn z0.b,{z1.h-z2.h}'
+[^:]+:40: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtnb z1.h,{z0.s-z1.s}'
+[^:]+:41: Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtnb z0.s,{z0.s-z1.s}'
+[^:]+:41: Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtnb z7.d,{z0.s-z1.s}'
+[^:]+:41: Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtnb z0.b,{z1.s-z2.s}'
+[^:]+:41: Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtnt z1.h,{z0.s-z1.s}'
+[^:]+:42: Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtnt z0.s,{z0.s-z1.s}'
+[^:]+:42: Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtnt z7.d,{z0.s-z1.s}'
+[^:]+:42: Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtnt z0.b,{z1.s-z2.s}'
+[^:]+:42: Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.s b/gas/testsuite/gas/aarch64/sve2-fp8-fail.s
new file mode 100644
index 00000000000..057bb626247
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.s
@@ -0,0 +1,42 @@
+ /* sve-fp8-fail.s Test file for error-checking AArch64 SVE 8-bit
+ floating-point vector instructions. */
+
+ .macro cvt_pat1, op
+ /* Check element width qualifier for destination register. */
+ \op z0.b, z1.b
+ \op z0.h, z1.b /* Valid. */
+ \op z0.s, z1.b
+ \op z0.d, z1.b
+ /* Check element width qualifier for source register. */
+ \op z0.h, z1.b /* Valid. */
+ \op z0.h, z1.h
+ \op z0.h, z1.s
+ \op z0.h, z1.d
+ /* Ensure predicate register is not allowed. */
+ \op z0.h, p0, z1.d
+ \op z0.h, p0/z, z1.d
+ .endm
+
+ .macro cvt_pat2, op, width
+ /* Check element width qualifier for destination register. */
+ \op z0.b, { z0.\width - z1.\width } /* Valid. */
+ \op z1.h, { z0.\width - z1.\width }
+ \op z0.s, { z0.\width - z1.\width }
+ \op z7.d, { z0.\width - z1.\width }
+ /* Check whether source register range starts at even register. */
+ \op z0.b, { z1.\width - z2.\width }
+ .endm
+
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+ cvt_pat1 bf1cvtlt
+ cvt_pat1 bf2cvtlt
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+ cvt_pat1 f1cvtlt
+ cvt_pat1 f2cvtlt
+
+ cvt_pat2 bfcvtn, h
+ cvt_pat2 fcvtn, h
+ cvt_pat2 fcvtnb, s
+ cvt_pat2 fcvtnt, s
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8.d b/gas/testsuite/gas/aarch64/sve2-fp8.d
new file mode 100644
index 00000000000..774b8e79d09
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.5-a+fp8+sve2
+#objdump: -dr
+#dump: sve2-fp8-dump
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8.s b/gas/testsuite/gas/aarch64/sve2-fp8.s
new file mode 100644
index 00000000000..62dee7334cc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8.s
@@ -0,0 +1,48 @@
+ /* sve-fp8.s Test file for AArch64 SVE 8-bit floating-point vector
+ instructions. */
+
+ .macro cvt_pat1, op
+ \op z0.h, z0.b
+ \op z1.h, z0.b
+ \op z0.h, z1.b
+ \op z30.h, z31.b
+ .endm
+
+ .macro cvt_pat2, op, width
+ \op z0.b, { z0.\width - z1.\width }
+ \op z1.b, { z0.\width - z1.\width }
+ \op z0.b, { z2.\width - z3.\width }
+ \op z29.b, { z30.\width - z31.\width }
+ .endm
+
+ /* 8-bit floating-point convert to BFloat16 (top/bottom) with scaling by
+ 2^-UInt(FPMR.LSCALE{2}[5:0]). */
+
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+ cvt_pat1 bf1cvtlt
+ cvt_pat1 bf2cvtlt
+
+ /* 8-bit floating-point convert to half-precision (top/bottom) with
+ scaling by 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+ cvt_pat1 f1cvtlt
+ cvt_pat1 f2cvtlt
+
+ /* BFloat16 convert, narrow and interleave to 8-bit floating-point
+ with scaling by 2^SInt(FPMR.NSCALE). */
+
+ cvt_pat2 bfcvtn, h
+
+ /* Half-precision convert, narrow and interleave to 8-bit floating-point
+ with scaling by 2^SInt(FPMR.NSCALE[4:0]). */
+
+ cvt_pat2 fcvtn, h
+
+ /* Single-precision convert, narrow and interleave to 8-bit
+ floating-point (top/bottom) 2^SInt(FPMR.NSCALE). */
+
+ cvt_pat2 fcvtnb, s
+ cvt_pat2 fcvtnt, s
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 2268bf6983a..36d474403e2 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10334,7 +10334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3346;
+ return 3358;
}
else
{
@@ -10342,7 +10342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3347;
+ return 3359;
}
}
}
@@ -11260,7 +11260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3348;
+ return 3360;
}
else
{
@@ -11268,7 +11268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3349;
+ return 3361;
}
}
}
@@ -11353,7 +11353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3350;
+ return 3362;
}
else
{
@@ -11460,7 +11460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3352;
+ return 3364;
}
else
{
@@ -11665,7 +11665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3351;
+ return 3363;
}
else
{
@@ -11706,7 +11706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3353;
+ return 3365;
}
else
{
@@ -13364,7 +13364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3355;
+ return 3367;
}
}
else
@@ -13394,7 +13394,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3354;
+ return 3366;
}
}
}
@@ -20817,11 +20817,55 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0x1000001xxxxxxxxxxxxx
- fadda. */
- return 1447;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x00xxxxxxxxxx
+ f1cvt. */
+ return 3350;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x10xxxxxxxxxx
+ bf1cvt. */
+ return 3346;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x01xxxxxxxxxx
+ f2cvt. */
+ return 3351;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx001000001x11xxxxxxxxxx
+ bf2cvt. */
+ return 3347;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx011000001xxxxxxxxxxxxx
+ fadda. */
+ return 1447;
+ }
}
}
else
@@ -20837,11 +20881,55 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 18) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx010001xxxxxxxxxxxxx
- fcmeq. */
- return 1453;
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0010001xxxxxxxxxxxxx
+ fcmeq. */
+ return 1453;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x00xxxxxxxxxx
+ fcvtn. */
+ return 3355;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x10xxxxxxxxxx
+ bfcvtn. */
+ return 3354;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x01xxxxxxxxxx
+ fcvtnb. */
+ return 3356;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1010001x11xxxxxxxxxx
+ fcvtnt. */
+ return 3357;
+ }
+ }
+ }
}
else
{
@@ -20870,21 +20958,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx001001xxxxxxxx0xxxx
- fcmlt. */
- return 1460;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0001001xxxxxxxx0xxxx
+ fcmlt. */
+ return 1460;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0001001xxxxxxxx1xxxx
+ fcmle. */
+ return 1459;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx001001xxxxxxxx1xxxx
- fcmle. */
- return 1459;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x00xxxxxxxxxx
+ f1cvtlt. */
+ return 3352;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x10xxxxxxxxxx
+ bf1cvtlt. */
+ return 3348;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x01xxxxxxxxxx
+ f2cvtlt. */
+ return 3353;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1001001x11xxxxxxxxxx
+ bf2cvtlt. */
+ return 3349;
+ }
+ }
}
}
else
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f876c1b342f..464d9313a37 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1644,6 +1644,14 @@
{ \
QLF2(S_H,S_B), \
}
+#define OP_SVE_BH \
+{ \
+ QLF2(S_B,S_H), \
+}
+#define OP_SVE_BS \
+{ \
+ QLF2(S_B,S_S), \
+}
#define OP_SVE_HHH \
{ \
QLF3(S_H,S_H,S_H), \
@@ -6500,6 +6508,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FP8_INSN("fcvtn", 0xe40f400, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3_BHH, F_SIZEQ),
FP8_INSN("fscale", 0x2ec03c00, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_VSHIFT_H, F_SIZEQ),
FP8_INSN("fscale", 0x2ea0fc00, 0xbfa0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ),
+ FP8_SVE2_INSN ("bf1cvt", 0x65083800, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf2cvt", 0x65083c00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf1cvtlt", 0x65093800, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bf2cvtlt", 0x65093c00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f1cvt", 0x65083000, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f2cvt", 0x65083400, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f1cvtlt", 0x65093000, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("f2cvtlt", 0x65093400, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SVE2_INSN ("bfcvtn", 0x650a3800, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SVE2_INSN ("fcvtn", 0x650a3000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SVE2_INSN ("fcvtnb", 0x650a3400, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
+ FP8_SVE2_INSN ("fcvtnt", 0x650a3c00, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
/* Checked Pointer Arithmetic Instructions. */
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 insn variants
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
` (2 preceding siblings ...)
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
@ 2024-04-10 15:29 ` Victor Do Nascimento
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
4 siblings, 0 replies; 7+ messages in thread
From: Victor Do Nascimento @ 2024-04-10 15:29 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
From: Victor Do Nascimento <vicdon01@e133397.arm.com>
Add the SME2 variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+sme2+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
Multi-vector floating-point convert from FP8 to
BFloat16 (in-order):
-----------------------------------------------
- bf1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved BFloat16:
-----------------------------------------------
- bf1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from BFloat16
to packed FP8 format:
-------------------------------------------------
- bfcvt <Zd>.B, { <Zn1>.H-<Zn2>.H }
Multi-vector floating-point convert from FP8 to
half-precision (in-order):
-----------------------------------------------
- f1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved half-precision:
-----------------------------------------------
- f1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from half-precision
to packed FP8 format:
-------------------------------------------------------
fcvt_2h
Multi-vector floating-point convert from single-precision
to packed FP8 format:
---------------------------------------------------------
fcvt_4s
Multi-vector floating-point convert from single-precision
to interleaved FP8 format:
---------------------------------------------------------
- fcvtn <Zd>.B, { <Zn1>.S-<Zn4>.S }
Multi-vector floating-point adjust exponent by vector:
------------------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
<Zm>.H
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
<Zm>.S
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
<Zm>.D
Multi-vector floating-point adjust exponent:
--------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
{ <Zm1>.H - <Zm2>.H }
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
{ <Zm1>.S - <Zm2>.S }
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
{ <Zm1>.D - <Zm2>.D }
---
gas/testsuite/gas/aarch64/sme2-24-invalid.l | 4 +-
gas/testsuite/gas/aarch64/sme2-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/sme2-fp8-fail.l | 273 ++++++++++++
gas/testsuite/gas/aarch64/sme2-fp8-fail.s | 106 +++++
gas/testsuite/gas/aarch64/sme2-fp8.d | 128 ++++++
gas/testsuite/gas/aarch64/sme2-fp8.s | 112 +++++
opcodes/aarch64-dis-2.c | 448 ++++++++++++++------
opcodes/aarch64-tbl.h | 16 +
8 files changed, 951 insertions(+), 138 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.s
diff --git a/gas/testsuite/gas/aarch64/sme2-24-invalid.l b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
index c44a582979d..82dd0fb1308 100644
--- a/gas/testsuite/gas/aarch64/sme2-24-invalid.l
+++ b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
@@ -9,10 +9,10 @@
[^ :]+:[0-9]+: Info: bfcvtn z0\.h, {z0\.s-z3\.s}
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.s,{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: bfcvt z0\.h, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info: bfcvt z0\.b, {z0\.h-z3\.h}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fcvt z0\.h, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: fcvt z0\.b, {z0\.h-z1\.h}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvt z0\.h, {z0\.s-z1\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.d b/gas/testsuite/gas/aarch64/sme2-fp8-fail.d
new file mode 100644
index 00000000000..79f139c2353
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8+sme2 -mno-verbose-error
+#error_output: sme2-fp8-fail.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.l b/gas/testsuite/gas/aarch64/sme2-fp8-fail.l
new file mode 100644
index 00000000000..f25fd60b1bd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.l
@@ -0,0 +1,273 @@
+[^:]+: Assembler messages:
+[^:]+:7: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.h'
+[^:]+:19: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.s'
+[^:]+:19: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.d'
+[^:]+:19: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvt {z0.b-z1.b},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvt {z0.s-z1.s},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvt {z0.d-z1.d},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf1cvt {z1.h-z2.h},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.h'
+[^:]+:20: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.s'
+[^:]+:20: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.d'
+[^:]+:20: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvt {z0.b-z1.b},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvt {z0.s-z1.s},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvt {z0.d-z1.d},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf2cvt {z1.h-z2.h},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.h'
+[^:]+:21: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.s'
+[^:]+:21: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.d'
+[^:]+:21: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvtl {z0.b-z1.b},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtl {z0.s-z1.s},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtl {z0.d-z1.d},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf1cvtl {z1.h-z2.h},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.h'
+[^:]+:22: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.s'
+[^:]+:22: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.d'
+[^:]+:22: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvtl {z0.b-z1.b},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtl {z0.s-z1.s},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtl {z0.d-z1.d},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf2cvtl {z1.h-z2.h},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.h'
+[^:]+:23: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.s'
+[^:]+:23: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.d'
+[^:]+:23: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvt {z0.b-z1.b},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvt {z0.s-z1.s},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvt {z0.d-z1.d},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f1cvt {z1.h-z2.h},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.h'
+[^:]+:24: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.s'
+[^:]+:24: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.d'
+[^:]+:24: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvt {z0.b-z1.b},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvt {z0.s-z1.s},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvt {z0.d-z1.d},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f2cvt {z1.h-z2.h},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.h'
+[^:]+:25: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.s'
+[^:]+:25: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.d'
+[^:]+:25: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvtl {z0.b-z1.b},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtl {z0.s-z1.s},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtl {z0.d-z1.d},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f1cvtl {z1.h-z2.h},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.h'
+[^:]+:26: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.s'
+[^:]+:26: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.d'
+[^:]+:26: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvtl {z0.b-z1.b},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtl {z0.s-z1.s},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtl {z0.d-z1.d},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f2cvtl {z1.h-z2.h},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:31: Error: operand mismatch -- `bfcvt z2.h,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:32: Error: operand mismatch -- `bfcvt z2.s,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:33: Error: operand mismatch -- `bfcvt z2.d,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:35: Error: operand mismatch -- `bfcvt z2.b,{z0.b-z1.b}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bfcvt z2.b,{z0.s-z1.s}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bfcvt z2.b,{z0.d-z1.d}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:40: Error: start register out of range at operand 2 -- `bfcvt z2.b,{z1.h-z2.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:31: Error: operand mismatch -- `fcvt z2.h,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:32: Error: operand mismatch -- `fcvt z2.s,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:33: Error: operand mismatch -- `fcvt z2.d,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:35: Error: operand mismatch -- `fcvt z2.b,{z0.b-z1.b}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:37: Error: expected a list of 4 registers at operand 2 -- `fcvt z2.b,{z0.s-z1.s}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `fcvt z2.b,{z0.d-z1.d}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:40: Error: start register out of range at operand 2 -- `fcvt z2.b,{z1.h-z2.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:49: Error: expected a list of 2 registers at operand 2 -- `fcvtn z4.h,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `fcvtn z4.s,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `fcvtn z4.d,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:53: Error: operand mismatch -- `fcvtn z4.b,{z0.b-z3.b}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:54: Error: expected a list of 2 registers at operand 2 -- `fcvtn z4.b,{z0.h-z3.h}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:56: Error: operand mismatch -- `fcvtn z4.b,{z0.d-z3.d}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:58: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z1.s-z4.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:59: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z2.s-z5.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:60: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z3.s-z6.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:49: Error: expected a list of 2 registers at operand 2 -- `fcvt z4.h,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `fcvt z4.s,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `fcvt z4.d,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:53: Error: operand mismatch -- `fcvt z4.b,{z0.b-z3.b}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:54: Error: expected a list of 2 registers at operand 2 -- `fcvt z4.b,{z0.h-z3.h}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:56: Error: operand mismatch -- `fcvt z4.b,{z0.d-z3.d}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:58: Error: start register out of range at operand 2 -- `fcvt z4.b,{z1.s-z4.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:59: Error: start register out of range at operand 2 -- `fcvt z4.b,{z2.s-z5.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:60: Error: start register out of range at operand 2 -- `fcvt z4.b,{z3.s-z6.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z1.h},{z2.h-z3.h},z2.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},z3.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z3.h},{z1.h-z4.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.h-z4.h},{z1.h-z4.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.h-z5.h},{z2.h-z5.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.h-z6.h},{z3.h-z6.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z1.s},{z2.s-z3.s},z2.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},z3.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z3.s},{z1.s-z4.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.s-z4.s},{z1.s-z4.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.s-z5.s},{z2.s-z5.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.s-z6.s},{z3.s-z6.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z1.d},{z2.d-z3.d},z2.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},z3.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z3.d},{z1.d-z4.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.d-z4.d},{z1.d-z4.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.d-z5.d},{z2.d-z5.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.d-z6.d},{z3.d-z6.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z1.h},{z1.h-z2.h},{z2.h-z3.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},{z2.h-z3.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},{z3.h-z4.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z3.h},{z1.h-z4.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.h-z4.h},{z1.h-z4.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.h-z5.h},{z2.h-z5.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.h-z6.h},{z3.h-z6.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z5.h-z8.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z6.h-z9.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z7.h-z10.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z1.s},{z1.s-z2.s},{z2.s-z3.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},{z2.s-z3.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},{z3.s-z4.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z3.s},{z1.s-z4.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.s-z4.s},{z1.s-z4.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.s-z5.s},{z2.s-z5.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.s-z6.s},{z3.s-z6.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z5.s-z8.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z6.s-z9.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z7.s-z10.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z1.d},{z1.d-z2.d},{z2.d-z3.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},{z2.d-z3.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},{z3.d-z4.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z3.d},{z1.d-z4.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.d-z4.d},{z1.d-z4.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.d-z5.d},{z2.d-z5.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.d-z6.d},{z3.d-z6.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z5.d-z8.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z6.d-z9.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z7.d-z10.d}'
+[^:]+:106: Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.s b/gas/testsuite/gas/aarch64/sme2-fp8-fail.s
new file mode 100644
index 00000000000..612710fdda8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.s
@@ -0,0 +1,106 @@
+ /* sme-fp8-fail.s Test file for error-checking AArch64 SME 8-bit
+ floating-point vector instructions. */
+
+ .macro cvt_pat1, op
+ /* Check element width qualifier for source register. */
+ \op {z0.h-z1.h}, z2.b /* Valid. */
+ \op {z0.h-z1.h}, z2.h
+ \op {z0.h-z1.h}, z2.s
+ \op {z0.h-z1.h}, z2.d
+ /* Check element width qualifier for destination register pair. */
+ \op {z0.b-z1.b}, z2.b
+ \op {z0.h-z1.h}, z2.b /* Valid. */
+ \op {z0.s-z1.s}, z2.b
+ \op {z0.d-z1.d}, z2.b
+ /* Check whether destination register range starts at even register. */
+ \op {z1.h-z2.h}, z2.b
+ .endm
+
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+ cvt_pat1 bf1cvtl
+ cvt_pat1 bf2cvtl
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+ cvt_pat1 f1cvtl
+ cvt_pat1 f2cvtl
+
+ .macro cvt_pat2, op
+ /* Check element width qualifier for destination register. */
+ \op z2.b, {z0.h-z1.h} /* Valid. */
+ \op z2.h, {z0.h-z1.h}
+ \op z2.s, {z0.h-z1.h}
+ \op z2.d, {z0.h-z1.h}
+ /* Check element width qualifier for source register pair. */
+ \op z2.b, {z0.b-z1.b}
+ \op z2.b, {z0.h-z1.h} /* Valid. */
+ \op z2.b, {z0.s-z1.s}
+ \op z2.b, {z0.d-z1.d}
+ /* Check whether source register range starts at even register. */
+ \op z2.b, {z1.h-z2.h}
+ .endm
+
+ cvt_pat2 bfcvt
+ cvt_pat2 fcvt
+
+ .macro cvt_pat3, op
+ /* Check element width qualifier for destination register. */
+ \op z4.b, {z0.s-z3.s} /* Valid. */
+ \op z4.h, {z0.s-z3.s}
+ \op z4.s, {z0.s-z3.s}
+ \op z4.d, {z0.s-z3.s}
+ /* Check element width qualifier for source register pair. */
+ \op z4.b, {z0.b-z3.b}
+ \op z4.b, {z0.h-z3.h}
+ \op z4.b, {z0.s-z3.s} /* Valid. */
+ \op z4.b, {z0.d-z3.d}
+ /* Check whether start of source register range is multiple of 4. */
+ \op z4.b, {z1.s-z4.s}
+ \op z4.b, {z2.s-z5.s}
+ \op z4.b, {z3.s-z6.s}
+ .endm
+
+ cvt_pat3 fcvtn
+ cvt_pat3 fcvt
+
+ .macro fscale_single, w
+ /* pair. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w - z1.\w }, { z2.\w - z3.\w }, z2.\w
+ /* Check first source multi-vector group starts at even register. */
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, z3.\w
+ /* quad. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w-z3.\w }, { z1.\w-z4.\w }, z4.\w
+ /* Check start of first source multi-vector group is multiple of 4. */
+ fscale { z1.\w-z4.\w }, { z1.\w-z4.\w }, z4.\w
+ fscale { z2.\w-z5.\w }, { z2.\w-z5.\w }, z4.\w
+ fscale { z3.\w-z6.\w }, { z3.\w-z6.\w }, z4.\w
+ .endm
+
+ fscale_single h
+ fscale_single s
+ fscale_single d
+
+ .macro fscale_multi, w
+ /* pair. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w - z1.\w }, { z1.\w - z2.\w }, { z2.\w-z3.\w }
+ /* Check multi-vector groups start at even register. */
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, { z2.\w-z3.\w }
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, { z3.\w-z4.\w }
+ /* quad. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w-z3.\w }, { z1.\w-z4.\w }, { z4.\w-z7.\w }
+ /* Check the start of multi-vector group ranges is multiple of 4. */
+ fscale { z1.\w-z4.\w }, { z1.\w-z4.\w }, { z4.\w-z7.\w }
+ fscale { z2.\w-z5.\w }, { z2.\w-z5.\w }, { z4.\w-z7.\w }
+ fscale { z3.\w-z6.\w }, { z3.\w-z6.\w }, { z4.\w-z7.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z5.\w-z8.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z6.\w-z9.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z7.\w-z10.\w }
+ .endm
+
+ fscale_multi h
+ fscale_multi s
+ fscale_multi d
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8.d b/gas/testsuite/gas/aarch64/sme2-fp8.d
new file mode 100644
index 00000000000..8d952d4b8ad
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8.d
@@ -0,0 +1,128 @@
+#as: -march=armv8.5-a+fp8+sme2
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+: c166e040 bf1cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c166e080 bf1cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c166e042 bf1cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c166e082 bf1cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c166e3dc bf1cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1e6e040 bf2cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e080 bf2cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e042 bf2cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e082 bf2cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e3dc bf2cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c166e041 bf1cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c166e081 bf1cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c166e043 bf1cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c166e083 bf1cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c166e3dd bf1cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1e6e041 bf2cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e081 bf2cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e043 bf2cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e083 bf2cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e3dd bf2cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c126e040 f1cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c126e080 f1cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c126e042 f1cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c126e082 f1cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c126e3dc f1cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1a6e040 f2cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e080 f2cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e042 f2cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e082 f2cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e3dc f2cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c126e041 f1cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c126e081 f1cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c126e043 f1cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c126e083 f1cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c126e3dd f1cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1a6e041 f2cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e081 f2cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e043 f2cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e083 f2cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e3dd f2cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c164e002 bfcvt z2.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c164e004 bfcvt z4.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c164e042 bfcvt z2.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164e044 bfcvt z4.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164e39e bfcvt z30.b, {z28.h-z29.h}
+[ ]*[0-9a-f]+: c124e002 fcvt z2.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c124e004 fcvt z4.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c124e042 fcvt z2.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c124e044 fcvt z4.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c124e39e fcvt z30.b, {z28.h-z29.h}
+[ ]*[0-9a-f]+: c134e024 fcvtn z4.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e028 fcvtn z8.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e0a4 fcvtn z4.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e0a8 fcvtn z8.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e33c fcvtn z28.b, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c134e004 fcvt z4.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e008 fcvt z8.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e084 fcvt z4.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e088 fcvt z8.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e31c fcvt z28.b, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c162a180 fscale {z0.h-z1.h}, {z0.h-z1.h}, z2.h
+[ ]*[0-9a-f]+: c162a182 fscale {z2.h-z3.h}, {z2.h-z3.h}, z2.h
+[ ]*[0-9a-f]+: c164a180 fscale {z0.h-z1.h}, {z0.h-z1.h}, z4.h
+[ ]*[0-9a-f]+: c164a182 fscale {z2.h-z3.h}, {z2.h-z3.h}, z4.h
+[ ]*[0-9a-f]+: c16fa198 fscale {z24.h-z25.h}, {z24.h-z25.h}, z15.h
+[ ]*[0-9a-f]+: c164a980 fscale {z0.h-z3.h}, {z0.h-z3.h}, z4.h
+[ ]*[0-9a-f]+: c164a984 fscale {z4.h-z7.h}, {z4.h-z7.h}, z4.h
+[ ]*[0-9a-f]+: c168a980 fscale {z0.h-z3.h}, {z0.h-z3.h}, z8.h
+[ ]*[0-9a-f]+: c168a984 fscale {z4.h-z7.h}, {z4.h-z7.h}, z8.h
+[ ]*[0-9a-f]+: c16fa998 fscale {z24.h-z27.h}, {z24.h-z27.h}, z15.h
+[ ]*[0-9a-f]+: c1a2a180 fscale {z0.s-z1.s}, {z0.s-z1.s}, z2.s
+[ ]*[0-9a-f]+: c1a2a182 fscale {z2.s-z3.s}, {z2.s-z3.s}, z2.s
+[ ]*[0-9a-f]+: c1a4a180 fscale {z0.s-z1.s}, {z0.s-z1.s}, z4.s
+[ ]*[0-9a-f]+: c1a4a182 fscale {z2.s-z3.s}, {z2.s-z3.s}, z4.s
+[ ]*[0-9a-f]+: c1afa198 fscale {z24.s-z25.s}, {z24.s-z25.s}, z15.s
+[ ]*[0-9a-f]+: c1a4a980 fscale {z0.s-z3.s}, {z0.s-z3.s}, z4.s
+[ ]*[0-9a-f]+: c1a4a984 fscale {z4.s-z7.s}, {z4.s-z7.s}, z4.s
+[ ]*[0-9a-f]+: c1a8a980 fscale {z0.s-z3.s}, {z0.s-z3.s}, z8.s
+[ ]*[0-9a-f]+: c1a8a984 fscale {z4.s-z7.s}, {z4.s-z7.s}, z8.s
+[ ]*[0-9a-f]+: c1afa998 fscale {z24.s-z27.s}, {z24.s-z27.s}, z15.s
+[ ]*[0-9a-f]+: c1e2a180 fscale {z0.d-z1.d}, {z0.d-z1.d}, z2.d
+[ ]*[0-9a-f]+: c1e2a182 fscale {z2.d-z3.d}, {z2.d-z3.d}, z2.d
+[ ]*[0-9a-f]+: c1e4a180 fscale {z0.d-z1.d}, {z0.d-z1.d}, z4.d
+[ ]*[0-9a-f]+: c1e4a182 fscale {z2.d-z3.d}, {z2.d-z3.d}, z4.d
+[ ]*[0-9a-f]+: c1efa198 fscale {z24.d-z25.d}, {z24.d-z25.d}, z15.d
+[ ]*[0-9a-f]+: c1e4a980 fscale {z0.d-z3.d}, {z0.d-z3.d}, z4.d
+[ ]*[0-9a-f]+: c1e4a984 fscale {z4.d-z7.d}, {z4.d-z7.d}, z4.d
+[ ]*[0-9a-f]+: c1e8a980 fscale {z0.d-z3.d}, {z0.d-z3.d}, z8.d
+[ ]*[0-9a-f]+: c1e8a984 fscale {z4.d-z7.d}, {z4.d-z7.d}, z8.d
+[ ]*[0-9a-f]+: c1efa998 fscale {z24.d-z27.d}, {z24.d-z27.d}, z15.d
+[ ]*[0-9a-f]+: c162b180 fscale {z0.h-z1.h}, {z0.h-z1.h}, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c162b182 fscale {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164b180 fscale {z0.h-z1.h}, {z0.h-z1.h}, {z4.h-z5.h}
+[ ]*[0-9a-f]+: c164b182 fscale {z2.h-z3.h}, {z2.h-z3.h}, {z4.h-z5.h}
+[ ]*[0-9a-f]+: c176b194 fscale {z20.h-z21.h}, {z20.h-z21.h}, {z22.h-z23.h}
+[ ]*[0-9a-f]+: c164b980 fscale {z0.h-z3.h}, {z0.h-z3.h}, {z4.h-z7.h}
+[ ]*[0-9a-f]+: c164b984 fscale {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+[ ]*[0-9a-f]+: c168b980 fscale {z0.h-z3.h}, {z0.h-z3.h}, {z8.h-z11.h}
+[ ]*[0-9a-f]+: c168b984 fscale {z4.h-z7.h}, {z4.h-z7.h}, {z8.h-z11.h}
+[ ]*[0-9a-f]+: c178b994 fscale {z20.h-z23.h}, {z20.h-z23.h}, {z24.h-z27.h}
+[ ]*[0-9a-f]+: c1a2b180 fscale {z0.s-z1.s}, {z0.s-z1.s}, {z2.s-z3.s}
+[ ]*[0-9a-f]+: c1a2b182 fscale {z2.s-z3.s}, {z2.s-z3.s}, {z2.s-z3.s}
+[ ]*[0-9a-f]+: c1a4b180 fscale {z0.s-z1.s}, {z0.s-z1.s}, {z4.s-z5.s}
+[ ]*[0-9a-f]+: c1a4b182 fscale {z2.s-z3.s}, {z2.s-z3.s}, {z4.s-z5.s}
+[ ]*[0-9a-f]+: c1b6b194 fscale {z20.s-z21.s}, {z20.s-z21.s}, {z22.s-z23.s}
+[ ]*[0-9a-f]+: c1a4b980 fscale {z0.s-z3.s}, {z0.s-z3.s}, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c1a4b984 fscale {z4.s-z7.s}, {z4.s-z7.s}, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c1a8b980 fscale {z0.s-z3.s}, {z0.s-z3.s}, {z8.s-z11.s}
+[ ]*[0-9a-f]+: c1a8b984 fscale {z4.s-z7.s}, {z4.s-z7.s}, {z8.s-z11.s}
+[ ]*[0-9a-f]+: c1b8b994 fscale {z20.s-z23.s}, {z20.s-z23.s}, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c1e2b180 fscale {z0.d-z1.d}, {z0.d-z1.d}, {z2.d-z3.d}
+[ ]*[0-9a-f]+: c1e2b182 fscale {z2.d-z3.d}, {z2.d-z3.d}, {z2.d-z3.d}
+[ ]*[0-9a-f]+: c1e4b180 fscale {z0.d-z1.d}, {z0.d-z1.d}, {z4.d-z5.d}
+[ ]*[0-9a-f]+: c1e4b182 fscale {z2.d-z3.d}, {z2.d-z3.d}, {z4.d-z5.d}
+[ ]*[0-9a-f]+: c1f6b194 fscale {z20.d-z21.d}, {z20.d-z21.d}, {z22.d-z23.d}
+[ ]*[0-9a-f]+: c1e4b980 fscale {z0.d-z3.d}, {z0.d-z3.d}, {z4.d-z7.d}
+[ ]*[0-9a-f]+: c1e4b984 fscale {z4.d-z7.d}, {z4.d-z7.d}, {z4.d-z7.d}
+[ ]*[0-9a-f]+: c1e8b980 fscale {z0.d-z3.d}, {z0.d-z3.d}, {z8.d-z11.d}
+[ ]*[0-9a-f]+: c1e8b984 fscale {z4.d-z7.d}, {z4.d-z7.d}, {z8.d-z11.d}
+[ ]*[0-9a-f]+: c1f8b994 fscale {z20.d-z23.d}, {z20.d-z23.d}, {z24.d-z27.d}
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8.s b/gas/testsuite/gas/aarch64/sme2-fp8.s
new file mode 100644
index 00000000000..ca2a4b4d20a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8.s
@@ -0,0 +1,112 @@
+ /* sme-fp8.s Test file for AArch64 SME 8-bit floating-point
+ vector instructions. */
+
+ .macro cvt_pat1, op
+ \op {z0.h-z1.h}, z2.b
+ \op {z0.h-z1.h}, z4.b
+ \op {z2.h-z3.h}, z2.b
+ \op {z2.h-z3.h}, z4.b
+ \op {z28.h-z29.h}, z30.b
+ .endm
+
+ /* Multi-vector floating-point convert from 8-bit floating-point. */
+
+ /* To BFloat16 (in-order) 2^-UInt(FPMR.LSCALE{2}[5:0]). */
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+
+ /* To deinterleaved BFloat16 (in-order) 2^-UInt(FPMR.LSCALE{2}[5:0]). */
+ cvt_pat1 bf1cvtl
+ cvt_pat1 bf2cvtl
+
+ /* To half-precision (in-order) 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+
+ /* To deinterleaved half-precision 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+ cvt_pat1 f1cvtl
+ cvt_pat1 f2cvtl
+
+ .macro cvt_pat2, op
+ \op z2.b, {z0.h-z1.h}
+ \op z4.b, {z0.h-z1.h}
+ \op z2.b, {z2.h-z3.h}
+ \op z4.b, {z2.h-z3.h}
+ \op z30.b, {z28.h-z29.h}
+ .endm
+
+ /* Multi-vector floating-point convert to packed 8-bit floating-point
+ format. */
+
+ /* From BFloat16 with 2^SInt(FPMR.NSCALE) scaling. */
+ cvt_pat2 bfcvt
+
+ /* From half-precision with 2^SInt(FPMR.NSCALE[4:0]) scaling. */
+ cvt_pat2 fcvt
+
+ .macro cvt_pat3, op
+ \op z4.b, {z0.s-z3.s}
+ \op z8.b, {z0.s-z3.s}
+ \op z4.b, {z4.s-z7.s}
+ \op z8.b, {z4.s-z7.s}
+ \op z28.b, {z24.s-z27.s}
+ .endm
+
+ /* Multi-vector floating-point convert from single-precision to
+ {interleaved|packed} 8-bit floating-point format with
+ 2^SInt(FPMR.NSCALE) scaling. */
+
+ cvt_pat3 fcvtn /* interleaved. */
+ cvt_pat3 fcvt /* packed. */
+
+ .macro fscale_single, w
+ /* pair. */
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, z2.\w
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, z2.\w
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, z4.\w
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, z4.\w
+ fscale { z24.\w-z25.\w }, { z24.\w-z25.\w }, z15.\w
+ /* quad. */
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, z4.\w
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, z4.\w
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, z8.\w
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, z8.\w
+ fscale { z24.\w-z27.\w }, { z24.\w-z27.\w }, z15.\w
+ .endm
+
+ /* Multi-vector floating-point adjust exponent by vector.
+
+ Multiply floating-point elements of the 2 or 4 first source vecs by
+ 2.0^SInt(vals in the corresponding elements of 2nd source vector)
+ and destructively place results in corresponding elements of 2 or 4
+ first source vectors. */
+
+ fscale_single h
+ fscale_single s
+ fscale_single d
+
+ .macro fscale_multi, w
+ /* pair. */
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, { z2.\w-z3.\w }
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, { z2.\w-z3.\w }
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, { z4.\w-z5.\w }
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, { z4.\w-z5.\w }
+ fscale { z20.\w-z21.\w }, { z20.\w-z21.\w }, { z22.\w-z23.\w }
+ /* quad. */
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z4.\w-z7.\w }
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, { z4.\w-z7.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z8.\w-z11.\w }
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, { z8.\w-z11.\w }
+ fscale { z20.\w-z23.\w }, { z20.\w-z23.\w }, { z24.\w-z27.\w }
+ .endm
+
+ /* Multi-vector floating-point adjust exponent.
+
+ Multiply floating-point elements of the 2 or 4 first source vecs by
+ 2.0^SInt(vals in the corresponding elements of the 2 or 4 2nd source
+ vectors) and destructively place results in corresponding elements
+ of 2 or 4 first source vectors. */
+
+ fscale_multi h
+ fscale_multi s
+ fscale_multi d
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 36d474403e2..46f4e2ff1fa 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4465,33 +4465,44 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx101000x0xx0xxxx0
- smax. */
- return 2710;
- }
- else
+ if (((word >> 7) & 0x1) == 0)
{
- if (((word >> 9) & 0x1) == 0)
+ if (((word >> 8) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx10100001xx0xxxx0
- fmax. */
- return 2545;
+ x1000001xx1xxxxx101000x00x0xxxx0
+ smax. */
+ return 2710;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx10100011xx0xxxx0
- add. */
- return 2499;
+ if (((word >> 9) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000010x0xxxx0
+ fmax. */
+ return 2545;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000110x0xxxx0
+ add. */
+ return 2499;
+ }
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000xx1x0xxxx0
+ fscale. */
+ return 3370;
+ }
}
else
{
@@ -4581,9 +4592,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
if (((word >> 18) & 0x1) == 0)
{
@@ -4627,46 +4638,35 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
}
else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10x100111000xxxx0xxxxx
- frinta. */
- return 2589;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11x100111000xxxx0xxxxx
- frinta. */
- return 2590;
- }
- }
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
{
if (((word >> 19) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx100010111000xxxx0xxxxx
- scvtf. */
- return 2694;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x0100100111000xxxx0xxxxx
+ fcvt. */
+ return 3367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x1100100111000xxxx0xxxxx
+ bfcvt. */
+ return 3362;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx110010111000xxxx0xxxxx
- scvtf. */
- return 2695;
+ x1000001xx110100111000xxxx0xxxxx
+ fcvt. */
+ return 3368;
}
}
else
@@ -4675,79 +4675,222 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx101010111000xxxx0xxxxx
- frintm. */
- return 2591;
+ x1000001xx101100111000xxxx0xxxxx
+ frinta. */
+ return 2589;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx111010111000xxxx0xxxxx
- frintm. */
- return 2592;
+ x1000001xx111100111000xxxx0xxxxx
+ frinta. */
+ return 2590;
}
}
}
- else
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 1) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx110111000xxxx0xxx0x
- zip. */
- return 2959;
+ x1000001x01xx000111000xxxx1xxxxx
+ fcvtn. */
+ return 2534;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx110111000xxxx0xxx1x
- uzp. */
- return 2946;
+ x1000001x11xx000111000xxxx1xxxxx
+ bfcvtn. */
+ return 2502;
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx100111000xxxx1xxxxx
+ fcvtn. */
+ return 3369;
+ }
}
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 0) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x01xxx00111000xxxx1xxxxx
- fcvtn. */
- return 2534;
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx100010111000xxxx0xxxx0
+ scvtf. */
+ return 2694;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx110010111000xxxx0xxxx0
+ scvtf. */
+ return 2695;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx101010111000xxxx0xxxx0
+ frintm. */
+ return 2591;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx111010111000xxxx0xxxx0
+ frintm. */
+ return 2592;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx10x010111000xxxx1xxxx0
+ ucvtf. */
+ return 2859;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x010111000xxxx1xxxx0
+ ucvtf. */
+ return 2860;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x11xxx00111000xxxx1xxxxx
- bfcvtn. */
- return 2502;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010x110111000xxxxxxxxx0
+ f1cvt. */
+ return 3363;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x110111000xxxxxxxxx0
+ f2cvt. */
+ return 3364;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110x110111000xxxxxxxxx0
+ bf1cvt. */
+ return 3358;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x110111000xxxxxxxxx0
+ bf2cvt. */
+ return 3359;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 1) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x110111000xxxxxxxx00
+ zip. */
+ return 2959;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x110111000xxxxxxxx10
+ uzp. */
+ return 2946;
+ }
+ }
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xx10111000xxxx1xxxxx
- ucvtf. */
- return 2859;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001001xxx10111000xxxxxxxxx1
+ f1cvtl. */
+ return 3365;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxx10111000xxxxxxxxx1
+ f2cvtl. */
+ return 3366;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xx10111000xxxx1xxxxx
- ucvtf. */
- return 2860;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001011xxx10111000xxxxxxxxx1
+ bf1cvtl. */
+ return 3360;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001111xxx10111000xxxxxxxxx1
+ bf2cvtl. */
+ return 3361;
+ }
}
}
}
@@ -4990,21 +5133,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 6) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
+ if (((word >> 7) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1100x0x00xxxx0
- smax. */
- return 2712;
+ if (((word >> 8) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1100x0000xxxx0
+ smax. */
+ return 2712;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1100x1000xxxx0
+ fmax. */
+ return 2547;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x1100x1x00xxxx0
- fmax. */
- return 2547;
+ x1000001xx1xxxxx1x1100xx100xxxx0
+ fscale. */
+ return 3372;
}
}
else
@@ -5120,53 +5274,75 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 6) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
+ if (((word >> 7) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1010x0x00xxxx0
- smax. */
- return 2711;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110x0x00xxxx0
- smax. */
- return 2713;
- }
- }
- else
- {
- if (((word >> 9) & 0x1) == 0)
+ if (((word >> 8) & 0x1) == 0)
{
if (((word >> 12) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x101001x00xxxx0
- fmax. */
- return 2546;
+ x1000001xx1xxxxx1x1010x0000xxxx0
+ smax. */
+ return 2711;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x111001x00xxxx0
- fmax. */
- return 2548;
+ x1000001xx1xxxxx1x1110x0000xxxx0
+ smax. */
+ return 2713;
+ }
+ }
+ else
+ {
+ if (((word >> 9) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x101001000xxxx0
+ fmax. */
+ return 2546;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x111001000xxxx0
+ fmax. */
+ return 2548;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1x1011000xxxx0
+ add. */
+ return 2500;
}
}
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1010xx100xxxx0
+ fscale. */
+ return 3371;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x1x1011x00xxxx0
- add. */
- return 2500;
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3373;
}
}
}
@@ -10334,7 +10510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3358;
+ return 3374;
}
else
{
@@ -10342,7 +10518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3359;
+ return 3375;
}
}
}
@@ -11260,7 +11436,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3360;
+ return 3376;
}
else
{
@@ -11268,7 +11444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3361;
+ return 3377;
}
}
}
@@ -11353,7 +11529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3362;
+ return 3378;
}
else
{
@@ -11460,7 +11636,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3364;
+ return 3380;
}
else
{
@@ -11665,7 +11841,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3363;
+ return 3379;
}
else
{
@@ -11706,7 +11882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3365;
+ return 3381;
}
else
{
@@ -13364,7 +13540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3367;
+ return 3383;
}
}
else
@@ -13394,7 +13570,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3366;
+ return 3382;
}
}
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 464d9313a37..43153f41d6b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6520,6 +6520,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FP8_SVE2_INSN ("fcvtn", 0x650a3000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
FP8_SVE2_INSN ("fcvtnb", 0x650a3400, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
FP8_SVE2_INSN ("fcvtnt", 0x650a3c00, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("bf1cvt", 0xc166e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf2cvt", 0xc1e6e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf1cvtl", 0xc166e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf2cvtl", 0xc1e6e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bfcvt", 0xc164e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SME2_INSN ("f1cvt", 0xc126e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f2cvt", 0xc1a6e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f1cvtl", 0xc126e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f2cvtl", 0xc1a6e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("fcvt", 0xc124e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SME2_INSN ("fcvt", 0xc134e000, 0xfffffc60, sme_misc, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("fcvtn", 0xc134e020, 0xfffffc60, sme_misc, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("fscale", 0xc120a180, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120a980, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120b180, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120b980, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1),
/* Checked Pointer Arithmetic Instructions. */
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
` (3 preceding siblings ...)
2024-04-10 15:29 ` [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 " Victor Do Nascimento
@ 2024-04-17 9:50 ` Nick Clifton
4 siblings, 0 replies; 7+ messages in thread
From: Nick Clifton @ 2024-04-17 9:50 UTC (permalink / raw)
To: Victor Do Nascimento, binutils; +Cc: richard.earnshaw
Hi Victor,
> Regtested on aarch64-linux-gnu, no new regressions.
>
> [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
>
> Victor Do Nascimento (4):
> aarch64: fp8 convert and scale - add feature flags and related
> structures
> aarch64: fp8 convert and scale - Add advsimd insn variants
> aarch64: fp8 convert and scale - add sve2 insn variants
> aarch64: fp8 convert and scale - add sme2 insn variants
>
> gas/config/tc-aarch64.c | 1 +
> gas/doc/c-aarch64.texi | 2 +
> gas/testsuite/gas/aarch64/advsimd-fp8-fail.d | 2 +
> gas/testsuite/gas/aarch64/advsimd-fp8-fail.l | 262 ++++++
> gas/testsuite/gas/aarch64/advsimd-fp8-fail.s | 121 +++
> gas/testsuite/gas/aarch64/advsimd-fp8.d | 120 +++
> gas/testsuite/gas/aarch64/advsimd-fp8.s | 76 ++
> gas/testsuite/gas/aarch64/sme2-24-invalid.l | 4 +-
> gas/testsuite/gas/aarch64/sme2-fp8-fail.d | 2 +
> gas/testsuite/gas/aarch64/sme2-fp8-fail.l | 273 ++++++
> gas/testsuite/gas/aarch64/sme2-fp8-fail.s | 106 +++
> .../gas/aarch64/sme2-fp8-streaming.d | 4 +
> gas/testsuite/gas/aarch64/sme2-fp8.d | 128 +++
> gas/testsuite/gas/aarch64/sme2-fp8.s | 112 +++
> gas/testsuite/gas/aarch64/sve2-fp8-dump | 53 ++
> gas/testsuite/gas/aarch64/sve2-fp8-fail.d | 2 +
> gas/testsuite/gas/aarch64/sve2-fp8-fail.l | 161 ++++
> gas/testsuite/gas/aarch64/sve2-fp8-fail.s | 42 +
> gas/testsuite/gas/aarch64/sve2-fp8.d | 3 +
> gas/testsuite/gas/aarch64/sve2-fp8.s | 48 +
> include/opcode/aarch64.h | 2 +
> opcodes/aarch64-dis-2.c | 817 ++++++++++++++----
> opcodes/aarch64-tbl.h | 95 ++
> 23 files changed, 2251 insertions(+), 185 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
> create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
> create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
> create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.d
> create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp8.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-dump
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8-fail.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2-fp8.s
Patch series approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
@ 2024-05-17 15:43 ` Richard Earnshaw (lists)
0 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw (lists) @ 2024-05-17 15:43 UTC (permalink / raw)
To: Victor Do Nascimento, binutils; +Cc: nickc
On 10/04/2024 16:29, Victor Do Nascimento wrote:
> @@ -6459,6 +6487,19 @@ const struct aarch64_opcode
> aarch64_opcode_table[] =
> SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> + FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("bf2cvtl2", 0x6ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("f1cvtl", 0x2e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("f1cvtl2", 0x6e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("f2cvtl", 0x2e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("f2cvtl2", 0x6e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("fcvtn", 0xe00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BSS_LOWER, 0),
Nit: The opcode in this pattern is missing the leading zero, which makes it a bit harder to verify. Please can you add that before pushing.
> + FP8_INSN("fcvtn2", 0x4e00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BSS_FULL, 0),
> + FP8_INSN("fcvtn", 0xe40f400, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BHH, F_SIZEQ),
Same here.
> + FP8_INSN("fscale", 0x2ec03c00, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_VSHIFT_H, F_SIZEQ),
> + FP8_INSN("fscale", 0x2ea0fc00, 0xbfa0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3SAMESD, F_SIZEQ),
R.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-05-17 15:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
2024-05-17 15:43 ` Richard Earnshaw (lists)
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 " Victor Do Nascimento
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
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