* [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions
@ 2023-07-01 5:20 Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension Christoph Muellner
` (15 more replies)
0 siblings, 16 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patchset adds support for the RISC-V Vector Cryptography extensions. These
are: Zvbb, Zvbc, Zvkg, Zkvned, Zvknh[a,b], Zvkn, Zvkng, Zvknc, Zvksed, Zvksh,
Zvks, Zvksg, Zvksc.
This is based off the v20230620 version of the Vector Cryptography
specification. The specification is frozen.
https://github.com/riscv/riscv-crypto/releases/tag/v20230620
All extensions come with (passing) tests.
Changes in v6:
* Fix formatting of patch 0009
Christoph Müllner (9):
RISC-V: Add support for the Zvbb ISA extension
RISC-V: Add support for the Zvkg ISA extension
RISC-V: Add support for the Zvkned ISA extension
RISC-V: Add support for the Zvknh[a,b] ISA extensions
RISC-V: Add support for the Zvksed ISA extension
RISC-V: Add support for the Zvksh ISA extension
RISC-V: Add support for the Zvkn ISA extension
RISC-V: Add support for the Zvks ISA extension
binutils: NEWS: Announce new RISC-V vector crypto extensions
Nathan Huckleberry via Binutils (6):
RISC-V: Add support for the Zvbc extension
RISC-V: Allow nested implications for extensions
RISC-V: Add support for the Zvkng ISA extension
RISC-V: Add support for the Zvksg ISA extension
RISC-V: Add support for the Zvknc ISA extension
RISC-V: Add support for the Zvksc ISA extension
bfd/elfxx-riscv.c | 93 ++++++++++++++--
binutils/NEWS | 2 +
gas/config/tc-riscv.c | 13 +++
gas/testsuite/gas/riscv/zvbb.d | 43 ++++++++
gas/testsuite/gas/riscv/zvbb.s | 34 ++++++
gas/testsuite/gas/riscv/zvbc.d | 16 +++
gas/testsuite/gas/riscv/zvbc.s | 8 ++
gas/testsuite/gas/riscv/zvkg.d | 10 ++
gas/testsuite/gas/riscv/zvkg.s | 2 +
gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++
gas/testsuite/gas/riscv/zvkn.s | 36 +++++++
gas/testsuite/gas/riscv/zvknc.d | 18 ++++
gas/testsuite/gas/riscv/zvknc.s | 10 ++
gas/testsuite/gas/riscv/zvkned.d | 21 ++++
gas/testsuite/gas/riscv/zvkned.s | 13 +++
gas/testsuite/gas/riscv/zvkng.d | 12 +++
gas/testsuite/gas/riscv/zvkng.s | 4 +
gas/testsuite/gas/riscv/zvknha.d | 12 +++
gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +
gas/testsuite/gas/riscv/zvknhb.d | 12 +++
gas/testsuite/gas/riscv/zvks.d | 45 ++++++++
gas/testsuite/gas/riscv/zvks.s | 36 +++++++
gas/testsuite/gas/riscv/zvksc.d | 18 ++++
gas/testsuite/gas/riscv/zvksc.s | 10 ++
gas/testsuite/gas/riscv/zvksed.d | 12 +++
gas/testsuite/gas/riscv/zvksed.s | 4 +
gas/testsuite/gas/riscv/zvksg.d | 12 +++
gas/testsuite/gas/riscv/zvksg.s | 4 +
gas/testsuite/gas/riscv/zvksh.d | 11 ++
gas/testsuite/gas/riscv/zvksh.s | 3 +
include/opcode/riscv-opc.h | 137 ++++++++++++++++++++++++
include/opcode/riscv.h | 13 +++
opcodes/riscv-dis.c | 4 +
opcodes/riscv-opc.c | 55 ++++++++++
34 files changed, 764 insertions(+), 7 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zvbb.d
create mode 100644 gas/testsuite/gas/riscv/zvbb.s
create mode 100644 gas/testsuite/gas/riscv/zvbc.d
create mode 100644 gas/testsuite/gas/riscv/zvbc.s
create mode 100644 gas/testsuite/gas/riscv/zvkg.d
create mode 100644 gas/testsuite/gas/riscv/zvkg.s
create mode 100644 gas/testsuite/gas/riscv/zvkn.d
create mode 100644 gas/testsuite/gas/riscv/zvkn.s
create mode 100644 gas/testsuite/gas/riscv/zvknc.d
create mode 100644 gas/testsuite/gas/riscv/zvknc.s
create mode 100644 gas/testsuite/gas/riscv/zvkned.d
create mode 100644 gas/testsuite/gas/riscv/zvkned.s
create mode 100644 gas/testsuite/gas/riscv/zvkng.d
create mode 100644 gas/testsuite/gas/riscv/zvkng.s
create mode 100644 gas/testsuite/gas/riscv/zvknha.d
create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
create mode 100644 gas/testsuite/gas/riscv/zvks.d
create mode 100644 gas/testsuite/gas/riscv/zvks.s
create mode 100644 gas/testsuite/gas/riscv/zvksc.d
create mode 100644 gas/testsuite/gas/riscv/zvksc.s
create mode 100644 gas/testsuite/gas/riscv/zvksed.d
create mode 100644 gas/testsuite/gas/riscv/zvksed.s
create mode 100644 gas/testsuite/gas/riscv/zvksg.d
create mode 100644 gas/testsuite/gas/riscv/zvksg.s
create mode 100644 gas/testsuite/gas/riscv/zvksh.d
create mode 100644 gas/testsuite/gas/riscv/zvksh.s
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension Christoph Muellner
` (14 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvbb is part of the vector crypto extensions.
This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbb.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
string directive.
(riscv_ip): Likewise.
* testsuite/gas/riscv/zvbb.d: New test.
* testsuite/gas/riscv/zvbb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
(MASK_VANDN_VV): New.
(MATCH_VANDN_VX): New.
(MASK_VANDN_VX): New.
(MATCH_VBREV8_V): New.
(MASK_VBREV8_V): New.
(MATCH_VBREV_V): New.
(MASK_VBREV_V): New.
(MATCH_VCLZ_V): New.
(MASK_VCLZ_V): New.
(MATCH_VCPOP_V): New.
(MASK_VCPOP_V): New.
(MATCH_VCTZ_V): New.
(MASK_VCTZ_V): New.
(MATCH_VREV8_V): New.
(MASK_VREV8_V): New.
(MATCH_VROL_VV): New.
(MASK_VROL_VV): New.
(MATCH_VROL_VX): New.
(MASK_VROL_VX): New.
(MATCH_VROR_VI): New.
(MASK_VROR_VI): New.
(MATCH_VROR_VV): New.
(MASK_VROR_VV): New.
(MATCH_VROR_VX): New.
(MASK_VROR_VX): New.
(MATCH_VWSLL_VI): New.
(MASK_VWSLL_VI): New.
(MATCH_VWSLL_VV): New.
(MASK_VWSLL_VV): New.
(MATCH_VWSLL_VX): New.
(MASK_VWSLL_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
(ENCODE_RVV_VI_UIMM6): New.
(enum riscv_insn_class): Add instruction class for Zvbb.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add 'l' as new format string
directive.
* riscv-opc.c: Add Zvbb instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 ++++
gas/config/tc-riscv.c | 13 +++++++++
gas/testsuite/gas/riscv/zvbb.d | 43 +++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zvbb.s | 34 +++++++++++++++++++++++
include/opcode/riscv-opc.h | 50 ++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 5 ++++
opcodes/riscv-dis.c | 4 +++
opcodes/riscv-opc.c | 18 ++++++++++++
8 files changed, 172 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvbb.d
create mode 100644 gas/testsuite/gas/riscv/zvbb.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 497709ef0db..21a4dc8ae8b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1262,6 +1262,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2427,6 +2428,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve64d")
|| riscv_subset_supports (rps, "zve64f")
|| riscv_subset_supports (rps, "zve32f"));
+ case INSN_CLASS_ZVBB:
+ return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2615,6 +2618,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64x' or `zve32x");
case INSN_CLASS_ZVEF:
return _("v' or `zve64d' or `zve64f' or `zve32f");
+ case INSN_CLASS_ZVBB:
+ return _("zvbb");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 6bd3b2f198a..297bb9b2a81 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1341,6 +1341,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'i':
case 'j':
case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+ case 'l': used_bits |= ENCODE_RVV_VI_UIMM6 (-1U); break;
case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
case 'M': break; /* Macro operand, must be a mask register. */
case 'T': break; /* Macro operand, must be a vector register. */
@@ -3069,6 +3070,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
asarg = expr_parse_end;
continue;
+ case 'l': /* 6-bit vector arith unsigned immediate */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number >= 64)
+ as_bad (_("bad value for vector immediate field, "
+ "value must be 0...63"));
+ ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_parse_end;
+ continue;
+
case 'm': /* optional vector mask */
if (*asarg == '\0')
{
diff --git a/gas/testsuite/gas/riscv/zvbb.d b/gas/testsuite/gas/riscv/zvbb.d
new file mode 100644
index 00000000000..c6c9df5c681
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.d
@@ -0,0 +1,43 @@
+#as: -march=rv64gc_zvbb
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
+[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvbb.s b/gas/testsuite/gas/riscv/zvbb.s
new file mode 100644
index 00000000000..7a666ff959b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbb.s
@@ -0,0 +1,34 @@
+ vandn.vv v4, v8, v12
+ vandn.vv v4, v8, v12, v0.t
+ vandn.vx v4, v8, a1
+ vandn.vx v4, v8, a1, v0.t
+ vbrev.v v4, v8
+ vbrev.v v4, v8, v0.t
+ vbrev8.v v4, v8
+ vbrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vclz.v v4, v8
+ vclz.v v4, v8, v0.t
+ vctz.v v4, v8
+ vctz.v v4, v8, v0.t
+ vcpop.v v4, v8
+ vcpop.v v4, v8, v0.t
+ vrol.vv v4, v8, v12
+ vrol.vv v4, v8, v12, v0.t
+ vrol.vx v4, v8, a1
+ vrol.vx v4, v8, a1, v0.t
+ vror.vv v4, v8, v12
+ vror.vv v4, v8, v12, v0.t
+ vror.vx v4, v8, a1
+ vror.vx v4, v8, a1, v0.t
+ vror.vi v4, v8, 0
+ vror.vi v4, v8, 63, v0.t
+ vwsll.vv v4, v8, v12
+ vwsll.vv v4, v8, v12, v0.t
+ vwsll.vx v4, v8, a1
+ vwsll.vx v4, v8, a1, v0.t
+ vwsll.vi v4, v8, 0
+ vwsll.vi v4, v8, 31, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 3d5f6606d91..9003200d2d4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2121,6 +2121,39 @@
#define MASK_VDOTUVV 0xfc00707f
#define MATCH_VFDOTVV 0xe4001057
#define MASK_VFDOTVV 0xfc00707f
+/* Zvbb instructions. */
+#define MATCH_VANDN_VV 0x4000057
+#define MASK_VANDN_VV 0xfc00707f
+#define MATCH_VANDN_VX 0x4004057
+#define MASK_VANDN_VX 0xfc00707f
+#define MATCH_VBREV8_V 0x48042057
+#define MASK_VBREV8_V 0xfc0ff07f
+#define MATCH_VBREV_V 0x48052057
+#define MASK_VBREV_V 0xfc0ff07f
+#define MATCH_VCLZ_V 0x48062057
+#define MASK_VCLZ_V 0xfc0ff07f
+#define MATCH_VCPOP_V 0x48072057
+#define MASK_VCPOP_V 0xfc0ff07f
+#define MATCH_VCTZ_V 0x4806a057
+#define MASK_VCTZ_V 0xfc0ff07f
+#define MATCH_VREV8_V 0x4804a057
+#define MASK_VREV8_V 0xfc0ff07f
+#define MATCH_VROL_VV 0x54000057
+#define MASK_VROL_VV 0xfc00707f
+#define MATCH_VROL_VX 0x54004057
+#define MASK_VROL_VX 0xfc00707f
+#define MATCH_VROR_VI 0x50003057
+#define MASK_VROR_VI 0xf800707f
+#define MATCH_VROR_VV 0x50000057
+#define MASK_VROR_VV 0xfc00707f
+#define MATCH_VROR_VX 0x50004057
+#define MASK_VROR_VX 0xfc00707f
+#define MATCH_VWSLL_VI 0xd4003057
+#define MASK_VWSLL_VI 0xfc00707f
+#define MATCH_VWSLL_VV 0xd4000057
+#define MASK_VWSLL_VV 0xfc00707f
+#define MATCH_VWSLL_VX 0xd4004057
+#define MASK_VWSLL_VX 0xfc00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3230,6 +3263,23 @@ DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zvbb instructions. */
+DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
+DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
+DECLARE_INSN(vbrev8_v, MATCH_VBREV8_V, MASK_VBREV8_V)
+DECLARE_INSN(vbrev_v, MATCH_VBREV_V, MASK_VBREV_V)
+DECLARE_INSN(vclz_v, MATCH_VCLZ_V, MASK_VCLZ_V)
+DECLARE_INSN(vcpop_v, MATCH_VCPOP_V, MASK_VCPOP_V)
+DECLARE_INSN(vctz_v, MATCH_VCTZ_V, MASK_VCTZ_V)
+DECLARE_INSN(vrev8_v, MATCH_VREV8_V, MASK_VREV8_V)
+DECLARE_INSN(vrol_vv, MATCH_VROL_VV, MASK_VROL_VV)
+DECLARE_INSN(vrol_vx, MATCH_VROL_VX, MASK_VROL_VX)
+DECLARE_INSN(vror_vi, MATCH_VROR_VI, MASK_VROR_VI)
+DECLARE_INSN(vror_vv, MATCH_VROR_VV, MASK_VROR_VV)
+DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
+DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
+DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
+DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index e96b95782c4..487856478f3 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
#define EXTRACT_RVV_VI_UIMM(x) \
(RV_X(x, 15, 5))
+#define EXTRACT_RVV_VI_UIMM6(x) \
+ (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
#define EXTRACT_RVV_OFFSET(x) \
(RV_X(x, 29, 3))
#define EXTRACT_RVV_VB_IMM(x) \
@@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 0, 10) << 20)
#define ENCODE_RVV_VC_IMM(x) \
(RV_X(x, 0, 11) << 20)
+#define ENCODE_RVV_VI_UIMM6(x) \
+ (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -410,6 +414,7 @@ enum riscv_insn_class
INSN_CLASS_ZKND_OR_ZKNE,
INSN_CLASS_V,
INSN_CLASS_ZVEF,
+ INSN_CLASS_ZVBB,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 576cd247884..827d9b67437 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -400,6 +400,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_RVV_OFFSET (l));
break;
+ case 'l':
+ print (info->stream, dis_style_immediate, "%d",
+ (int)EXTRACT_RVV_VI_UIMM6 (l));
+ break;
case 'm':
if (!EXTRACT_OPERAND (VMASK, l))
{
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c607e095764..6e8313bac16 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1884,6 +1884,24 @@ const struct riscv_opcode riscv_opcodes[] =
{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
+/* Zvbb instructions. */
+{"vandn.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
+{"vandn.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
+{"vbrev.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV_V, MASK_VBREV_V, match_opcode, 0},
+{"vbrev8.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV8_V, MASK_VBREV8_V, match_opcode, 0},
+{"vrev8.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VREV8_V, MASK_VREV8_V, match_opcode, 0},
+{"vclz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCLZ_V, MASK_VCLZ_V, match_opcode, 0},
+{"vctz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCTZ_V, MASK_VCTZ_V, match_opcode, 0},
+{"vcpop.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCPOP_V, MASK_VCPOP_V, match_opcode, 0},
+{"vrol.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROL_VV, MASK_VROL_VV, match_opcode, 0},
+{"vrol.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROL_VX, MASK_VROL_VX, match_opcode, 0},
+{"vror.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROR_VV, MASK_VROR_VV, match_opcode, 0},
+{"vror.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROR_VX, MASK_VROR_VX, match_opcode, 0},
+{"vror.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VlVm", MATCH_VROR_VI, MASK_VROR_VI, match_opcode, 0},
+{"vwsll.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VWSLL_VV, MASK_VWSLL_VV, match_opcode, 0},
+{"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
+{"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-17 7:02 ` Jan Beulich
2023-07-01 5:20 ` [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension Christoph Muellner
` (13 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Zvbc is part of the crypto vector extensions.
This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbc.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvbc.d: New test.
* testsuite/gas/riscv/zvbc.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
(MASK_VCLMUL_VV): New.
(MATCH_VCLMUL_VX): New.
(MASK_VCLMUL_VX): New.
(MATCH_VCLMULH_VV): New.
(MASK_VCLMULH_VV): New.
(MATCH_VCLMULH_VX): New.
(MASK_VCLMULH_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvbc.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvbc instruction.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++
gas/testsuite/gas/riscv/zvbc.s | 8 ++++++++
include/opcode/riscv-opc.h | 14 ++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 6 ++++++
6 files changed, 50 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvbc.d
create mode 100644 gas/testsuite/gas/riscv/zvbc.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 21a4dc8ae8b..295e0d2c942 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1263,6 +1263,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2430,6 +2431,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve32f"));
case INSN_CLASS_ZVBB:
return riscv_subset_supports (rps, "zvbb");
+ case INSN_CLASS_ZVBC:
+ return riscv_subset_supports (rps, "zvbc");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2620,6 +2623,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64d' or `zve64f' or `zve32f");
case INSN_CLASS_ZVBB:
return _("zvbb");
+ case INSN_CLASS_ZVBC:
+ return _("zvbc");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d
new file mode 100644
index 00000000000..d9213b25b01
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.d
@@ -0,0 +1,16 @@
+#as: -march=rv64gc_zvbc
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s
new file mode 100644
index 00000000000..c302d1eb011
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.s
@@ -0,0 +1,8 @@
+ vclmul.vv v4, v8, v12
+ vclmul.vv v4, v8, v12, v0.t
+ vclmul.vx v4, v8, a1
+ vclmul.vx v4, v8, a1, v0.t
+ vclmulh.vv v4, v8, v12
+ vclmulh.vv v4, v8, v12, v0.t
+ vclmulh.vx v4, v8, a1
+ vclmulh.vx v4, v8, a1, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9003200d2d4..6102feaa557 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2154,6 +2154,15 @@
#define MASK_VWSLL_VV 0xfc00707f
#define MATCH_VWSLL_VX 0xd4004057
#define MASK_VWSLL_VX 0xfc00707f
+/* Zvbc instructions. */
+#define MATCH_VCLMUL_VV 0x30002057
+#define MASK_VCLMUL_VV 0xfc00707f
+#define MATCH_VCLMUL_VX 0x30006057
+#define MASK_VCLMUL_VX 0xfc00707f
+#define MATCH_VCLMULH_VV 0x34002057
+#define MASK_VCLMULH_VV 0xfc00707f
+#define MATCH_VCLMULH_VX 0x34006057
+#define MASK_VCLMULH_VX 0xfc00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3280,6 +3289,11 @@ DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
+/* Zvbc instructions. */
+DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
+DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
+DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
+DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 487856478f3..783b1c01e52 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -415,6 +415,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
+ INSN_CLASS_ZVBC,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6e8313bac16..19a72903510 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
{"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
+/* Zvbc instructions. */
+{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
+{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
+{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
+{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-24 7:14 ` Jan Beulich
2023-07-01 5:20 ` [PATCH v6 04/15] RISC-V: Add support for the Zvkned " Christoph Muellner
` (12 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvkg is part of the vector crypto extensions.
This extension adds the following instructions:
- vghsh.vv
- vgmul.vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkg.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvkg.d: New test.
* testsuite/gas/riscv/zvkg.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VGHSH_VV): New.
(MASK_VGHSH_VV): New.
(MATCH_VGMUL_VV): New.
(MASK_VGMUL_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkg.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvkg instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++
gas/testsuite/gas/riscv/zvkg.s | 2 ++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 30 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkg.d
create mode 100644 gas/testsuite/gas/riscv/zvkg.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 295e0d2c942..84461490835 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1264,6 +1264,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2433,6 +2434,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbb");
case INSN_CLASS_ZVBC:
return riscv_subset_supports (rps, "zvbc");
+ case INSN_CLASS_ZVKG:
+ return riscv_subset_supports (rps, "zvkg");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2625,6 +2628,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbb");
case INSN_CLASS_ZVBC:
return _("zvbc");
+ case INSN_CLASS_ZVKG:
+ return _("zvkg");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..7f898d377b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..b802d6add39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+ vghsh.vv v4, v8, v12
+ vgmul.vv v4, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6102feaa557..8b4b3b2662c 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2163,6 +2163,11 @@
#define MASK_VCLMULH_VV 0xfc00707f
#define MATCH_VCLMULH_VX 0x34006057
#define MASK_VCLMULH_VX 0xfc00707f
+/* Zvkg instructions. */
+#define MATCH_VGHSH_VV 0xb2002077
+#define MASK_VGHSH_VV 0xfe00707f
+#define MATCH_VGMUL_VV 0xa208a077
+#define MASK_VGMUL_VV 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3294,6 +3299,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvkg instructions. */
+DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
+DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 783b1c01e52..b2098867a19 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
INSN_CLASS_ZVEF,
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
+ INSN_CLASS_ZVKG,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 19a72903510..b2aadb1bc79 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1908,6 +1908,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+/* Zvkg instructions. */
+{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
+{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 04/15] RISC-V: Add support for the Zvkned ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (2 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions Christoph Muellner
` (11 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvkned is part of the vector crypto extensions.
This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkned.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvkned.d: New test.
* testsuite/gas/riscv/zvkned.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VAESDF_VS): New.
(MASK_VAESDF_VS): New.
(MATCH_VAESDF_VV): New.
(MASK_VAESDF_VV): New.
(MATCH_VAESDM_VS): New.
(MASK_VAESDM_VS): New.
(MATCH_VAESDM_VV): New.
(MASK_VAESDM_VV): New.
(MATCH_VAESEF_VS): New.
(MASK_VAESEF_VS): New.
(MATCH_VAESEF_VV): New.
(MASK_VAESEF_VV): New.
(MATCH_VAESEM_VS): New.
(MASK_VAESEM_VS): New.
(MATCH_VAESEM_VV): New.
(MASK_VAESEM_VV): New.
(MATCH_VAESKF1_VI): New.
(MASK_VAESKF1_VI): New.
(MATCH_VAESKF2_VI): New.
(MASK_VAESKF2_VI): New.
(MATCH_VAESZ_VS): New.
(MASK_VAESZ_VS): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkned.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvkned instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 13 ++++++++++++
6 files changed, 88 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkned.d
create mode 100644 gas/testsuite/gas/riscv/zvkned.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 84461490835..be8d956f316 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1265,6 +1265,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2436,6 +2437,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvbc");
case INSN_CLASS_ZVKG:
return riscv_subset_supports (rps, "zvkg");
+ case INSN_CLASS_ZVKNED:
+ return riscv_subset_supports (rps, "zvkned");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2630,6 +2633,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvbc");
case INSN_CLASS_ZVKG:
return _("zvkg");
+ case INSN_CLASS_ZVKNED:
+ return _("zvkned");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvkned.d
new file mode 100644
index 00000000000..0b09da9dbc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkned
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvkned.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.s
@@ -0,0 +1,13 @@
+ vaesdf.vv v4, v8
+ vaesdf.vs v4, v8
+ vaesdm.vv v4, v8
+ vaesdm.vs v4, v8
+ vaesef.vv v4, v8
+ vaesef.vs v4, v8
+ vaesem.vv v4, v8
+ vaesem.vs v4, v8
+ vaeskf1.vi v4, v8, 2
+ vaeskf1.vi v4, v8, 14
+ vaeskf2.vi v4, v8, 2
+ vaeskf2.vi v4, v8, 14
+ vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 8b4b3b2662c..b8c3834b819 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2168,6 +2168,29 @@
#define MASK_VGHSH_VV 0xfe00707f
#define MATCH_VGMUL_VV 0xa208a077
#define MASK_VGMUL_VV 0xfe0ff07f
+/* Zvkned instructions. */
+#define MATCH_VAESDF_VS 0xa600a077
+#define MASK_VAESDF_VS 0xfe0ff07f
+#define MATCH_VAESDF_VV 0xa200a077
+#define MASK_VAESDF_VV 0xfe0ff07f
+#define MATCH_VAESDM_VS 0xa6002077
+#define MASK_VAESDM_VS 0xfe0ff07f
+#define MATCH_VAESDM_VV 0xa2002077
+#define MASK_VAESDM_VV 0xfe0ff07f
+#define MATCH_VAESEF_VS 0xa601a077
+#define MASK_VAESEF_VS 0xfe0ff07f
+#define MATCH_VAESEF_VV 0xa201a077
+#define MASK_VAESEF_VV 0xfe0ff07f
+#define MATCH_VAESEM_VS 0xa6012077
+#define MASK_VAESEM_VS 0xfe0ff07f
+#define MATCH_VAESEM_VV 0xa2012077
+#define MASK_VAESEM_VV 0xfe0ff07f
+#define MATCH_VAESKF1_VI 0x8a002077
+#define MASK_VAESKF1_VI 0xfe00707f
+#define MATCH_VAESKF2_VI 0xaa002077
+#define MASK_VAESKF2_VI 0xfe00707f
+#define MATCH_VAESZ_VS 0xa603a077
+#define MASK_VAESZ_VS 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3302,6 +3325,18 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
/* Zvkg instructions. */
DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
+/* Zvkned instructions. */
+DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS)
+DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV)
+DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS)
+DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV)
+DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS)
+DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV)
+DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS)
+DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
+DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
+DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
+DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b2098867a19..5d55dbcedf3 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -417,6 +417,7 @@ enum riscv_insn_class
INSN_CLASS_ZVBB,
INSN_CLASS_ZVBC,
INSN_CLASS_ZVKG,
+ INSN_CLASS_ZVKNED,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b2aadb1bc79..175cf5cc94f 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1912,6 +1912,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+/* Zvkned instructions. */
+{"vaesdf.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdf.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdm.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesdm.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesef.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesef.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesem.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESEM_VV, match_opcode, 0},
+{"vaesem.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESEM_VV, match_opcode, 0},
+{"vaeskf1.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_VAESKF1_VI, match_opcode, 0},
+{"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
+{"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (3 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 04/15] RISC-V: Add support for the Zvkned " Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-03 9:47 ` Nelson Chu
2023-07-01 5:20 ` [PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension Christoph Muellner
` (10 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvknh[a,b] are parts of the vector crypto extensions.
This extension adds the following instructions:
- vsha2ms.vv
- vsha2c[hl].vv
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvknh[a,b].
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvknha.d: New test.
* testsuite/gas/riscv/zvknha_zvknhb.s: New test.
* testsuite/gas/riscv/zvknhb.d: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
(MASK_VSHA2CH_VV): New.
(MATCH_VSHA2CL_VV): New.
(MASK_VSHA2CL_VV): New.
(MATCH_VSHA2MS_VV): New.
(MASK_VSHA2MS_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvknh[a,b].
opcodes/ChangeLog:
* riscv-opc.c: Add Zvknh[a,b] instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 13 +++++++++++++
gas/testsuite/gas/riscv/zvknha.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +++
gas/testsuite/gas/riscv/zvknhb.d | 12 ++++++++++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 3 +++
opcodes/riscv-opc.c | 5 +++++
7 files changed, 59 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvknha.d
create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index be8d956f316..696b5c10147 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1266,6 +1266,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2439,6 +2441,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvkg");
case INSN_CLASS_ZVKNED:
return riscv_subset_supports (rps, "zvkned");
+ case INSN_CLASS_ZVKNHA:
+ return riscv_subset_supports (rps, "zvknha");
+ case INSN_CLASS_ZVKNHB:
+ return riscv_subset_supports (rps, "zvknhb");
+ case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
+ return (riscv_subset_supports (rps, "zvknha")
+ || riscv_subset_supports (rps, "zvknhb"));
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2635,6 +2644,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvkg");
case INSN_CLASS_ZVKNED:
return _("zvkned");
+ case INSN_CLASS_ZVKNHA:
+ return _("zvknha");
+ case INSN_CLASS_ZVKNHB:
+ return _("zvknhb");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvknha.d
new file mode 100644
index 00000000000..36d660f634f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknha
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
new file mode 100644
index 00000000000..d20e6310531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
@@ -0,0 +1,3 @@
+ vsha2ch.vv v4, v8, v12
+ vsha2cl.vv v4, v8, v12
+ vsha2ms.vv v4, v8, v12
diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvknhb.d
new file mode 100644
index 00000000000..ab0f035889e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknhb.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknhb
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index b8c3834b819..95c4188d084 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2191,6 +2191,13 @@
#define MASK_VAESKF2_VI 0xfe00707f
#define MATCH_VAESZ_VS 0xa603a077
#define MASK_VAESZ_VS 0xfe0ff07f
+/* Zvknh[a,b] instructions. */
+#define MATCH_VSHA2CH_VV 0xba002077
+#define MASK_VSHA2CH_VV 0xfe00707f
+#define MATCH_VSHA2CL_VV 0xbe002077
+#define MASK_VSHA2CL_VV 0xfe00707f
+#define MATCH_VSHA2MS_VV 0xb6002077
+#define MASK_VSHA2MS_VV 0xfe00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3337,6 +3344,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
+/* Zvknh[a,b] instructions. */
+DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
+DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
+DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5d55dbcedf3..77207ea79b2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -418,6 +418,9 @@ enum riscv_insn_class
INSN_CLASS_ZVBC,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
+ INSN_CLASS_ZVKNHA,
+ INSN_CLASS_ZVKNHB,
+ INSN_CLASS_ZVKNHA_OR_ZVKNHB,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 175cf5cc94f..297fda85af5 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1925,6 +1925,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
{"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
+/* Zvknh[a,b] instructions. */
+{"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV, match_opcode, 0},
+{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
+{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (4 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 07/15] RISC-V: Add support for the Zvksh " Christoph Muellner
` (9 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvksed is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksed.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksed.d: New test.
* testsuite/gas/riscv/zvksed.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
(MASK_VSM4K_VI): New.
(MATCH_VSM4R_VS): New.
(MASK_VSM4R_VS): New.
(MATCH_VSM4R_VV): New.
(MASK_VSM4R_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksed.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksed instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvksed.s | 4 ++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
6 files changed, 38 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksed.d
create mode 100644 gas/testsuite/gas/riscv/zvksed.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 696b5c10147..f3f8a7401d9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1268,6 +1268,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2448,6 +2449,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
return (riscv_subset_supports (rps, "zvknha")
|| riscv_subset_supports (rps, "zvknhb"));
+ case INSN_CLASS_ZVKSED:
+ return riscv_subset_supports (rps, "zvksed");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2648,6 +2651,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvknha");
case INSN_CLASS_ZVKNHB:
return _("zvknhb");
+ case INSN_CLASS_ZVKSED:
+ return _("zvksed");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+8683a277[ ]+vsm4k.vi[ ]+v4,v8,7
+[ ]+[0-9a-f]+:[ ]+a2882277[ ]+vsm4r.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6882277[ ]+vsm4r.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@
+ vsm4k.vi v4, v8, 0
+ vsm4k.vi v4, v8, 7
+ vsm4r.vv v4, v8
+ vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 95c4188d084..39c0cadd686 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2198,6 +2198,13 @@
#define MASK_VSHA2CL_VV 0xfe00707f
#define MATCH_VSHA2MS_VV 0xb6002077
#define MASK_VSHA2MS_VV 0xfe00707f
+/* Zvksed instructions. */
+#define MATCH_VSM4K_VI 0x86002077
+#define MASK_VSM4K_VI 0xfe00707f
+#define MATCH_VSM4R_VS 0xa6082077
+#define MASK_VSM4R_VS 0xfe0ff07f
+#define MATCH_VSM4R_VV 0xa2082077
+#define MASK_VSM4R_VV 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3348,6 +3355,10 @@ DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
+/* Zvksed instructions. */
+DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
+DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
+DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 77207ea79b2..c378cce71c7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -421,6 +421,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKNHA,
INSN_CLASS_ZVKNHB,
INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+ INSN_CLASS_ZVKSED,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 297fda85af5..095af039040 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1930,6 +1930,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
+/* Zvksed instructions. */
+{"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VSM4K_VI, match_opcode, 0},
+{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
+{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 07/15] RISC-V: Add support for the Zvksh ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (5 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 08/15] RISC-V: Add support for the Zvkn " Christoph Muellner
` (8 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvksh is part of the vector crypto extensions.
This extension adds the following instructions:
- vsm3me.vv
- vsm3c.vi
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksh.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvksh.d: New test.
* testsuite/gas/riscv/zvksh.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VSM3C_VI): New.
(MASK_VSM3C_VI): New.
(MATCH_VSM3ME_VV): New.
(MASK_VSM3ME_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksh.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvksh instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
gas/testsuite/gas/riscv/zvksh.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 32 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksh.d
create mode 100644 gas/testsuite/gas/riscv/zvksh.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f3f8a7401d9..10cdcc2eb84 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1269,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2451,6 +2452,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zvknhb"));
case INSN_CLASS_ZVKSED:
return riscv_subset_supports (rps, "zvksed");
+ case INSN_CLASS_ZVKSH:
+ return riscv_subset_supports (rps, "zvksh");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2653,6 +2656,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvknhb");
case INSN_CLASS_ZVKSED:
return _("zvksed");
+ case INSN_CLASS_ZVKSH:
+ return _("zvksh");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+ae8fa277[ ]+vsm3c.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+82862277[ ]+vsm3me.vv[ ]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@
+ vsm3c.vi v4, v8, 0
+ vsm3c.vi v4, v8, 31
+ vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 39c0cadd686..90f44153750 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2205,6 +2205,11 @@
#define MASK_VSM4R_VS 0xfe0ff07f
#define MATCH_VSM4R_VV 0xa2082077
#define MASK_VSM4R_VV 0xfe0ff07f
+/* Zvksh instructions. */
+#define MATCH_VSM3C_VI 0xae002077
+#define MASK_VSM3C_VI 0xfe00707f
+#define MATCH_VSM3ME_VV 0x82002077
+#define MASK_VSM3ME_VV 0xfe00707f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3359,6 +3364,9 @@ DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
+/* Zvksh instructions. */
+DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI)
+DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c378cce71c7..d859f44fc92 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -422,6 +422,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKNHB,
INSN_CLASS_ZVKNHA_OR_ZVKNHB,
INSN_CLASS_ZVKSED,
+ INSN_CLASS_ZVKSH,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 095af039040..533e3f4a079 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1935,6 +1935,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
+/* Zvksh instructions. */
+{"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0},
+{"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 08/15] RISC-V: Add support for the Zvkn ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (6 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 07/15] RISC-V: Add support for the Zvksh " Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 09/15] RISC-V: Allow nested implications for extensions Christoph Muellner
` (7 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvkn is part of the vector crypto extensions.
Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkn extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkn.d: New test.
* testsuite/gas/riscv/zvkn.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 ++++
gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zvkn.s | 36 +++++++++++++++++++++++++++
3 files changed, 86 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkn.d
create mode 100644 gas/testsuite/gas/riscv/zvkn.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 10cdcc2eb84..426139d4960 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1156,6 +1156,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zks", "zbkx", check_implicit_always},
{"zks", "zksed", check_implicit_always},
{"zks", "zksh", check_implicit_always},
+ {"zvkn", "zvkned", check_implicit_always},
+ {"zvkn", "zvknha", check_implicit_always},
+ {"zvkn", "zvknhb", check_implicit_always},
+ {"zvkn", "zvbb", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@@ -1265,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d
new file mode 100644
index 00000000000..abb92b9f001
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.d
@@ -0,0 +1,45 @@
+#as: -march=rv64gc_zvkn
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
+[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s
new file mode 100644
index 00000000000..44e8f1769ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.s
@@ -0,0 +1,36 @@
+ vaesdf.vv v4, v8
+ vsha2ch.vv v4, v8, v12
+ vandn.vv v4, v8, v12
+ vandn.vv v4, v8, v12, v0.t
+ vandn.vx v4, v8, a1
+ vandn.vx v4, v8, a1, v0.t
+ vbrev.v v4, v8
+ vbrev.v v4, v8, v0.t
+ vbrev8.v v4, v8
+ vbrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vclz.v v4, v8
+ vclz.v v4, v8, v0.t
+ vctz.v v4, v8
+ vctz.v v4, v8, v0.t
+ vcpop.v v4, v8
+ vcpop.v v4, v8, v0.t
+ vrol.vv v4, v8, v12
+ vrol.vv v4, v8, v12, v0.t
+ vrol.vx v4, v8, a1
+ vrol.vx v4, v8, a1, v0.t
+ vror.vv v4, v8, v12
+ vror.vv v4, v8, v12, v0.t
+ vror.vx v4, v8, a1
+ vror.vx v4, v8, a1, v0.t
+ vror.vi v4, v8, 0
+ vror.vi v4, v8, 63, v0.t
+ vwsll.vv v4, v8, v12
+ vwsll.vv v4, v8, v12, v0.t
+ vwsll.vx v4, v8, a1
+ vwsll.vx v4, v8, a1, v0.t
+ vwsll.vi v4, v8, 0
+ vwsll.vi v4, v8, 31, v0.t
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 09/15] RISC-V: Allow nested implications for extensions
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (7 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 08/15] RISC-V: Add support for the Zvkn " Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 10/15] RISC-V: Add support for the Zvkng ISA extension Christoph Muellner
` (6 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Certain extensions require two levels of implications. For example,
zvkng implies zvkn and zvkn implies zvkned. Enabling zvkng should also
enable zvkned.
This patch fixes this behavior.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_add_implicit_subsets): Allow nested
implications for extensions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 426139d4960..f7fb7d88d76 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1873,14 +1873,29 @@ static void
riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
{
struct riscv_implicit_subset *t = riscv_implicit_subsets;
- for (; t->subset_name; t++)
+ bool finished = false;
+ while (!finished)
{
- riscv_subset_t *subset = NULL;
- if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset)
- && t->check_func (t->implicit_name, subset))
- riscv_parse_add_subset (rps, t->implicit_name,
- RISCV_UNKNOWN_VERSION,
- RISCV_UNKNOWN_VERSION, true);
+ finished = true;
+ for (; t->subset_name; t++)
+ {
+ riscv_subset_t *subset = NULL;
+ riscv_subset_t *implicit_subset = NULL;
+ if (riscv_lookup_subset (rps->subset_list, t->subset_name, &subset)
+ && !riscv_lookup_subset (rps->subset_list, t->implicit_name,
+ &implicit_subset)
+ && t->check_func (t->implicit_name, subset))
+ {
+ riscv_parse_add_subset (rps, t->implicit_name,
+ RISCV_UNKNOWN_VERSION,
+ RISCV_UNKNOWN_VERSION, true);
+
+ /* Restart the loop and pick up any new implications. */
+ finished = false;
+ t = riscv_implicit_subsets;
+ break;
+ }
+ }
}
}
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 10/15] RISC-V: Add support for the Zvkng ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (8 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 09/15] RISC-V: Allow nested implications for extensions Christoph Muellner
@ 2023-07-01 5:20 ` Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 11/15] RISC-V: Add support for the Zvks " Christoph Muellner
` (5 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:20 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Zvkng is part of the vector crypto extensions.
Zvkng is shorthand for the following set of extensions:
- Zvkn
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkng extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkng.d: New test.
* testsuite/gas/riscv/zvkng.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zvkng.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvkng.s | 4 ++++
3 files changed, 19 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkng.d
create mode 100644 gas/testsuite/gas/riscv/zvkng.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f7fb7d88d76..60cd74f06d9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1160,6 +1160,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvkn", "zvknha", check_implicit_always},
{"zvkn", "zvknhb", check_implicit_always},
{"zvkn", "zvbb", check_implicit_always},
+ {"zvkng", "zvkn", check_implicit_always},
+ {"zvkng", "zvkg", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@@ -1270,6 +1272,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvkng.d b/gas/testsuite/gas/riscv/zvkng.d
new file mode 100644
index 00000000000..1206350c7e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkng.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvkng
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkng.s b/gas/testsuite/gas/riscv/zvkng.s
new file mode 100644
index 00000000000..5c24ffd63c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkng.s
@@ -0,0 +1,4 @@
+ vaesdf.vv v4, v8
+ vsha2ch.vv v4, v8, v12
+ vghsh.vv v4, v8, v12
+ vgmul.vv v4, v12
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 11/15] RISC-V: Add support for the Zvks ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (9 preceding siblings ...)
2023-07-01 5:20 ` [PATCH v6 10/15] RISC-V: Add support for the Zvkng ISA extension Christoph Muellner
@ 2023-07-01 5:21 ` Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 12/15] RISC-V: Add support for the Zvksg " Christoph Muellner
` (4 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:21 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
Zvks is part of the vector crypto extensions.
Zvks is shorthand for the following set of extensions:
- Zvksed
- Zvksh
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvks extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvks.d: New test.
* testsuite/gas/riscv/zvks.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 4 +++
gas/testsuite/gas/riscv/zvks.d | 45 ++++++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zvks.s | 36 +++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvks.d
create mode 100644 gas/testsuite/gas/riscv/zvks.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 60cd74f06d9..5d51ef6b262 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1162,6 +1162,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvkn", "zvbb", check_implicit_always},
{"zvkng", "zvkn", check_implicit_always},
{"zvkng", "zvkg", check_implicit_always},
+ {"zvks", "zvksed", check_implicit_always},
+ {"zvks", "zvksh", check_implicit_always},
+ {"zvks", "zvbb", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@@ -1278,6 +1281,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvks.d b/gas/testsuite/gas/riscv/zvks.d
new file mode 100644
index 00000000000..2f55630f505
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.d
@@ -0,0 +1,45 @@
+#as: -march=rv64gc_zvks
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t
+[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t
+
diff --git a/gas/testsuite/gas/riscv/zvks.s b/gas/testsuite/gas/riscv/zvks.s
new file mode 100644
index 00000000000..b0d3d824f3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.s
@@ -0,0 +1,36 @@
+ vsm4k.vi v4, v8, 0
+ vsm3c.vi v4, v8, 0
+ vandn.vv v4, v8, v12
+ vandn.vv v4, v8, v12, v0.t
+ vandn.vx v4, v8, a1
+ vandn.vx v4, v8, a1, v0.t
+ vbrev.v v4, v8
+ vbrev.v v4, v8, v0.t
+ vbrev8.v v4, v8
+ vbrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vrev8.v v4, v8
+ vrev8.v v4, v8, v0.t
+ vclz.v v4, v8
+ vclz.v v4, v8, v0.t
+ vctz.v v4, v8
+ vctz.v v4, v8, v0.t
+ vcpop.v v4, v8
+ vcpop.v v4, v8, v0.t
+ vrol.vv v4, v8, v12
+ vrol.vv v4, v8, v12, v0.t
+ vrol.vx v4, v8, a1
+ vrol.vx v4, v8, a1, v0.t
+ vror.vv v4, v8, v12
+ vror.vv v4, v8, v12, v0.t
+ vror.vx v4, v8, a1
+ vror.vx v4, v8, a1, v0.t
+ vror.vi v4, v8, 0
+ vror.vi v4, v8, 63, v0.t
+ vwsll.vv v4, v8, v12
+ vwsll.vv v4, v8, v12, v0.t
+ vwsll.vx v4, v8, a1
+ vwsll.vx v4, v8, a1, v0.t
+ vwsll.vi v4, v8, 0
+ vwsll.vi v4, v8, 31, v0.t
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 12/15] RISC-V: Add support for the Zvksg ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (10 preceding siblings ...)
2023-07-01 5:21 ` [PATCH v6 11/15] RISC-V: Add support for the Zvks " Christoph Muellner
@ 2023-07-01 5:21 ` Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 13/15] RISC-V: Add support for the Zvknc " Christoph Muellner
` (3 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:21 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Zvksg is part of the vector crypto extensions.
Zvksg is shorthand for the following set of extensions:
- Zvks
- Zvkg
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksg extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksg.d: New test.
* testsuite/gas/riscv/zvksg.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zvksg.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zvksg.s | 4 ++++
3 files changed, 19 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksg.d
create mode 100644 gas/testsuite/gas/riscv/zvksg.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 5d51ef6b262..e2a7d8cebcd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1165,6 +1165,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvks", "zvksed", check_implicit_always},
{"zvks", "zvksh", check_implicit_always},
{"zvks", "zvbb", check_implicit_always},
+ {"zvksg", "zvks", check_implicit_always},
+ {"zvksg", "zvkg", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@@ -1282,6 +1284,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvksg.d b/gas/testsuite/gas/riscv/zvksg.d
new file mode 100644
index 00000000000..24a7126e9a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksg.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksg
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvksg.s b/gas/testsuite/gas/riscv/zvksg.s
new file mode 100644
index 00000000000..8da053e1d6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksg.s
@@ -0,0 +1,4 @@
+ vsm4k.vi v4, v8, 0
+ vsm3c.vi v4, v8, 0
+ vghsh.vv v4, v8, v12
+ vgmul.vv v4, v12
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 13/15] RISC-V: Add support for the Zvknc ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (11 preceding siblings ...)
2023-07-01 5:21 ` [PATCH v6 12/15] RISC-V: Add support for the Zvksg " Christoph Muellner
@ 2023-07-01 5:21 ` Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 14/15] RISC-V: Add support for the Zvksc " Christoph Muellner
` (2 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:21 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Zvknc is part of the vector crypto extensions.
Zvknc is shorthand for the following set of extensxions:
- Zvkn
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvknc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvknc.d: New test.
* testsuite/gas/riscv/zvknc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zvknc.d | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zvknc.s | 10 ++++++++++
3 files changed, 31 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvknc.d
create mode 100644 gas/testsuite/gas/riscv/zvknc.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e2a7d8cebcd..95b3ab3c2c7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1162,6 +1162,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvkn", "zvbb", check_implicit_always},
{"zvkng", "zvkn", check_implicit_always},
{"zvkng", "zvkg", check_implicit_always},
+ {"zvknc", "zvkn", check_implicit_always},
+ {"zvknc", "zvbc", check_implicit_always},
{"zvks", "zvksed", check_implicit_always},
{"zvks", "zvksh", check_implicit_always},
{"zvks", "zvbb", check_implicit_always},
@@ -1278,6 +1280,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvknc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvknc.d b/gas/testsuite/gas/riscv/zvknc.d
new file mode 100644
index 00000000000..f68103b129e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvknc
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+32862257[ +vclmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvknc.s b/gas/testsuite/gas/riscv/zvknc.s
new file mode 100644
index 00000000000..60b10d8b8b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.s
@@ -0,0 +1,10 @@
+ vaesdf.vv v4, v8
+ vsha2ch.vv v4, v8, v12
+ vclmul.vv v4, v8, v12
+ vclmul.vv v4, v8, v12, v0.t
+ vclmul.vx v4, v8, a1
+ vclmul.vx v4, v8, a1, v0.t
+ vclmulh.vv v4, v8, v12
+ vclmulh.vv v4, v8, v12, v0.t
+ vclmulh.vx v4, v8, a1
+ vclmulh.vx v4, v8, a1, v0.t
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 14/15] RISC-V: Add support for the Zvksc ISA extension
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (12 preceding siblings ...)
2023-07-01 5:21 ` [PATCH v6 13/15] RISC-V: Add support for the Zvknc " Christoph Muellner
@ 2023-07-01 5:21 ` Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions Christoph Muellner
2023-07-01 13:38 ` [PATCH v6 00/15] RISC-V: Add support for " Palmer Dabbelt
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:21 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Nathan Huckleberry via Binutils <binutils@sourceware.org>
Zvksc is part of the vector crypto extensions.
Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvksc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvksc.d: New test.
* testsuite/gas/riscv/zvksc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zvksc.d | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zvksc.s | 10 ++++++++++
3 files changed, 31 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvksc.d
create mode 100644 gas/testsuite/gas/riscv/zvksc.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 95b3ab3c2c7..d6c8e046e3e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1169,6 +1169,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvks", "zvbb", check_implicit_always},
{"zvksg", "zvks", check_implicit_always},
{"zvksg", "zvkg", check_implicit_always},
+ {"zvksc", "zvks", check_implicit_always},
+ {"zvksc", "zvbc", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
@@ -1288,6 +1290,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvksc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvksc.d b/gas/testsuite/gas/riscv/zvksc.d
new file mode 100644
index 00000000000..8614ede5ccf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvksc
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0
+[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvksc.s b/gas/testsuite/gas/riscv/zvksc.s
new file mode 100644
index 00000000000..aed60105c69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.s
@@ -0,0 +1,10 @@
+ vsm4k.vi v4, v8, 0
+ vsm3c.vi v4, v8, 0
+ vclmul.vv v4, v8, v12
+ vclmul.vv v4, v8, v12, v0.t
+ vclmul.vx v4, v8, a1
+ vclmul.vx v4, v8, a1, v0.t
+ vclmulh.vv v4, v8, v12
+ vclmulh.vv v4, v8, v12, v0.t
+ vclmulh.vx v4, v8, a1
+ vclmulh.vx v4, v8, a1, v0.t
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (13 preceding siblings ...)
2023-07-01 5:21 ` [PATCH v6 14/15] RISC-V: Add support for the Zvksc " Christoph Muellner
@ 2023-07-01 5:21 ` Christoph Muellner
2023-07-01 13:38 ` [PATCH v6 00/15] RISC-V: Add support for " Palmer Dabbelt
15 siblings, 0 replies; 26+ messages in thread
From: Christoph Muellner @ 2023-07-01 5:21 UTC (permalink / raw)
To: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
Cc: Christoph Müllner
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the recently added support of the RISC-V vector crypto
extensions to the NEWS file.
binutils/ChangeLog:
* NEWS: Announce new RISC-V vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
binutils/NEWS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/binutils/NEWS b/binutils/NEWS
index 2e8d51d2773..834e648db6c 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -23,6 +23,8 @@
* The RISC-V port now supports the following new standard extensions:
- Zicond (conditional zero instructions)
- Zfa (additional floating-point instructions)
+ - Zvbb, Zvbc, Zvkg, Zvkned, Zvknh[ab], Zvksed, Zvksh, Zvkn, Zvknc, Zvkng,
+ Zvks, Zvksc, Zvkg, Zvkt (vector crypto instructions)
* The RISC-V port now supports the following vendor-defined extensions:
- XVentanaCondOps
--
2.41.0
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
` (14 preceding siblings ...)
2023-07-01 5:21 ` [PATCH v6 15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions Christoph Muellner
@ 2023-07-01 13:38 ` Palmer Dabbelt
15 siblings, 0 replies; 26+ messages in thread
From: Palmer Dabbelt @ 2023-07-01 13:38 UTC (permalink / raw)
To: christoph.muellner
Cc: binutils, nhuck, nhuck, jeffreyalaw, nelson, Andrew Waterman,
Jim Wilson, philipp.tomsich, christoph.muellner
On Fri, 30 Jun 2023 22:20:49 PDT (-0700), christoph.muellner@vrull.eu wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patchset adds support for the RISC-V Vector Cryptography extensions. These
> are: Zvbb, Zvbc, Zvkg, Zkvned, Zvknh[a,b], Zvkn, Zvkng, Zvknc, Zvksed, Zvksh,
> Zvks, Zvksg, Zvksc.
>
> This is based off the v20230620 version of the Vector Cryptography
> specification. The specification is frozen.
>
> https://github.com/riscv/riscv-crypto/releases/tag/v20230620
>
> All extensions come with (passing) tests.
>
> Changes in v6:
> * Fix formatting of patch 0009
Thanks. The v5 passed the tests, looks like Jeff got the v6 committed a
few minutes ago so everything should be good for the release.
>
> Christoph Müllner (9):
> RISC-V: Add support for the Zvbb ISA extension
> RISC-V: Add support for the Zvkg ISA extension
> RISC-V: Add support for the Zvkned ISA extension
> RISC-V: Add support for the Zvknh[a,b] ISA extensions
> RISC-V: Add support for the Zvksed ISA extension
> RISC-V: Add support for the Zvksh ISA extension
> RISC-V: Add support for the Zvkn ISA extension
> RISC-V: Add support for the Zvks ISA extension
> binutils: NEWS: Announce new RISC-V vector crypto extensions
>
> Nathan Huckleberry via Binutils (6):
> RISC-V: Add support for the Zvbc extension
> RISC-V: Allow nested implications for extensions
> RISC-V: Add support for the Zvkng ISA extension
> RISC-V: Add support for the Zvksg ISA extension
> RISC-V: Add support for the Zvknc ISA extension
> RISC-V: Add support for the Zvksc ISA extension
>
> bfd/elfxx-riscv.c | 93 ++++++++++++++--
> binutils/NEWS | 2 +
> gas/config/tc-riscv.c | 13 +++
> gas/testsuite/gas/riscv/zvbb.d | 43 ++++++++
> gas/testsuite/gas/riscv/zvbb.s | 34 ++++++
> gas/testsuite/gas/riscv/zvbc.d | 16 +++
> gas/testsuite/gas/riscv/zvbc.s | 8 ++
> gas/testsuite/gas/riscv/zvkg.d | 10 ++
> gas/testsuite/gas/riscv/zvkg.s | 2 +
> gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++
> gas/testsuite/gas/riscv/zvkn.s | 36 +++++++
> gas/testsuite/gas/riscv/zvknc.d | 18 ++++
> gas/testsuite/gas/riscv/zvknc.s | 10 ++
> gas/testsuite/gas/riscv/zvkned.d | 21 ++++
> gas/testsuite/gas/riscv/zvkned.s | 13 +++
> gas/testsuite/gas/riscv/zvkng.d | 12 +++
> gas/testsuite/gas/riscv/zvkng.s | 4 +
> gas/testsuite/gas/riscv/zvknha.d | 12 +++
> gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +
> gas/testsuite/gas/riscv/zvknhb.d | 12 +++
> gas/testsuite/gas/riscv/zvks.d | 45 ++++++++
> gas/testsuite/gas/riscv/zvks.s | 36 +++++++
> gas/testsuite/gas/riscv/zvksc.d | 18 ++++
> gas/testsuite/gas/riscv/zvksc.s | 10 ++
> gas/testsuite/gas/riscv/zvksed.d | 12 +++
> gas/testsuite/gas/riscv/zvksed.s | 4 +
> gas/testsuite/gas/riscv/zvksg.d | 12 +++
> gas/testsuite/gas/riscv/zvksg.s | 4 +
> gas/testsuite/gas/riscv/zvksh.d | 11 ++
> gas/testsuite/gas/riscv/zvksh.s | 3 +
> include/opcode/riscv-opc.h | 137 ++++++++++++++++++++++++
> include/opcode/riscv.h | 13 +++
> opcodes/riscv-dis.c | 4 +
> opcodes/riscv-opc.c | 55 ++++++++++
> 34 files changed, 764 insertions(+), 7 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zvbb.d
> create mode 100644 gas/testsuite/gas/riscv/zvbb.s
> create mode 100644 gas/testsuite/gas/riscv/zvbc.d
> create mode 100644 gas/testsuite/gas/riscv/zvbc.s
> create mode 100644 gas/testsuite/gas/riscv/zvkg.d
> create mode 100644 gas/testsuite/gas/riscv/zvkg.s
> create mode 100644 gas/testsuite/gas/riscv/zvkn.d
> create mode 100644 gas/testsuite/gas/riscv/zvkn.s
> create mode 100644 gas/testsuite/gas/riscv/zvknc.d
> create mode 100644 gas/testsuite/gas/riscv/zvknc.s
> create mode 100644 gas/testsuite/gas/riscv/zvkned.d
> create mode 100644 gas/testsuite/gas/riscv/zvkned.s
> create mode 100644 gas/testsuite/gas/riscv/zvkng.d
> create mode 100644 gas/testsuite/gas/riscv/zvkng.s
> create mode 100644 gas/testsuite/gas/riscv/zvknha.d
> create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
> create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
> create mode 100644 gas/testsuite/gas/riscv/zvks.d
> create mode 100644 gas/testsuite/gas/riscv/zvks.s
> create mode 100644 gas/testsuite/gas/riscv/zvksc.d
> create mode 100644 gas/testsuite/gas/riscv/zvksc.s
> create mode 100644 gas/testsuite/gas/riscv/zvksed.d
> create mode 100644 gas/testsuite/gas/riscv/zvksed.s
> create mode 100644 gas/testsuite/gas/riscv/zvksg.d
> create mode 100644 gas/testsuite/gas/riscv/zvksg.s
> create mode 100644 gas/testsuite/gas/riscv/zvksh.d
> create mode 100644 gas/testsuite/gas/riscv/zvksh.s
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions
2023-07-01 5:20 ` [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions Christoph Muellner
@ 2023-07-03 9:47 ` Nelson Chu
2023-07-03 10:10 ` Christoph Müllner
0 siblings, 1 reply; 26+ messages in thread
From: Nelson Chu @ 2023-07-03 9:47 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nathan Huckleberry, nhuck, Jeff Law, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich
[-- Attachment #1: Type: text/plain, Size: 8643 bytes --]
On Sat, Jul 1, 2023 at 1:21 PM Christoph Muellner <
christoph.muellner@vrull.eu> wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> Zvknh[a,b] are parts of the vector crypto extensions.
>
> This extension adds the following instructions:
> - vsha2ms.vv
> - vsha2c[hl].vv
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
> class support for Zvknh[a,b].
> (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zvknha.d: New test.
> * testsuite/gas/riscv/zvknha_zvknhb.s: New test.
> * testsuite/gas/riscv/zvknhb.d: New test.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
> (MASK_VSHA2CH_VV): New.
> (MATCH_VSHA2CL_VV): New.
> (MASK_VSHA2CL_VV): New.
> (MATCH_VSHA2MS_VV): New.
> (MASK_VSHA2MS_VV): New.
> (DECLARE_INSN): New.
> * opcode/riscv.h (enum riscv_insn_class): Add instruction class
> support for Zvknh[a,b].
>
> opcodes/ChangeLog:
>
> * riscv-opc.c: Add Zvknh[a,b] instructions.
>
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> bfd/elfxx-riscv.c | 13 +++++++++++++
> gas/testsuite/gas/riscv/zvknha.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +++
> gas/testsuite/gas/riscv/zvknhb.d | 12 ++++++++++++
> include/opcode/riscv-opc.h | 11 +++++++++++
> include/opcode/riscv.h | 3 +++
> opcodes/riscv-opc.c | 5 +++++
> 7 files changed, 59 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zvknha.d
> create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
> create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index be8d956f316..696b5c10147 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1266,6 +1266,8 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2439,6 +2441,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> return riscv_subset_supports (rps, "zvkg");
> case INSN_CLASS_ZVKNED:
> return riscv_subset_supports (rps, "zvkned");
> + case INSN_CLASS_ZVKNHA:
> + return riscv_subset_supports (rps, "zvknha");
> + case INSN_CLASS_ZVKNHB:
> + return riscv_subset_supports (rps, "zvknhb");
> + case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
> + return (riscv_subset_supports (rps, "zvknha")
> + || riscv_subset_supports (rps, "zvknhb"));
>
Looks like we only have INSN_CLASS_ZVKNHA_OR_ZVKNHB in the opcode table, so
INSN_CLASS_ZVKNHA and INSN_CLASS_ZVKNHB are redundant here.
> case INSN_CLASS_SVINVAL:
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> @@ -2635,6 +2644,10 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return _("zvkg");
> case INSN_CLASS_ZVKNED:
> return _("zvkned");
> + case INSN_CLASS_ZVKNHA:
> + return _("zvknha");
> + case INSN_CLASS_ZVKNHB:
> + return _("zvknhb");
>
Likewise, the INSN_CLASS_ZVKNHA_OR_ZVKNHB define is lost, so I guess it
will return an unreachable INSN_CLASS_* internal error.
> case INSN_CLASS_SVINVAL:
> return "svinval";
> case INSN_CLASS_H:
> diff --git a/gas/testsuite/gas/riscv/zvknha.d
> b/gas/testsuite/gas/riscv/zvknha.d
> new file mode 100644
> index 00000000000..36d660f634f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvknha.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvknha
> +#source: zvknha_zvknhb.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
> diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s
> b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
> new file mode 100644
> index 00000000000..d20e6310531
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
> @@ -0,0 +1,3 @@
> + vsha2ch.vv v4, v8, v12
> + vsha2cl.vv v4, v8, v12
> + vsha2ms.vv v4, v8, v12
> diff --git a/gas/testsuite/gas/riscv/zvknhb.d
> b/gas/testsuite/gas/riscv/zvknhb.d
> new file mode 100644
> index 00000000000..ab0f035889e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvknhb.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64gc_zvknhb
> +#source: zvknha_zvknhb.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index b8c3834b819..95c4188d084 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2191,6 +2191,13 @@
> #define MASK_VAESKF2_VI 0xfe00707f
> #define MATCH_VAESZ_VS 0xa603a077
> #define MASK_VAESZ_VS 0xfe0ff07f
> +/* Zvknh[a,b] instructions. */
> +#define MATCH_VSHA2CH_VV 0xba002077
> +#define MASK_VSHA2CH_VV 0xfe00707f
> +#define MATCH_VSHA2CL_VV 0xbe002077
> +#define MASK_VSHA2CL_VV 0xfe00707f
> +#define MATCH_VSHA2MS_VV 0xb6002077
> +#define MASK_VSHA2MS_VV 0xfe00707f
> /* Svinval instruction. */
> #define MATCH_SINVAL_VMA 0x16000073
> #define MASK_SINVAL_VMA 0xfe007fff
> @@ -3337,6 +3344,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV,
> MASK_VAESEM_VV)
> DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
> DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
> DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
> +/* Zvknh[a,b] instructions. */
> +DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
> +DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
> +DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
> /* Vendor-specific (T-Head) XTheadBa instructions. */
> DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
> /* Vendor-specific (T-Head) XTheadBb instructions. */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 5d55dbcedf3..77207ea79b2 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -418,6 +418,9 @@ enum riscv_insn_class
> INSN_CLASS_ZVBC,
> INSN_CLASS_ZVKG,
> INSN_CLASS_ZVKNED,
> + INSN_CLASS_ZVKNHA,
> + INSN_CLASS_ZVKNHB,
>
Likewise.
> + INSN_CLASS_ZVKNHA_OR_ZVKNHB,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 175cf5cc94f..297fda85af5 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1925,6 +1925,11 @@ const struct riscv_opcode riscv_opcodes[] =
> {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI,
> MASK_VAESKF2_VI, match_opcode, 0},
> {"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS,
> MASK_VAESZ_VS, match_opcode, 0},
>
> +/* Zvknh[a,b] instructions. */
> +{"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs",
> MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV, match_opcode, 0},
> +{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs",
> MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
> +{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs",
> MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
> +
> /* Supervisor instructions. */
> {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS,
> MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
> {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW,
> MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
> --
> 2.41.0
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions
2023-07-03 9:47 ` Nelson Chu
@ 2023-07-03 10:10 ` Christoph Müllner
0 siblings, 0 replies; 26+ messages in thread
From: Christoph Müllner @ 2023-07-03 10:10 UTC (permalink / raw)
To: Nelson Chu
Cc: binutils, Nathan Huckleberry, nhuck, Jeff Law, Andrew Waterman,
Palmer Dabbelt, Jim Wilson, Philipp Tomsich
On Mon, Jul 3, 2023 at 11:47 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
>
>
> On Sat, Jul 1, 2023 at 1:21 PM Christoph Muellner <christoph.muellner@vrull.eu> wrote:
>>
>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> Zvknh[a,b] are parts of the vector crypto extensions.
>>
>> This extension adds the following instructions:
>> - vsha2ms.vv
>> - vsha2c[hl].vv
>>
>> bfd/ChangeLog:
>>
>> * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
>> class support for Zvknh[a,b].
>> (riscv_multi_subset_supports_ext): Likewise.
>>
>> gas/ChangeLog:
>>
>> * testsuite/gas/riscv/zvknha.d: New test.
>> * testsuite/gas/riscv/zvknha_zvknhb.s: New test.
>> * testsuite/gas/riscv/zvknhb.d: New test.
>>
>> include/ChangeLog:
>>
>> * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New.
>> (MASK_VSHA2CH_VV): New.
>> (MATCH_VSHA2CL_VV): New.
>> (MASK_VSHA2CL_VV): New.
>> (MATCH_VSHA2MS_VV): New.
>> (MASK_VSHA2MS_VV): New.
>> (DECLARE_INSN): New.
>> * opcode/riscv.h (enum riscv_insn_class): Add instruction class
>> support for Zvknh[a,b].
>>
>> opcodes/ChangeLog:
>>
>> * riscv-opc.c: Add Zvknh[a,b] instructions.
>>
>> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> ---
>> bfd/elfxx-riscv.c | 13 +++++++++++++
>> gas/testsuite/gas/riscv/zvknha.d | 12 ++++++++++++
>> gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +++
>> gas/testsuite/gas/riscv/zvknhb.d | 12 ++++++++++++
>> include/opcode/riscv-opc.h | 11 +++++++++++
>> include/opcode/riscv.h | 3 +++
>> opcodes/riscv-opc.c | 5 +++++
>> 7 files changed, 59 insertions(+)
>> create mode 100644 gas/testsuite/gas/riscv/zvknha.d
>> create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
>> create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index be8d956f316..696b5c10147 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1266,6 +1266,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>> {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> + {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> + {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> @@ -2439,6 +2441,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>> return riscv_subset_supports (rps, "zvkg");
>> case INSN_CLASS_ZVKNED:
>> return riscv_subset_supports (rps, "zvkned");
>> + case INSN_CLASS_ZVKNHA:
>> + return riscv_subset_supports (rps, "zvknha");
>> + case INSN_CLASS_ZVKNHB:
>> + return riscv_subset_supports (rps, "zvknhb");
>> + case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
>> + return (riscv_subset_supports (rps, "zvknha")
>> + || riscv_subset_supports (rps, "zvknhb"));
>
>
> Looks like we only have INSN_CLASS_ZVKNHA_OR_ZVKNHB in the opcode table, so INSN_CLASS_ZVKNHA and INSN_CLASS_ZVKNHB are redundant here.
Fixed.
>
>>
>> case INSN_CLASS_SVINVAL:
>> return riscv_subset_supports (rps, "svinval");
>> case INSN_CLASS_H:
>> @@ -2635,6 +2644,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
>> return _("zvkg");
>> case INSN_CLASS_ZVKNED:
>> return _("zvkned");
>> + case INSN_CLASS_ZVKNHA:
>> + return _("zvknha");
>> + case INSN_CLASS_ZVKNHB:
>> + return _("zvknhb");
>
>
> Likewise, the INSN_CLASS_ZVKNHA_OR_ZVKNHB define is lost, so I guess it will return an unreachable INSN_CLASS_* internal error.
Fixed.
>
>>
>> case INSN_CLASS_SVINVAL:
>> return "svinval";
>> case INSN_CLASS_H:
>> diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvknha.d
>> new file mode 100644
>> index 00000000000..36d660f634f
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvknha.d
>> @@ -0,0 +1,12 @@
>> +#as: -march=rv64gc_zvknha
>> +#source: zvknha_zvknhb.s
>> +#objdump: -dr
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +0+000 <.text>:
>> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
>> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
>> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
>> diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
>> new file mode 100644
>> index 00000000000..d20e6310531
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
>> @@ -0,0 +1,3 @@
>> + vsha2ch.vv v4, v8, v12
>> + vsha2cl.vv v4, v8, v12
>> + vsha2ms.vv v4, v8, v12
>> diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvknhb.d
>> new file mode 100644
>> index 00000000000..ab0f035889e
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvknhb.d
>> @@ -0,0 +1,12 @@
>> +#as: -march=rv64gc_zvknhb
>> +#source: zvknha_zvknhb.s
>> +#objdump: -dr
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +0+000 <.text>:
>> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
>> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12
>> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index b8c3834b819..95c4188d084 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -2191,6 +2191,13 @@
>> #define MASK_VAESKF2_VI 0xfe00707f
>> #define MATCH_VAESZ_VS 0xa603a077
>> #define MASK_VAESZ_VS 0xfe0ff07f
>> +/* Zvknh[a,b] instructions. */
>> +#define MATCH_VSHA2CH_VV 0xba002077
>> +#define MASK_VSHA2CH_VV 0xfe00707f
>> +#define MATCH_VSHA2CL_VV 0xbe002077
>> +#define MASK_VSHA2CL_VV 0xfe00707f
>> +#define MATCH_VSHA2MS_VV 0xb6002077
>> +#define MASK_VSHA2MS_VV 0xfe00707f
>> /* Svinval instruction. */
>> #define MATCH_SINVAL_VMA 0x16000073
>> #define MASK_SINVAL_VMA 0xfe007fff
>> @@ -3337,6 +3344,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
>> DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
>> DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
>> DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
>> +/* Zvknh[a,b] instructions. */
>> +DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
>> +DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
>> +DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
>> /* Vendor-specific (T-Head) XTheadBa instructions. */
>> DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
>> /* Vendor-specific (T-Head) XTheadBb instructions. */
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index 5d55dbcedf3..77207ea79b2 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -418,6 +418,9 @@ enum riscv_insn_class
>> INSN_CLASS_ZVBC,
>> INSN_CLASS_ZVKG,
>> INSN_CLASS_ZVKNED,
>> + INSN_CLASS_ZVKNHA,
>> + INSN_CLASS_ZVKNHB,
>
>
> Likewise.
Fixed.
Thanks for pointing that out.
Since this got merged, I have sent out a new patch to address this.
BR,
Christoph
>
>>
>> + INSN_CLASS_ZVKNHA_OR_ZVKNHB,
>> INSN_CLASS_SVINVAL,
>> INSN_CLASS_ZICBOM,
>> INSN_CLASS_ZICBOP,
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index 175cf5cc94f..297fda85af5 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -1925,6 +1925,11 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
>> {"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
>>
>> +/* Zvknh[a,b] instructions. */
>> +{"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV, match_opcode, 0},
>> +{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
>> +{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
>> +
>> /* Supervisor instructions. */
>> {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
>> {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
>> --
>> 2.41.0
>>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-01 5:20 ` [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension Christoph Muellner
@ 2023-07-17 7:02 ` Jan Beulich
2023-07-17 7:11 ` Philipp Tomsich
2023-07-17 7:20 ` Christoph Müllner
0 siblings, 2 replies; 26+ messages in thread
From: Jan Beulich @ 2023-07-17 7:02 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
On 01.07.2023 07:20, Christoph Muellner wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
>
> +/* Zvbc instructions. */
> +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
I realize this is more a spec question than an implementation one, but
implementation might be affected by the answer to the question: What
exactly are this and ...
> +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
... this insn doing in RV32 mode? There are no 64 bits to take from
the GPR, yet that's what the doc presently says. Is the value coming
from a pair of GPRs, or is it sign- or zero-extended? Or is this an
RV64-only insn? (Note how the doc explicitly describes the behavior
for vandn's scalar-source form; the only thing left to be implied
there is that truncation / sign-extension are to - I assume - element
size, but maybe that's said somewhere in more general terms.)
As a nit: The two vclmulh lines have one too many blanks, resulting
in columns to not be aligned.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-17 7:02 ` Jan Beulich
@ 2023-07-17 7:11 ` Philipp Tomsich
2023-07-17 7:26 ` Jan Beulich
2023-07-17 7:20 ` Christoph Müllner
1 sibling, 1 reply; 26+ messages in thread
From: Philipp Tomsich @ 2023-07-17 7:11 UTC (permalink / raw)
To: Jan Beulich
Cc: Christoph Muellner, binutils, Nathan Huckleberry, nhuck,
Jeff Law, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson
On Mon, 17 Jul 2023 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 01.07.2023 07:20, Christoph Muellner wrote:
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> > {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
> >
> > +/* Zvbc instructions. */
> > +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> > +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
>
> I realize this is more a spec question than an implementation one, but
> implementation might be affected by the answer to the question: What
> exactly are this and ...
>
> > +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> > +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
>
> ... this insn doing in RV32 mode? There are no 64 bits to take from
> the GPR, yet that's what the doc presently says. Is the value coming
> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> RV64-only insn? (Note how the doc explicitly describes the behavior
> for vandn's scalar-source form; the only thing left to be implied
> there is that truncation / sign-extension are to - I assume - element
> size, but maybe that's said somewhere in more general terms.
According to the pull-request for the SAIL model (which will in the
future be auto-generated into the specification documents and often
clarifies on parts of the specification where the English text is
ambiguous or imprecise), these are defined for RV64 only:
>
> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> + <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
Consequently, these should only be allowed for RV64.
Thanks for catching this!
Philipp.
>
> As a nit: The two vclmulh lines have one too many blanks, resulting
> in columns to not be aligned.
>
> Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-17 7:02 ` Jan Beulich
2023-07-17 7:11 ` Philipp Tomsich
@ 2023-07-17 7:20 ` Christoph Müllner
2023-07-24 21:12 ` [CAUTION - External Sender] " Ken Dockser
1 sibling, 1 reply; 26+ messages in thread
From: Christoph Müllner @ 2023-07-17 7:20 UTC (permalink / raw)
To: Ken Dockser, Nicolas Brunie
Cc: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich,
Jan Beulich
+Ken Dockser
+Nicolas Brunie
I've added Ken and Nicolas (spec authors) to give an authoritative answer, and
because this looks like a valid public-review comment for the specification.
The spec indeed mentions "the 64-bit value from integer register rs1
(vector-scalar)",
which is unclear for RV32.
BR
Christoph
On Mon, Jul 17, 2023 at 9:02 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 01.07.2023 07:20, Christoph Muellner wrote:
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> > {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> > {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
> >
> > +/* Zvbc instructions. */
> > +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> > +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
>
> I realize this is more a spec question than an implementation one, but
> implementation might be affected by the answer to the question: What
> exactly are this and ...
>
> > +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> > +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
>
> ... this insn doing in RV32 mode? There are no 64 bits to take from
> the GPR, yet that's what the doc presently says. Is the value coming
> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> RV64-only insn? (Note how the doc explicitly describes the behavior
> for vandn's scalar-source form; the only thing left to be implied
> there is that truncation / sign-extension are to - I assume - element
> size, but maybe that's said somewhere in more general terms.)
>
> As a nit: The two vclmulh lines have one too many blanks, resulting
> in columns to not be aligned.
>
> Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-17 7:11 ` Philipp Tomsich
@ 2023-07-17 7:26 ` Jan Beulich
2023-07-17 7:28 ` Philipp Tomsich
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2023-07-17 7:26 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Christoph Muellner, binutils, Nathan Huckleberry, nhuck,
Jeff Law, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson
On 17.07.2023 09:11, Philipp Tomsich wrote:
> On Mon, 17 Jul 2023 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 01.07.2023 07:20, Christoph Muellner wrote:
>>> --- a/opcodes/riscv-opc.c
>>> +++ b/opcodes/riscv-opc.c
>>> @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
>>> {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
>>> {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
>>>
>>> +/* Zvbc instructions. */
>>> +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
>>> +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
>>
>> I realize this is more a spec question than an implementation one, but
>> implementation might be affected by the answer to the question: What
>> exactly are this and ...
>>
>>> +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
>>> +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
>>
>> ... this insn doing in RV32 mode? There are no 64 bits to take from
>> the GPR, yet that's what the doc presently says. Is the value coming
>> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
>> RV64-only insn? (Note how the doc explicitly describes the behavior
>> for vandn's scalar-source form; the only thing left to be implied
>> there is that truncation / sign-extension are to - I assume - element
>> size, but maybe that's said somewhere in more general terms.
>
>
> According to the pull-request for the SAIL model (which will in the
> future be auto-generated into the specification documents and often
> clarifies on parts of the specification where the English text is
> ambiguous or imprecise), these are defined for RV64 only:
>>
>> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
>> + <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
>
> Consequently, these should only be allowed for RV64.
Oh, even the .vv insn is RV64 only (I had asked about the .vx one)? Plus
then why not sizeof(xlen) >= 64?
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-17 7:26 ` Jan Beulich
@ 2023-07-17 7:28 ` Philipp Tomsich
0 siblings, 0 replies; 26+ messages in thread
From: Philipp Tomsich @ 2023-07-17 7:28 UTC (permalink / raw)
To: Jan Beulich
Cc: Christoph Muellner, binutils, Nathan Huckleberry, nhuck,
Jeff Law, Nelson Chu, Andrew Waterman, Palmer Dabbelt,
Jim Wilson
Same on the .vv:
>
> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & have Zvbc() & sizeof(xlen) == 64)
+ <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if
(haveRVV() & have Zvbc() & sizeof(xlen) == 64)
On Mon, 17 Jul 2023 at 09:26, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 17.07.2023 09:11, Philipp Tomsich wrote:
> > On Mon, 17 Jul 2023 at 09:02, Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 01.07.2023 07:20, Christoph Muellner wrote:
> >>> --- a/opcodes/riscv-opc.c
> >>> +++ b/opcodes/riscv-opc.c
> >>> @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> >>> {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
> >>> {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
> >>>
> >>> +/* Zvbc instructions. */
> >>> +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
> >>> +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
> >>
> >> I realize this is more a spec question than an implementation one, but
> >> implementation might be affected by the answer to the question: What
> >> exactly are this and ...
> >>
> >>> +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
> >>> +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
> >>
> >> ... this insn doing in RV32 mode? There are no 64 bits to take from
> >> the GPR, yet that's what the doc presently says. Is the value coming
> >> from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> >> RV64-only insn? (Note how the doc explicitly describes the behavior
> >> for vandn's scalar-source form; the only thing left to be implied
> >> there is that truncation / sign-extension are to - I assume - element
> >> size, but maybe that's said somewhere in more general terms.
> >
> >
> > According to the pull-request for the SAIL model (which will in the
> > future be auto-generated into the specification documents and often
> > clarifies on parts of the specification where the English text is
> > ambiguous or imprecise), these are defined for RV64 only:
> >>
> >> +mapping clause encdec = RISCV_VCLMULH_VV(vm, vs1, vs2, vd) if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> >> + <-> 0b001101 @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if (haveRVV() & haveZvbc() & sizeof(xlen) == 64)
> >
> > Consequently, these should only be allowed for RV64.
>
> Oh, even the .vv insn is RV64 only (I had asked about the .vx one)? Plus
> then why not sizeof(xlen) >= 64?
>
> Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension
2023-07-01 5:20 ` [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension Christoph Muellner
@ 2023-07-24 7:14 ` Jan Beulich
0 siblings, 0 replies; 26+ messages in thread
From: Jan Beulich @ 2023-07-24 7:14 UTC (permalink / raw)
To: Christoph Muellner
Cc: binutils, Nathan Huckleberry, nhuck, Jeff Law, Nelson Chu,
Andrew Waterman, Palmer Dabbelt, Jim Wilson, Philipp Tomsich
On 01.07.2023 07:20, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> Zvkg is part of the vector crypto extensions.
>
> This extension adds the following instructions:
> - vghsh.vv
> - vgmul.vv
I'm afraid I again have a question here which is more towards the spec
than the implementation. Also the above two are merely good examples,
there are other insns throughout the series to which the question also
applies.
I'm wondering about the suffixes here. The base model (conversion and
other more "special" insns excluded) of the V extension looks to be to
have the suffixes name the forms of the inputs. Depending on whether
vd being both input and output is also accounted for, this would make
the above two either vghsh.vv and vgmul.v or vghsh.vvv and vgmul.vv.
(The underlying observation was that 2-operand and 3-operand insns
unexpectedly have identical suffixes.)
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [CAUTION - External Sender] Re: [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension
2023-07-17 7:20 ` Christoph Müllner
@ 2023-07-24 21:12 ` Ken Dockser
0 siblings, 0 replies; 26+ messages in thread
From: Ken Dockser @ 2023-07-24 21:12 UTC (permalink / raw)
To: Christoph Müllner
Cc: Nicolas Brunie, binutils, Nathan Huckleberry, nhuck, Jeff Law,
Nelson Chu, Andrew Waterman, Palmer Dabbelt, Jim Wilson,
Philipp Tomsich, Jan Beulich
[-- Attachment #1: Type: text/plain, Size: 2820 bytes --]
Hi,
This instruction is supported in RV32. The answer is in the pseudo code:
let op1 : bits (64) = if suffix =="vv" then get_velem(vs1,i)
else zext_or_truncate_to_sew(X(vs1));
The xv form of the instruction reads X(vs2) and zero-extends it to SEW=64.
When you need something other than 0s in the upper 32 bits of the vs1
operand, the vx form will not be very useful in RV32. However, the vv form
will continue to operate.
It looks like the SAIL code needs to be updated to match the spec.
Thanks,
Ken
On Mon, Jul 17, 2023 at 2:20 AM Christoph Müllner <
christoph.muellner@vrull.eu> wrote:
> +Ken Dockser
> +Nicolas Brunie
>
> I've added Ken and Nicolas (spec authors) to give an authoritative answer,
> and
> because this looks like a valid public-review comment for the
> specification.
>
> The spec indeed mentions "the 64-bit value from integer register rs1
> (vector-scalar)",
> which is unclear for RV32.
>
> BR
> Christoph
>
> On Mon, Jul 17, 2023 at 9:02 AM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 01.07.2023 07:20, Christoph Muellner wrote:
> > > --- a/opcodes/riscv-opc.c
> > > +++ b/opcodes/riscv-opc.c
> > > @@ -1902,6 +1902,12 @@ const struct riscv_opcode riscv_opcodes[] =
> > > {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX,
> MASK_VWSLL_VX, match_opcode, 0},
> > > {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI,
> MASK_VWSLL_VI, match_opcode, 0},
> > >
> > > +/* Zvbc instructions. */
> > > +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV,
> MASK_VCLMUL_VV, match_opcode, 0},
> > > +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX,
> MASK_VCLMUL_VX, match_opcode, 0},
> >
> > I realize this is more a spec question than an implementation one, but
> > implementation might be affected by the answer to the question: What
> > exactly are this and ...
> >
> > > +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV,
> MASK_VCLMULH_VV, match_opcode, 0},
> > > +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX,
> MASK_VCLMULH_VX, match_opcode, 0},
> >
> > ... this insn doing in RV32 mode? There are no 64 bits to take from
> > the GPR, yet that's what the doc presently says. Is the value coming
> > from a pair of GPRs, or is it sign- or zero-extended? Or is this an
> > RV64-only insn? (Note how the doc explicitly describes the behavior
> > for vandn's scalar-source form; the only thing left to be implied
> > there is that truncation / sign-extension are to - I assume - element
> > size, but maybe that's said somewhere in more general terms.)
> >
> > As a nit: The two vclmulh lines have one too many blanks, resulting
> > in columns to not be aligned.
> >
> > Jan
>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2023-07-24 21:12 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-01 5:20 [PATCH v6 00/15] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 01/15] RISC-V: Add support for the Zvbb ISA extension Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 02/15] RISC-V: Add support for the Zvbc extension Christoph Muellner
2023-07-17 7:02 ` Jan Beulich
2023-07-17 7:11 ` Philipp Tomsich
2023-07-17 7:26 ` Jan Beulich
2023-07-17 7:28 ` Philipp Tomsich
2023-07-17 7:20 ` Christoph Müllner
2023-07-24 21:12 ` [CAUTION - External Sender] " Ken Dockser
2023-07-01 5:20 ` [PATCH v6 03/15] RISC-V: Add support for the Zvkg ISA extension Christoph Muellner
2023-07-24 7:14 ` Jan Beulich
2023-07-01 5:20 ` [PATCH v6 04/15] RISC-V: Add support for the Zvkned " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions Christoph Muellner
2023-07-03 9:47 ` Nelson Chu
2023-07-03 10:10 ` Christoph Müllner
2023-07-01 5:20 ` [PATCH v6 06/15] RISC-V: Add support for the Zvksed ISA extension Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 07/15] RISC-V: Add support for the Zvksh " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 08/15] RISC-V: Add support for the Zvkn " Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 09/15] RISC-V: Allow nested implications for extensions Christoph Muellner
2023-07-01 5:20 ` [PATCH v6 10/15] RISC-V: Add support for the Zvkng ISA extension Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 11/15] RISC-V: Add support for the Zvks " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 12/15] RISC-V: Add support for the Zvksg " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 13/15] RISC-V: Add support for the Zvknc " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 14/15] RISC-V: Add support for the Zvksc " Christoph Muellner
2023-07-01 5:21 ` [PATCH v6 15/15] binutils: NEWS: Announce new RISC-V vector crypto extensions Christoph Muellner
2023-07-01 13:38 ` [PATCH v6 00/15] RISC-V: Add support for " Palmer Dabbelt
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