* [PATCH 1/4] x86-64: LAR and LSL don't need REX.W
2023-02-10 8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
@ 2023-02-10 8:48 ` Jan Beulich
2023-02-10 8:49 ` [PATCH 2/4] x86: have insns acting on segment selector values allow for consistent operands Jan Beulich
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2023-02-10 8:48 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
Just like we suppress emitting REX.W for e.g. MOV from/to segment
register, there's also no need for it for LAR and LSL - these can only
ever return 32-bit values and hence always zero-extend their results
anyway.
While there also drop the redundant Word from the first operand of
the second template each - this is already implied by Reg16.
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -260,34 +260,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov QWORD PTR (ds:)?0x0,rcx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
#pass
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -260,34 +260,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov %rcx,0x0
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
#pass
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -567,16 +567,16 @@ nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
-lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/4] x86: have insns acting on segment selector values allow for consistent operands
2023-02-10 8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
2023-02-10 8:48 ` [PATCH 1/4] x86-64: LAR and LSL don't need REX.W Jan Beulich
@ 2023-02-10 8:49 ` Jan Beulich
2023-02-10 8:50 ` [PATCH 3/4] x86-64: don't permit LAHF/SAHF with "generic64" Jan Beulich
2023-02-10 8:51 ` [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns Jan Beulich
3 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2023-02-10 8:49 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
While MOV to/from segment register as well as selector storing insns
already permit 32- and 64-bit GPR operands, selector loading insns and
ARPL do not. Split templates accordingly.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -694,7 +694,8 @@ i386_intel_operand (char *operand_string
if (got_a_float == 2) /* "fi..." */
suffix = SHORT_MNEM_SUFFIX;
else if (current_templates->start->mnem_off != MN_lar
- && current_templates->start->mnem_off != MN_lsl)
+ && current_templates->start->mnem_off != MN_lsl
+ && current_templates->start->mnem_off != MN_arpl)
suffix = WORD_MNEM_SUFFIX;
break;
--- a/gas/testsuite/gas/i386/i386.d
+++ b/gas/testsuite/gas/i386/i386.d
@@ -61,24 +61,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%eax\)
+[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
+[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
+[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
+[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
+[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
+[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
#pass
--- a/gas/testsuite/gas/i386/i386.s
+++ b/gas/testsuite/gas/i386/i386.s
@@ -68,25 +68,75 @@ movzx eax, word ptr [eax]
movnti dword ptr [eax], eax
.att_syntax
+ arpl %cx,%dx
+ arpl %ecx,%edx
+ arpl %cx,(%edx)
+ arpl %ecx,(%edx)
+
lar %dx,%dx
lar %dx,%edx
lar %edx,%edx
lar (%edx),%dx
lar (%edx),%edx
+
+ lldt %dx
+ lldt %edx
+ lldt (%edx)
+
lsl %dx,%dx
lsl %dx,%edx
lsl %edx,%edx
lsl (%edx),%dx
lsl (%edx),%edx
+ ltr %dx
+ ltr %edx
+ ltr (%edx)
+
+ verr %dx
+ verr %edx
+ verr (%edx)
+
+ verw %dx
+ verw %edx
+ verw (%edx)
+
.intel_syntax noprefix
+ arpl cx,dx
+ arpl ecx,edx
+ arpl [ecx],dx
+ arpl [ecx],edx
+ arpl word ptr [ecx],dx
+ arpl word ptr [ecx],edx
+
lar dx,dx
lar edx,dx
lar edx,edx
lar dx,WORD PTR [edx]
lar edx,WORD PTR [edx]
+
+ lldt dx
+ lldt edx
+ lldt [edx]
+ lldt word ptr [edx]
+
lsl dx,dx
lsl edx,dx
lsl edx,edx
lsl dx,WORD PTR [edx]
lsl edx,WORD PTR [edx]
+
+ ltr dx
+ ltr edx
+ ltr [edx]
+ ltr word ptr [edx]
+
+ verr dx
+ verr edx
+ verr [edx]
+ verr word ptr [edx]
+
+ verw dx
+ verw edx
+ verw [edx]
+ verw word ptr [edx]
--- a/gas/testsuite/gas/i386/i386-intel.d
+++ b/gas/testsuite/gas/i386/i386-intel.d
@@ -62,24 +62,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[eax\],eax
+[ ]*[a-f0-9]+: 63 ca arpl dx,cx
+[ ]*[a-f0-9]+: 63 ca arpl dx,cx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
+[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
#pass
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -266,6 +266,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
@@ -274,6 +278,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
@@ -282,6 +298,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
@@ -290,4 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
#pass
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -320,6 +320,12 @@ mov tr0, rcx
lar (%rdx),%dx
lar (%rdx),%edx
lar (%rdx),%rdx
+
+ lldt %dx
+ lldt %edx
+ lldt %rdx
+ lldt (%rdx)
+
lsl %dx,%dx
lsl %dx,%edx
lsl %dx,%rdx
@@ -329,6 +335,21 @@ mov tr0, rcx
lsl (%rdx),%edx
lsl (%rdx),%rdx
+ ltr %dx
+ ltr %edx
+ ltr %rdx
+ ltr (%rdx)
+
+ verr %dx
+ verr %edx
+ verr %rdx
+ verr (%rdx)
+
+ verw %dx
+ verw %edx
+ verw %rdx
+ verw (%rdx)
+
.intel_syntax noprefix
lar dx,dx
lar edx,dx
@@ -338,6 +359,13 @@ mov tr0, rcx
lar dx,WORD PTR [rdx]
lar edx,WORD PTR [rdx]
lar rdx,WORD PTR [rdx]
+
+ lldt dx
+ lldt edx
+ lldt rdx
+ lldt [rdx]
+ lldt word ptr [rdx]
+
lsl dx,dx
lsl edx,dx
lsl rdx,dx
@@ -346,3 +374,21 @@ mov tr0, rcx
lsl dx,WORD PTR [rdx]
lsl edx,WORD PTR [rdx]
lsl rdx,WORD PTR [rdx]
+
+ ltr dx
+ ltr edx
+ ltr rdx
+ ltr [rdx]
+ ltr word ptr [rdx]
+
+ verr dx
+ verr edx
+ verr rdx
+ verr [rdx]
+ verr word ptr [rdx]
+
+ verw dx
+ verw edx
+ verw rdx
+ verw [rdx]
+ verw word ptr [rdx]
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -266,6 +266,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
@@ -274,6 +278,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
@@ -282,6 +298,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
@@ -290,4 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
#pass
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -566,18 +566,21 @@ nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf
nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
-arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
+arpl, 0x63, i286|No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Reg16|Reg32 }
+arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex }
lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
@@ -590,8 +593,10 @@ smsw, 0xf01/4, i286, Modrm|IgnoreSize|No
str, 0xf00/1, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
str, 0xf00/1, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
// Floating point instructions.
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 3/4] x86-64: don't permit LAHF/SAHF with "generic64"
2023-02-10 8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
2023-02-10 8:48 ` [PATCH 1/4] x86-64: LAR and LSL don't need REX.W Jan Beulich
2023-02-10 8:49 ` [PATCH 2/4] x86: have insns acting on segment selector values allow for consistent operands Jan Beulich
@ 2023-02-10 8:50 ` Jan Beulich
2023-02-10 8:51 ` [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns Jan Beulich
3 siblings, 0 replies; 8+ messages in thread
From: Jan Beulich @ 2023-02-10 8:50 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
The feature isn't universally available on 64-bit CPUs.
Note that in i386-gen.c:isa_dependencies[] I'm only adding it to models
where I'm certain the functionality exists. For Nocona and Core I'm
uncertain in particular.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1047,6 +1047,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (lwp, LWP, ANY_LWP, false),
SUBARCH (movbe, MOVBE, MOVBE, false),
SUBARCH (cx16, CX16, CX16, false),
+ SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false),
SUBARCH (ept, EPT, ANY_EPT, false),
SUBARCH (lzcnt, LZCNT, LZCNT, false),
SUBARCH (popcnt, POPCNT, POPCNT, false),
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -151,6 +151,7 @@ accept various extension mnemonics. For
@code{sse4},
@code{avx},
@code{avx2},
+@code{lahf_sahf},
@code{adx},
@code{rdseed},
@code{prfchw},
@@ -1487,7 +1488,7 @@ supported on the CPU specified. The cho
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
@item @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
-@item @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
+@item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -934,6 +934,7 @@ if [gas_64_check] then {
run_dump_test "x86-64-arch-2-btver2"
run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
run_list_test "x86-64-arch-2-2" "-march=generic64+cx16 -I${srcdir}/$subdir -al"
+ run_list_test "x86-64-arch-2-3" "-march=generic64+lahf_sahf -I${srcdir}/$subdir -aln"
run_dump_test "xmmhi64"
run_dump_test "x86-64-xsave"
run_dump_test "x86-64-xsave-intel"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
@@ -1,5 +1,5 @@
#source: ../x86-64-arch-2.s
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+lahf_sahf+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
#objdump: -dw
#name: x86-64 (ILP32) arch 2
#dump: ../x86-64-arch-2.d
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+lahf_sahf+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
#objdump: -dw
#name: x86-64 arch 2
@@ -38,4 +38,5 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
+[ ]*[a-f0-9]+: 9f lahf
#pass
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -62,3 +62,5 @@ xstorerng
blsr %ecx,%ebx
# TBM
blcfill %ecx,%ebx
+# LAHF/SAHF
+lahf
--- a/gas/testsuite/gas/i386/x86-64-arch-2-1.l
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-1.l
@@ -24,6 +24,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -95,3 +96,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# LAHF/SAHF
+[ ]*66[ ]+lahf
--- a/gas/testsuite/gas/i386/x86-64-arch-2-2.l
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-2.l
@@ -23,6 +23,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -94,3 +95,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# LAHF/SAHF
+[ ]*66[ ]+lahf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-3.l
@@ -0,0 +1,93 @@
+.*: Assembler messages:
+.*:16: Error: .*
+.*:18: Error: .*
+.*:20: Error: .*
+.*:22: Error: .*
+.*:24: Error: .*
+.*:26: Error: .*
+.*:28: Error: .*
+.*:30: Error: .*
+.*:32: Error: .*
+.*:34: Error: .*
+.*:36: Error: .*
+.*:38: Error: .*
+.*:40: Error: .*
+.*:42: Error: .*
+.*:44: Error: .*
+.*:46: Error: .*
+.*:48: Error: .*
+.*:50: Error: .*
+.*:52: Error: .*
+.*:54: Error: .*
+.*:56: Error: .*
+.*:58: Error: .*
+.*:60: Error: .*
+.*:62: Error: .*
+.*:64: Error: .*
+[ ]*1[ ]+\.include "x86-64-arch-2\.s"
+[ ]*1[ ]+\# Test -march=
+[ ]*2[ ]+\.text
+[ ]*3[ ]+\# cmov feature *
+[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx
+[ ]*5[ ]+\# clflush
+[ ]*6[ ]+\?\?\?\? 0FAE38 clflush \(%rax\)
+[ ]*7[ ]+\# SYSCALL
+[ ]*8[ ]+\?\?\?\? 0F05 syscall
+[ ]*9[ ]+\# MMX
+[ ]*10[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3
+[ ]*11[ ]+\# SSE
+[ ]*12[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3
+[ ]*13[ ]+\# SSE2
+[ ]*14[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3
+[ ]*15[ ]+\# SSE3
+[ ]*16[ ]+addsubpd %xmm4,%xmm3
+[ ]*17[ ]+\# SSSE3
+[ ]*18[ ]+phaddw %xmm4,%xmm3
+[ ]*19[ ]+\# SSE4\.1
+[ ]*20[ ]+phminposuw %xmm1,%xmm3
+[ ]*21[ ]+\# SSE4\.2
+[ ]*22[ ]+crc32 %ecx,%ebx
+[ ]*23[ ]+\# AVX
+[ ]*24[ ]+vzeroall
+[ ]*25[ ]+\# VMX
+[ ]*26[ ]+vmxoff
+[ ]*27[ ]+\# SMX
+[ ]*28[ ]+getsec
+[ ]*29[ ]+\# Xsave
+[ ]*30[ ]+xgetbv
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%rcx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%rcx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%rcx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%rcx\),%ebx
+[ ]*45[ ]+\# CX16
+[ ]*46[ ]+cmpxchg16b \(%rsi\)
+[ ]*47[ ]+\# EPT
+[ ]*48[ ]+invept \(%rcx\),%rbx
+[ ]*49[ ]+\# RDTSCP
+[ ]*50[ ]+rdtscp
+[ ]*51[ ]+\# 3DNow or PRFCHW
+[ ]*52[ ]+prefetchw 0x1000\(,%rsi,2\)
+[ ]*53[ ]+\# SSE4a
+[ ]*54[ ]+insertq %xmm2,%xmm1
+[ ]*55[ ]+\# SVME
+[ ]*56[ ]+vmload
+[ ]*57[ ]+\# ABM/LZCNT
+[ ]*58[ ]+lzcnt %ecx,%ebx
+[ ]*59[ ]+\# PadLock
+[ ]*60[ ]+xstorerng
+[ ]*61[ ]+\# BMI
+[ ]*62[ ]+blsr %ecx,%ebx
+[ ]*63[ ]+\# TBM
+[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# LAHF/SAHF
+[ ]*66[ ]+\?\?\?\? 9F lahf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-3.s
@@ -0,0 +1 @@
+.include "x86-64-arch-2.s"
--- a/gas/testsuite/gas/i386/x86-64-arch-2-lzcnt.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-lzcnt.d
@@ -1,5 +1,5 @@
#source: x86-64-arch-2.s
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+lahf_sahf+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
#objdump: -dw
#name: x86-64 arch 2 (lzcnt)
#dump: x86-64-arch-2.d
--- a/gas/testsuite/gas/i386/x86-64-arch-2-prefetchw.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2-prefetchw.d
@@ -1,5 +1,5 @@
#source: x86-64-arch-2.s
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+cx16+lahf_sahf+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
#objdump: -dw
#name: x86-64 arch 2 (prefetchw)
#dump: x86-64-arch-2.d
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -67,7 +67,7 @@ static const dependency isa_dependencies
{ "CORE2",
"NOCONA|SSSE3" },
{ "COREI7",
- "CORE2|SSE4_2|Rdtscp" },
+ "CORE2|SSE4_2|Rdtscp|LAHF_SAHF" },
{ "K6",
"186|286|386|486|586|SYSCALL|387|MMX" },
{ "K6_2",
@@ -79,7 +79,7 @@ static const dependency isa_dependencies
{ "AMDFAM10",
"K8|FISTTP|SSE4A|ABM" },
{ "BDVER1",
- "GENERIC64|FISTTP|Rdtscp|CX16|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
+ "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
{ "BDVER2",
"BDVER1|FMA|BMI|TBM|F16C" },
{ "BDVER3",
@@ -87,7 +87,7 @@ static const dependency isa_dependencies
{ "BDVER4",
"BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
{ "ZNVER1",
- "GENERIC64|FISTTP|Rdtscp|CX16|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
+ "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
{ "ZNVER2",
"ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
{ "ZNVER3",
@@ -95,7 +95,7 @@ static const dependency isa_dependencies
{ "ZNVER4",
"ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
{ "BTVER1",
- "GENERIC64|FISTTP|CX16|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|CX16|Clflush|FISTTP|SVME" },
+ "GENERIC64|FISTTP|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
{ "BTVER2",
"BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
{ "286",
@@ -313,6 +313,7 @@ static bitfield cpu_flags[] =
BITFIELD (LM),
BITFIELD (Movbe),
BITFIELD (CX16),
+ BITFIELD (LAHF_SAHF),
BITFIELD (EPT),
BITFIELD (Rdtscp),
BITFIELD (FSGSBase),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -137,6 +137,8 @@ enum
CpuMovbe,
/* CMPXCHG16B instruction support required. */
CpuCX16,
+ /* LAHF/SAHF instruction support required (in 64-bit mode). */
+ CpuLAHF_SAHF,
/* EPT Instructions required */
CpuEPT,
/* RDTSCP Instruction support required */
@@ -372,6 +374,7 @@ typedef union i386_cpu_flags
unsigned int cputbm:1;
unsigned int cpumovbe:1;
unsigned int cpucx16:1;
+ unsigned int cpulahf_sahf:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
unsigned int cpufsgsbase:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -264,8 +264,10 @@ cld, 0xfc, 0, NoSuf, {}
cli, 0xfa, 0, NoSuf, {}
clts, 0xf06, i286, NoSuf, {}
cmc, 0xf5, 0, NoSuf, {}
-lahf, 0x9f, 0, NoSuf, {}
-sahf, 0x9e, 0, NoSuf, {}
+lahf, 0x9f, No64, NoSuf, {}
+lahf, 0x9f, LAHF_SAHF, NoSuf, {}
+sahf, 0x9e, No64, NoSuf, {}
+sahf, 0x9e, LAHF_SAHF, NoSuf, {}
pushf, 0x9c, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
pushf, 0x9c, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
popf, 0x9d, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
2023-02-10 8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
` (2 preceding siblings ...)
2023-02-10 8:50 ` [PATCH 3/4] x86-64: don't permit LAHF/SAHF with "generic64" Jan Beulich
@ 2023-02-10 8:51 ` Jan Beulich
2023-02-10 17:02 ` H.J. Lu
3 siblings, 1 reply; 8+ messages in thread
From: Jan Beulich @ 2023-02-10 8:51 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
These have their own CPUID bit and hence they should also have their own
separate control.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1027,6 +1027,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, false),
SUBARCH (avx512bw, AVX512BW, ANY_AVX512BW, false),
SUBARCH (avx512vl, AVX512VL, ANY_AVX512VL, false),
+ SUBARCH (monitor, MONITOR, MONITOR, false),
SUBARCH (vmx, VMX, ANY_VMX, false),
SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false),
SUBARCH (smx, SMX, SMX, false),
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -152,6 +152,7 @@ accept various extension mnemonics. For
@code{avx},
@code{avx2},
@code{lahf_sahf},
+@code{monitor},
@code{adx},
@code{rdseed},
@code{prfchw},
@@ -1487,7 +1488,7 @@ supported on the CPU specified. The cho
@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
-@item @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
+@item @samp{.monitor} @tab @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
@item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+mmx+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
+#as: -march=i686+mmx+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+monitor+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
#objdump: -dw
#name: i386 arch 10
@@ -38,4 +38,5 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
+[ ]*[a-f0-9]+: 0f 01 c8 monitor( .*)
#pass
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -62,3 +62,5 @@ nopl (%eax)
blsr %ecx,%ebx
# TBM
blcfill %ecx,%ebx
+# MONITOR
+monitor
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -30,6 +30,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -101,3 +102,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# MONITOR
+[ ]*66[ ]+monitor
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -29,6 +29,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -100,3 +101,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# MONITOR
+[ ]*66[ ]+monitor
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -22,6 +22,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -96,3 +97,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# MONITOR
+[ ]*66[ ]+monitor
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -20,6 +20,7 @@
.*:60: Error: .*
.*:62: Error: .*
.*:64: Error: .*
+.*:66: Error: .*
GAS LISTING .*
@@ -94,3 +95,5 @@ GAS LISTING .*
[ ]*62[ ]+blsr %ecx,%ebx
[ ]*63[ ]+\# TBM
[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# MONITOR
+[ ]*66[ ]+monitor
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-10-6.l
@@ -0,0 +1,99 @@
+.*: Assembler messages:
+.*:4: Error: .*
+.*:6: Error: .*
+.*:8: Error: .*
+.*:10: Error: .*
+.*:12: Error: .*
+.*:14: Error: .*
+.*:16: Error: .*
+.*:18: Error: .*
+.*:20: Error: .*
+.*:22: Error: .*
+.*:24: Error: .*
+.*:26: Error: .*
+.*:28: Error: .*
+.*:30: Error: .*
+.*:32: Error: .*
+.*:34: Error: .*
+.*:36: Error: .*
+.*:38: Error: .*
+.*:40: Error: .*
+.*:42: Error: .*
+.*:44: Error: .*
+.*:46: Error: .*
+.*:48: Error: .*
+.*:50: Error: .*
+.*:52: Error: .*
+.*:54: Error: .*
+.*:56: Error: .*
+.*:58: Error: .*
+.*:60: Error: .*
+.*:62: Error: .*
+.*:64: Error: .*
+[ ]*1[ ]+\.include "arch-10\.s"
+[ ]*1[ ]+\# Test -march=
+[ ]*2[ ]+\.text
+[ ]*3[ ]+\# cmov feature *
+[ ]*4[ ]+cmove %eax,%ebx
+[ ]*5[ ]+\# clflush
+[ ]*6[ ]+clflush \(%eax\)
+[ ]*7[ ]+\# SYSCALL
+[ ]*8[ ]+syscall
+[ ]*9[ ]+\# MMX
+[ ]*10[ ]+paddb %mm4,%mm3
+[ ]*11[ ]+\# SSE
+[ ]*12[ ]+addss %xmm4,%xmm3
+[ ]*13[ ]+\# SSE2
+[ ]*14[ ]+addsd %xmm4,%xmm3
+[ ]*15[ ]+\# SSE3
+[ ]*16[ ]+addsubpd %xmm4,%xmm3
+[ ]*17[ ]+\# SSSE3
+[ ]*18[ ]+phaddw %xmm4,%xmm3
+[ ]*19[ ]+\# SSE4\.1
+[ ]*20[ ]+phminposuw %xmm1,%xmm3
+[ ]*21[ ]+\# SSE4\.2
+[ ]*22[ ]+crc32 %ecx,%ebx
+[ ]*23[ ]+\# AVX
+[ ]*24[ ]+vzeroall
+[ ]*25[ ]+\# VMX
+[ ]*26[ ]+vmxoff
+[ ]*27[ ]+\# SMX
+[ ]*28[ ]+getsec
+[ ]*29[ ]+\# Xsave
+[ ]*30[ ]+xgetbv
+[ ]*31[ ]+\# Xsaveopt
+[ ]*32[ ]+xsaveopt \(%ecx\)
+[ ]*33[ ]+\# AES
+[ ]*34[ ]+aesenc \(%ecx\),%xmm0
+[ ]*35[ ]+\# PCLMUL
+[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
+[ ]*37[ ]+\# AES \+ AVX
+[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
+[ ]*39[ ]+\# PCLMUL \+ AVX
+[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
+[ ]*41[ ]+\# FMA
+[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
+[ ]*43[ ]+\# MOVBE
+[ ]*44[ ]+movbe \(%ecx\),%ebx
+[ ]*45[ ]+\# EPT
+[ ]*46[ ]+invept \(%ecx\),%ebx
+[ ]*47[ ]+\# RDTSCP
+[ ]*48[ ]+rdtscp
+[ ]*49[ ]+\# 3DNow or PRFCHW
+[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
+[ ]*51[ ]+\# SSE4a
+[ ]*52[ ]+insertq %xmm2,%xmm1
+[ ]*53[ ]+\# SVME
+[ ]*54[ ]+vmload
+[ ]*55[ ]+\# ABM/LZCNT
+[ ]*56[ ]+lzcnt %ecx,%ebx
+[ ]*57[ ]+\# PadLock
+[ ]*58[ ]+xstorerng
+[ ]*59[ ]+\# nop
+[ ]*60[ ]+nopl \(%eax\)
+[ ]*61[ ]+\# BMI
+[ ]*62[ ]+blsr %ecx,%ebx
+[ ]*63[ ]+\# TBM
+[ ]*64[ ]+blcfill %ecx,%ebx
+[ ]*65[ ]+\# MONITOR
+[ ]*66[ ]+\?\?\?\? 0F01C8 monitor
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-10-6.s
@@ -0,0 +1 @@
+.include "arch-10.s"
--- a/gas/testsuite/gas/i386/arch-10-lzcnt.d
+++ b/gas/testsuite/gas/i386/arch-10-lzcnt.d
@@ -1,5 +1,5 @@
#source: arch-10.s
-#as: -march=i686+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
+#as: -march=i686+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+monitor+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
#objdump: -dw
#name: i386 arch 10 (lzcnt)
#dump: arch-10.d
--- a/gas/testsuite/gas/i386/arch-10-prefetchw.d
+++ b/gas/testsuite/gas/i386/arch-10-prefetchw.d
@@ -1,5 +1,5 @@
#source: arch-10.s
-#as: -march=i686+mmx+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
+#as: -march=i686+mmx+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+monitor+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
#objdump: -dw
#name: i386 arch 10 (prefetchw)
#dump: arch-10.d
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -206,6 +206,7 @@ if [gas_32_check] then {
run_list_test "arch-10-3" "-march=i686+mmx+sse4.2 -I${srcdir}/$subdir -al"
run_list_test "arch-10-4" "-march=i686+mmx+sse4+vmx+smx -I${srcdir}/$subdir -al"
run_list_test "arch-10-5" "-march=generic32+i686 -al"
+ run_list_test "arch-10-6" "-march=generic32+monitor -I${srcdir}/$subdir -aln"
run_dump_test "arch-11"
run_dump_test "arch-12"
run_dump_test "arch-13"
--- a/gas/testsuite/gas/i386/nosse-3.l
+++ b/gas/testsuite/gas/i386/nosse-3.l
@@ -5,3 +5,4 @@ GAS LISTING .*
[ ]*1[ ]+\# Test -march=\+nosse
[ ]*2[ ]+\.text
[ ]*3[ ]+lfence
+[ ]*4[ ]+\?\?\?\? 0F01C8 monitor
--- a/gas/testsuite/gas/i386/nosse-3.s
+++ b/gas/testsuite/gas/i386/nosse-3.s
@@ -1,3 +1,4 @@
# Test -march=+nosse
.text
lfence
+ monitor
--- a/gas/testsuite/gas/i386/nosse-4.l
+++ b/gas/testsuite/gas/i386/nosse-4.l
@@ -2,6 +2,7 @@
.*:6: Error: .*generic.*
.*:9: Error: .*\.sse.*
.*:12: Error: .*\.sse2.*
+.*:14: Error: .*\.sse3.*
.*:15: Error: .*\.sse3.*
.*:18: Error: .*\.ssse3.*
.*:21: Error: .*\.sse4\.1.*
@@ -9,10 +10,9 @@
.*:32: Error: .*\.nosse4\.2.*
.*:35: Error: .*\.nosse4\.1.*
.*:38: Error: .*\.nossse3.*
-.*:43: Error: .*\.nosse3.*
-.*:45: Error: .*\.nommx.*
-.*:47: Error: .*\.nosse2.*
-.*:50: Error: .*\.nosse.*
+.*:43: Error: .*\.nommx.*
+.*:45: Error: .*\.nosse2.*
+.*:48: Error: .*\.nosse.*
GAS LISTING .*
#...
[ ]*1[ ]+\# Test \.arch \[\.sseX|\.nosseX\]
@@ -28,7 +28,7 @@ GAS LISTING .*
[ ]*11[ ]+\?\?\?\? 0FAEE8 lfence
[ ]*12[ ]+mwait
[ ]*13[ ]+\.arch \.sse3
-[ ]*14[ ]+\?\?\?\? 0F01C9 mwait
+[ ]*14[ ]+mwait
[ ]*15[ ]+pabsd %xmm0, %xmm0
[ ]*16[ ]+\.arch \.ssse3
[ ]*17[ ]+\?\?\?\? 660F381E pabsd %xmm0, %xmm0
@@ -60,21 +60,15 @@ GAS LISTING .*
[ ]*36[ ]+C0
[ ]*37[ ]+\.arch \.nossse3
[ ]*38[ ]+pabsd %xmm0, %xmm0
-[ ]*39[ ]+\?\?\?\? 0F01C9 mwait
-[ ]*40[ ]+\?\?\?\? 0F77 emms
-[ ]*41[ ]+\.arch \.nommx
-[ ]*42[ ]+\.arch \.nosse3
-[ ]*43[ ]+mwait
-[ ]*44[ ]+\?\?\?\? 0FAEE8 lfence
-[ ]*45[ ]+emms
-[ ]*46[ ]+\.arch \.nosse2
-[ ]*47[ ]+lfence
-[ ]*48[ ]+\?\?\?\? 0F58C0 addps %xmm0, %xmm0
-[ ]*49[ ]+\.arch \.nosse
-[ ]*50[ ]+addps %xmm0, %xmm0
-\fGAS LISTING .*
-
-
-[ ]*51[ ]+\?\?\?\? 8DB42600 \.p2align 4
-[ ]*51[ ]+000000
+[ ]*39[ ]+\?\?\?\? 0F77 emms
+[ ]*40[ ]+\.arch \.nommx
+[ ]*41[ ]+\.arch \.nosse3
+[ ]*42[ ]+\?\?\?\? 0FAEE8 lfence
+[ ]*43[ ]+emms
+[ ]*44[ ]+\.arch \.nosse2
+[ ]*45[ ]+lfence
+[ ]*46[ ]+\?\?\?\? 0F58C0 addps %xmm0, %xmm0
+[ ]*47[ ]+\.arch \.nosse
+[ ]*48[ ]+addps %xmm0, %xmm0
+[ ]*49[ ]+\?\?\?\? .* \.p2align 4
#pass
--- a/gas/testsuite/gas/i386/nosse-4.s
+++ b/gas/testsuite/gas/i386/nosse-4.s
@@ -36,11 +36,9 @@
pabsd %xmm0, %xmm0
.arch .nossse3
pabsd %xmm0, %xmm0
- mwait
emms
.arch .nommx
.arch .nosse3
- mwait
lfence
emms
.arch .nosse2
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -61,9 +61,9 @@ static const dependency isa_dependencies
{ "P4",
"P3|Clflush|SSE2" },
{ "NOCONA",
- "GENERIC64|FISTTP|SSE3|CX16" },
+ "GENERIC64|FISTTP|SSE3|MONITOR|CX16" },
{ "CORE",
- "P4|FISTTP|SSE3|CX16" },
+ "P4|FISTTP|SSE3|MONITOR|CX16" },
{ "CORE2",
"NOCONA|SSSE3" },
{ "COREI7",
@@ -77,9 +77,9 @@ static const dependency isa_dependencies
{ "K8",
"ATHLON|Rdtscp|SSE2|LM" },
{ "AMDFAM10",
- "K8|FISTTP|SSE4A|ABM" },
+ "K8|FISTTP|SSE4A|ABM|MONITOR" },
{ "BDVER1",
- "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
{ "BDVER2",
"BDVER1|FMA|BMI|TBM|F16C" },
{ "BDVER3",
@@ -87,7 +87,7 @@ static const dependency isa_dependencies
{ "BDVER4",
"BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
{ "ZNVER1",
- "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
+ "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
{ "ZNVER2",
"ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
{ "ZNVER3",
@@ -95,7 +95,7 @@ static const dependency isa_dependencies
{ "ZNVER4",
"ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
{ "BTVER1",
- "GENERIC64|FISTTP|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
+ "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
{ "BTVER2",
"BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
{ "286",
@@ -322,6 +322,7 @@ static bitfield cpu_flags[] =
BITFIELD (BMI2),
BITFIELD (LZCNT),
BITFIELD (POPCNT),
+ BITFIELD (MONITOR),
BITFIELD (HLE),
BITFIELD (RTM),
BITFIELD (INVPCID),
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -88,6 +88,8 @@ enum
CpuLZCNT,
/* POPCNT support required */
CpuPOPCNT,
+ /* MONITOR support required */
+ CpuMONITOR,
/* SSE4.1 support required */
CpuSSE4_1,
/* SSE4.2 support required */
@@ -350,6 +352,7 @@ typedef union i386_cpu_flags
unsigned int cpusse4a:1;
unsigned int cpulzcnt:1;
unsigned int cpupopcnt:1;
+ unsigned int cpumonitor:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1270,17 +1270,17 @@ cmpxchg16b, 0xfc7/1, CX16|x64, Modrm|NoS
// MONITOR instructions.
-monitor, 0xf01c8, SSE3, NoSuf, {}
+monitor, 0xf01c8, MONITOR, NoSuf, {}
// monitor is very special. CX and DX are always 32 bits. The
// address size override prefix can be used to overrride the AX size in
// all modes.
-monitor, 0xf01c8, SSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
+monitor, 0xf01c8, MONITOR, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
// The 64-bit form exists only for compatibility with older gas.
-monitor, 0xf01c8, SSE3|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
-mwait, 0xf01c9, SSE3, NoSuf, {}
+monitor, 0xf01c8, MONITOR|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
+mwait, 0xf01c9, MONITOR, NoSuf, {}
// mwait is very special. AX and CX are always 32 bits.
// The 64-bit form exists only for compatibility with older gas.
-mwait, 0xf01c9, SSE3, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword }
+mwait, 0xf01c9, MONITOR, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword }
// VMX instructions.
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
2023-02-10 8:51 ` [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns Jan Beulich
@ 2023-02-10 17:02 ` H.J. Lu
2023-02-13 8:08 ` Jan Beulich
0 siblings, 1 reply; 8+ messages in thread
From: H.J. Lu @ 2023-02-10 17:02 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Fri, Feb 10, 2023 at 12:51 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> These have their own CPUID bit and hence they should also have their own
> separate control.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1027,6 +1027,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, false),
> SUBARCH (avx512bw, AVX512BW, ANY_AVX512BW, false),
> SUBARCH (avx512vl, AVX512VL, ANY_AVX512VL, false),
> + SUBARCH (monitor, MONITOR, MONITOR, false),
> SUBARCH (vmx, VMX, ANY_VMX, false),
> SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false),
> SUBARCH (smx, SMX, SMX, false),
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -152,6 +152,7 @@ accept various extension mnemonics. For
> @code{avx},
> @code{avx2},
> @code{lahf_sahf},
> +@code{monitor},
> @code{adx},
> @code{rdseed},
> @code{prfchw},
> @@ -1487,7 +1488,7 @@ supported on the CPU specified. The cho
> @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
> @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
> @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
> -@item @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
> +@item @samp{.monitor} @tab @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
> @item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
> @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
> @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
> --- a/gas/testsuite/gas/i386/arch-10.d
> +++ b/gas/testsuite/gas/i386/arch-10.d
> @@ -1,4 +1,4 @@
> -#as: -march=i686+mmx+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
> +#as: -march=i686+mmx+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+monitor+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
> #objdump: -dw
> #name: i386 arch 10
>
> @@ -38,4 +38,5 @@ Disassembly of section .text:
> [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
> [ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
> [ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
> +[ ]*[a-f0-9]+: 0f 01 c8 monitor( .*)
> #pass
> --- a/gas/testsuite/gas/i386/arch-10.s
> +++ b/gas/testsuite/gas/i386/arch-10.s
> @@ -62,3 +62,5 @@ nopl (%eax)
> blsr %ecx,%ebx
> # TBM
> blcfill %ecx,%ebx
> +# MONITOR
> +monitor
> --- a/gas/testsuite/gas/i386/arch-10-1.l
> +++ b/gas/testsuite/gas/i386/arch-10-1.l
> @@ -30,6 +30,7 @@
> .*:60: Error: .*
> .*:62: Error: .*
> .*:64: Error: .*
> +.*:66: Error: .*
> GAS LISTING .*
>
>
> @@ -101,3 +102,5 @@ GAS LISTING .*
> [ ]*62[ ]+blsr %ecx,%ebx
> [ ]*63[ ]+\# TBM
> [ ]*64[ ]+blcfill %ecx,%ebx
> +[ ]*65[ ]+\# MONITOR
> +[ ]*66[ ]+monitor
> --- a/gas/testsuite/gas/i386/arch-10-2.l
> +++ b/gas/testsuite/gas/i386/arch-10-2.l
> @@ -29,6 +29,7 @@
> .*:60: Error: .*
> .*:62: Error: .*
> .*:64: Error: .*
> +.*:66: Error: .*
> GAS LISTING .*
>
>
> @@ -100,3 +101,5 @@ GAS LISTING .*
> [ ]*62[ ]+blsr %ecx,%ebx
> [ ]*63[ ]+\# TBM
> [ ]*64[ ]+blcfill %ecx,%ebx
> +[ ]*65[ ]+\# MONITOR
> +[ ]*66[ ]+monitor
> --- a/gas/testsuite/gas/i386/arch-10-3.l
> +++ b/gas/testsuite/gas/i386/arch-10-3.l
> @@ -22,6 +22,7 @@
> .*:60: Error: .*
> .*:62: Error: .*
> .*:64: Error: .*
> +.*:66: Error: .*
> GAS LISTING .*
>
>
> @@ -96,3 +97,5 @@ GAS LISTING .*
> [ ]*62[ ]+blsr %ecx,%ebx
> [ ]*63[ ]+\# TBM
> [ ]*64[ ]+blcfill %ecx,%ebx
> +[ ]*65[ ]+\# MONITOR
> +[ ]*66[ ]+monitor
> --- a/gas/testsuite/gas/i386/arch-10-4.l
> +++ b/gas/testsuite/gas/i386/arch-10-4.l
> @@ -20,6 +20,7 @@
> .*:60: Error: .*
> .*:62: Error: .*
> .*:64: Error: .*
> +.*:66: Error: .*
> GAS LISTING .*
>
>
> @@ -94,3 +95,5 @@ GAS LISTING .*
> [ ]*62[ ]+blsr %ecx,%ebx
> [ ]*63[ ]+\# TBM
> [ ]*64[ ]+blcfill %ecx,%ebx
> +[ ]*65[ ]+\# MONITOR
> +[ ]*66[ ]+monitor
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-10-6.l
> @@ -0,0 +1,99 @@
> +.*: Assembler messages:
> +.*:4: Error: .*
> +.*:6: Error: .*
> +.*:8: Error: .*
> +.*:10: Error: .*
> +.*:12: Error: .*
> +.*:14: Error: .*
> +.*:16: Error: .*
> +.*:18: Error: .*
> +.*:20: Error: .*
> +.*:22: Error: .*
> +.*:24: Error: .*
> +.*:26: Error: .*
> +.*:28: Error: .*
> +.*:30: Error: .*
> +.*:32: Error: .*
> +.*:34: Error: .*
> +.*:36: Error: .*
> +.*:38: Error: .*
> +.*:40: Error: .*
> +.*:42: Error: .*
> +.*:44: Error: .*
> +.*:46: Error: .*
> +.*:48: Error: .*
> +.*:50: Error: .*
> +.*:52: Error: .*
> +.*:54: Error: .*
> +.*:56: Error: .*
> +.*:58: Error: .*
> +.*:60: Error: .*
> +.*:62: Error: .*
> +.*:64: Error: .*
> +[ ]*1[ ]+\.include "arch-10\.s"
> +[ ]*1[ ]+\# Test -march=
> +[ ]*2[ ]+\.text
> +[ ]*3[ ]+\# cmov feature *
> +[ ]*4[ ]+cmove %eax,%ebx
> +[ ]*5[ ]+\# clflush
> +[ ]*6[ ]+clflush \(%eax\)
> +[ ]*7[ ]+\# SYSCALL
> +[ ]*8[ ]+syscall
> +[ ]*9[ ]+\# MMX
> +[ ]*10[ ]+paddb %mm4,%mm3
> +[ ]*11[ ]+\# SSE
> +[ ]*12[ ]+addss %xmm4,%xmm3
> +[ ]*13[ ]+\# SSE2
> +[ ]*14[ ]+addsd %xmm4,%xmm3
> +[ ]*15[ ]+\# SSE3
> +[ ]*16[ ]+addsubpd %xmm4,%xmm3
> +[ ]*17[ ]+\# SSSE3
> +[ ]*18[ ]+phaddw %xmm4,%xmm3
> +[ ]*19[ ]+\# SSE4\.1
> +[ ]*20[ ]+phminposuw %xmm1,%xmm3
> +[ ]*21[ ]+\# SSE4\.2
> +[ ]*22[ ]+crc32 %ecx,%ebx
> +[ ]*23[ ]+\# AVX
> +[ ]*24[ ]+vzeroall
> +[ ]*25[ ]+\# VMX
> +[ ]*26[ ]+vmxoff
> +[ ]*27[ ]+\# SMX
> +[ ]*28[ ]+getsec
> +[ ]*29[ ]+\# Xsave
> +[ ]*30[ ]+xgetbv
> +[ ]*31[ ]+\# Xsaveopt
> +[ ]*32[ ]+xsaveopt \(%ecx\)
> +[ ]*33[ ]+\# AES
> +[ ]*34[ ]+aesenc \(%ecx\),%xmm0
> +[ ]*35[ ]+\# PCLMUL
> +[ ]*36[ ]+pclmulqdq \$8,%xmm1,%xmm0
> +[ ]*37[ ]+\# AES \+ AVX
> +[ ]*38[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
> +[ ]*39[ ]+\# PCLMUL \+ AVX
> +[ ]*40[ ]+vpclmulqdq \$8,%xmm4,%xmm6,%xmm2
> +[ ]*41[ ]+\# FMA
> +[ ]*42[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
> +[ ]*43[ ]+\# MOVBE
> +[ ]*44[ ]+movbe \(%ecx\),%ebx
> +[ ]*45[ ]+\# EPT
> +[ ]*46[ ]+invept \(%ecx\),%ebx
> +[ ]*47[ ]+\# RDTSCP
> +[ ]*48[ ]+rdtscp
> +[ ]*49[ ]+\# 3DNow or PRFCHW
> +[ ]*50[ ]+prefetchw 0x1000\(,%esi,2\)
> +[ ]*51[ ]+\# SSE4a
> +[ ]*52[ ]+insertq %xmm2,%xmm1
> +[ ]*53[ ]+\# SVME
> +[ ]*54[ ]+vmload
> +[ ]*55[ ]+\# ABM/LZCNT
> +[ ]*56[ ]+lzcnt %ecx,%ebx
> +[ ]*57[ ]+\# PadLock
> +[ ]*58[ ]+xstorerng
> +[ ]*59[ ]+\# nop
> +[ ]*60[ ]+nopl \(%eax\)
> +[ ]*61[ ]+\# BMI
> +[ ]*62[ ]+blsr %ecx,%ebx
> +[ ]*63[ ]+\# TBM
> +[ ]*64[ ]+blcfill %ecx,%ebx
> +[ ]*65[ ]+\# MONITOR
> +[ ]*66[ ]+\?\?\?\? 0F01C8 monitor
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-10-6.s
> @@ -0,0 +1 @@
> +.include "arch-10.s"
> --- a/gas/testsuite/gas/i386/arch-10-lzcnt.d
> +++ b/gas/testsuite/gas/i386/arch-10-lzcnt.d
> @@ -1,5 +1,5 @@
> #source: arch-10.s
> -#as: -march=i686+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
> +#as: -march=i686+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+monitor+rdtscp+3dnowa+sse4a+svme+lzcnt+padlock+bmi+tbm
> #objdump: -dw
> #name: i386 arch 10 (lzcnt)
> #dump: arch-10.d
> --- a/gas/testsuite/gas/i386/arch-10-prefetchw.d
> +++ b/gas/testsuite/gas/i386/arch-10-prefetchw.d
> @@ -1,5 +1,5 @@
> #source: arch-10.s
> -#as: -march=i686+mmx+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
> +#as: -march=i686+mmx+nop+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+monitor+rdtscp+sse4a+svme+lzcnt+padlock+bmi+tbm+prfchw
> #objdump: -dw
> #name: i386 arch 10 (prefetchw)
> #dump: arch-10.d
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -206,6 +206,7 @@ if [gas_32_check] then {
> run_list_test "arch-10-3" "-march=i686+mmx+sse4.2 -I${srcdir}/$subdir -al"
> run_list_test "arch-10-4" "-march=i686+mmx+sse4+vmx+smx -I${srcdir}/$subdir -al"
> run_list_test "arch-10-5" "-march=generic32+i686 -al"
> + run_list_test "arch-10-6" "-march=generic32+monitor -I${srcdir}/$subdir -aln"
> run_dump_test "arch-11"
> run_dump_test "arch-12"
> run_dump_test "arch-13"
> --- a/gas/testsuite/gas/i386/nosse-3.l
> +++ b/gas/testsuite/gas/i386/nosse-3.l
> @@ -5,3 +5,4 @@ GAS LISTING .*
> [ ]*1[ ]+\# Test -march=\+nosse
> [ ]*2[ ]+\.text
> [ ]*3[ ]+lfence
> +[ ]*4[ ]+\?\?\?\? 0F01C8 monitor
> --- a/gas/testsuite/gas/i386/nosse-3.s
> +++ b/gas/testsuite/gas/i386/nosse-3.s
> @@ -1,3 +1,4 @@
> # Test -march=+nosse
> .text
> lfence
> + monitor
> --- a/gas/testsuite/gas/i386/nosse-4.l
> +++ b/gas/testsuite/gas/i386/nosse-4.l
> @@ -2,6 +2,7 @@
> .*:6: Error: .*generic.*
> .*:9: Error: .*\.sse.*
> .*:12: Error: .*\.sse2.*
> +.*:14: Error: .*\.sse3.*
> .*:15: Error: .*\.sse3.*
> .*:18: Error: .*\.ssse3.*
> .*:21: Error: .*\.sse4\.1.*
> @@ -9,10 +10,9 @@
> .*:32: Error: .*\.nosse4\.2.*
> .*:35: Error: .*\.nosse4\.1.*
> .*:38: Error: .*\.nossse3.*
> -.*:43: Error: .*\.nosse3.*
> -.*:45: Error: .*\.nommx.*
> -.*:47: Error: .*\.nosse2.*
> -.*:50: Error: .*\.nosse.*
> +.*:43: Error: .*\.nommx.*
> +.*:45: Error: .*\.nosse2.*
> +.*:48: Error: .*\.nosse.*
> GAS LISTING .*
> #...
> [ ]*1[ ]+\# Test \.arch \[\.sseX|\.nosseX\]
> @@ -28,7 +28,7 @@ GAS LISTING .*
> [ ]*11[ ]+\?\?\?\? 0FAEE8 lfence
> [ ]*12[ ]+mwait
> [ ]*13[ ]+\.arch \.sse3
> -[ ]*14[ ]+\?\?\?\? 0F01C9 mwait
> +[ ]*14[ ]+mwait
> [ ]*15[ ]+pabsd %xmm0, %xmm0
> [ ]*16[ ]+\.arch \.ssse3
> [ ]*17[ ]+\?\?\?\? 660F381E pabsd %xmm0, %xmm0
> @@ -60,21 +60,15 @@ GAS LISTING .*
> [ ]*36[ ]+C0
> [ ]*37[ ]+\.arch \.nossse3
> [ ]*38[ ]+pabsd %xmm0, %xmm0
> -[ ]*39[ ]+\?\?\?\? 0F01C9 mwait
> -[ ]*40[ ]+\?\?\?\? 0F77 emms
> -[ ]*41[ ]+\.arch \.nommx
> -[ ]*42[ ]+\.arch \.nosse3
> -[ ]*43[ ]+mwait
> -[ ]*44[ ]+\?\?\?\? 0FAEE8 lfence
> -[ ]*45[ ]+emms
> -[ ]*46[ ]+\.arch \.nosse2
> -[ ]*47[ ]+lfence
> -[ ]*48[ ]+\?\?\?\? 0F58C0 addps %xmm0, %xmm0
> -[ ]*49[ ]+\.arch \.nosse
> -[ ]*50[ ]+addps %xmm0, %xmm0
> - GAS LISTING .*
> -
> -
> -[ ]*51[ ]+\?\?\?\? 8DB42600 \.p2align 4
> -[ ]*51[ ]+000000
> +[ ]*39[ ]+\?\?\?\? 0F77 emms
> +[ ]*40[ ]+\.arch \.nommx
> +[ ]*41[ ]+\.arch \.nosse3
> +[ ]*42[ ]+\?\?\?\? 0FAEE8 lfence
> +[ ]*43[ ]+emms
> +[ ]*44[ ]+\.arch \.nosse2
> +[ ]*45[ ]+lfence
> +[ ]*46[ ]+\?\?\?\? 0F58C0 addps %xmm0, %xmm0
> +[ ]*47[ ]+\.arch \.nosse
> +[ ]*48[ ]+addps %xmm0, %xmm0
> +[ ]*49[ ]+\?\?\?\? .* \.p2align 4
> #pass
> --- a/gas/testsuite/gas/i386/nosse-4.s
> +++ b/gas/testsuite/gas/i386/nosse-4.s
> @@ -36,11 +36,9 @@
> pabsd %xmm0, %xmm0
> .arch .nossse3
> pabsd %xmm0, %xmm0
> - mwait
> emms
> .arch .nommx
> .arch .nosse3
> - mwait
> lfence
> emms
> .arch .nosse2
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -61,9 +61,9 @@ static const dependency isa_dependencies
> { "P4",
> "P3|Clflush|SSE2" },
> { "NOCONA",
> - "GENERIC64|FISTTP|SSE3|CX16" },
> + "GENERIC64|FISTTP|SSE3|MONITOR|CX16" },
> { "CORE",
> - "P4|FISTTP|SSE3|CX16" },
> + "P4|FISTTP|SSE3|MONITOR|CX16" },
> { "CORE2",
> "NOCONA|SSSE3" },
> { "COREI7",
> @@ -77,9 +77,9 @@ static const dependency isa_dependencies
> { "K8",
> "ATHLON|Rdtscp|SSE2|LM" },
> { "AMDFAM10",
> - "K8|FISTTP|SSE4A|ABM" },
> + "K8|FISTTP|SSE4A|ABM|MONITOR" },
> { "BDVER1",
> - "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
> + "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMUL|PRFCHW" },
> { "BDVER2",
> "BDVER1|FMA|BMI|TBM|F16C" },
> { "BDVER3",
> @@ -87,7 +87,7 @@ static const dependency isa_dependencies
> { "BDVER4",
> "BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
> { "ZNVER1",
> - "GENERIC64|FISTTP|Rdtscp|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
> + "GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
> { "ZNVER2",
> "ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
> { "ZNVER3",
> @@ -95,7 +95,7 @@ static const dependency isa_dependencies
> { "ZNVER4",
> "ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
> { "BTVER1",
> - "GENERIC64|FISTTP|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
> + "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
> { "BTVER2",
> "BTVER1|AVX|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
> { "286",
> @@ -322,6 +322,7 @@ static bitfield cpu_flags[] =
> BITFIELD (BMI2),
> BITFIELD (LZCNT),
> BITFIELD (POPCNT),
> + BITFIELD (MONITOR),
> BITFIELD (HLE),
> BITFIELD (RTM),
> BITFIELD (INVPCID),
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -88,6 +88,8 @@ enum
> CpuLZCNT,
> /* POPCNT support required */
> CpuPOPCNT,
> + /* MONITOR support required */
> + CpuMONITOR,
> /* SSE4.1 support required */
> CpuSSE4_1,
> /* SSE4.2 support required */
> @@ -350,6 +352,7 @@ typedef union i386_cpu_flags
> unsigned int cpusse4a:1;
> unsigned int cpulzcnt:1;
> unsigned int cpupopcnt:1;
> + unsigned int cpumonitor:1;
> unsigned int cpusse4_1:1;
> unsigned int cpusse4_2:1;
> unsigned int cpuavx:1;
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -1270,17 +1270,17 @@ cmpxchg16b, 0xfc7/1, CX16|x64, Modrm|NoS
>
> // MONITOR instructions.
>
> -monitor, 0xf01c8, SSE3, NoSuf, {}
> +monitor, 0xf01c8, MONITOR, NoSuf, {}
> // monitor is very special. CX and DX are always 32 bits. The
> // address size override prefix can be used to overrride the AX size in
> // all modes.
> -monitor, 0xf01c8, SSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
> +monitor, 0xf01c8, MONITOR, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
> // The 64-bit form exists only for compatibility with older gas.
> -monitor, 0xf01c8, SSE3|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
> -mwait, 0xf01c9, SSE3, NoSuf, {}
> +monitor, 0xf01c8, MONITOR|x64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
> +mwait, 0xf01c9, MONITOR, NoSuf, {}
> // mwait is very special. AX and CX are always 32 bits.
> // The 64-bit form exists only for compatibility with older gas.
> -mwait, 0xf01c9, SSE3, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword }
> +mwait, 0xf01c9, MONITOR, CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword }
>
> // VMX instructions.
>
>
Since they used to be in SSE3, should they be also allowed with SSE3?
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
2023-02-10 17:02 ` H.J. Lu
@ 2023-02-13 8:08 ` Jan Beulich
2023-02-13 17:40 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Jan Beulich @ 2023-02-13 8:08 UTC (permalink / raw)
To: H.J. Lu; +Cc: Binutils
On 10.02.2023 18:02, H.J. Lu wrote:
> Since they used to be in SSE3, should they be also allowed with SSE3?
In order to answer the question, can you please clarify what you mean
by "used to be in SSE3"? I'm not aware of a spec ever marking them as
SSE3 insns. And not allowing their use in e.g. generic32+sse3 is one
of the purposes of this change, because that was simply wrong.
Jan
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
2023-02-13 8:08 ` Jan Beulich
@ 2023-02-13 17:40 ` H.J. Lu
0 siblings, 0 replies; 8+ messages in thread
From: H.J. Lu @ 2023-02-13 17:40 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Mon, Feb 13, 2023 at 12:08 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 10.02.2023 18:02, H.J. Lu wrote:
> > Since they used to be in SSE3, should they be also allowed with SSE3?
>
> In order to answer the question, can you please clarify what you mean
> by "used to be in SSE3"? I'm not aware of a spec ever marking them as
> SSE3 insns. And not allowing their use in e.g. generic32+sse3 is one
> of the purposes of this change, because that was simply wrong.
>
I checked 2005 Intel SDM which has a separate CPUID bit for MONITOR/MWAIT.
No need for SSE3 then.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread