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From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
	"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH v2] Support Intel SHA512
Date: Thu, 20 Jul 2023 08:32:12 +0000	[thread overview]
Message-ID: <SA1PR11MB5946E150A8CD42072CAE4797EC3EA@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <d09eef2d-abb9-14b3-13ff-b5dde697fc45@suse.com>

> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/sha512.d
> > @@ -0,0 +1,16 @@
> > +#as:
> 
> What purpose does this line (present in several of the tests) have?
> 
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/sha512.s
> > @@ -0,0 +1,13 @@
> > +# Check 32bit SHA512 instructions
> > +
> > +	.allow_index_reg
> 
> This doesn't look to be needed either.
> 

We use script to generate the testcases so these two are to fit all
circumstances since actually script does not know what will happen
for a new ISA. (The former is for some extra option in as the latter is
for index reg.)

We could omit that but one thing I need to mention is that there are
also some redundant things in all the existing testcases. If we want to
eliminate all of them, some may need careful manual work. I am
wondering if that is time-worthy to change all of them. Therefore, I
propose not to omit that to keep align with all the testcases since it
is not wrong. 

All the other mentioned in the review has been fixed in my v3 patch
which will be sent out later.

Thx,
Haochen

  reply	other threads:[~2023-07-20  8:32 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-13  6:32 [PATCH 0/5] Support Intel Arrow Lake/Lunar Lake ISAs Haochen Jiang
2023-07-13  6:32 ` [PATCH 1/5] Support Intel AVX-VNNI-INT16 Haochen Jiang
2023-07-13  9:29   ` Jan Beulich
2023-07-14  5:51     ` Jiang, Haochen
2023-07-13  6:33 ` [PATCH 2/5] Support Intel SHA512 Haochen Jiang
2023-07-13 10:02   ` Jan Beulich
2023-07-14  3:40     ` Jiang, Haochen
2023-07-14  7:12       ` Jan Beulich
2023-07-18  7:20         ` Jiang, Haochen
2023-07-18  7:54           ` [PATCH v2] " Haochen Jiang
2023-07-18  7:59             ` Jiang, Haochen
2023-07-18  8:51             ` Jan Beulich
2023-07-20  8:32               ` Jiang, Haochen [this message]
2023-07-20 10:37                 ` Jan Beulich
2023-07-20  8:32               ` [PATCH] " Haochen Jiang
2023-07-20 11:07                 ` [PATCH v3] " Jan Beulich
2023-07-27  5:52                   ` Jiang, Haochen
2023-07-18  8:11           ` [PATCH 2/5] " Jan Beulich
2023-07-13  6:33 ` [PATCH 3/5] Support Intel SM3 Haochen Jiang
2023-07-13 10:20   ` Jan Beulich
2023-07-18  8:09     ` [PATCH v2] " Haochen Jiang
2023-07-18  9:03       ` Jan Beulich
2023-07-24  2:54         ` Jiang, Haochen
2023-07-13  6:33 ` [PATCH 4/5] Support Intel SM4 Haochen Jiang
2023-07-13 10:25   ` Jan Beulich
2023-07-18  7:21     ` Jiang, Haochen
2023-07-18  8:13       ` [PATCH v2] " Haochen Jiang
2023-07-18  9:11         ` Jan Beulich
2023-07-13  6:33 ` [PATCH 5/5] Support Intel PBNDKB Haochen Jiang
2023-07-13 10:29   ` Jan Beulich
2023-07-14  7:15     ` Jiang, Haochen

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