Re: [PATCH v2] Support Intel SM3

[Jan Beulich <jbeulich@suse.com>]

On 18.07.2023 10:09, Haochen Jiang wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/sm3.s
> @@ -0,0 +1,37 @@
> +# Check 32bit SM3 instructions
> +
> +	.allow_index_reg
> +	.text
> +_start:
> +	vsm3msg1	%xmm4, %xmm5, %xmm6	 #SM3
> +	vsm3msg1	0x10000000(%esp, %esi, 8), %xmm5, %xmm6	 #SM3
> +	vsm3msg1	(%ecx), %xmm5, %xmm6	 #SM3
> +	vsm3msg1	2032(%ecx), %xmm5, %xmm6	 #SM3 Disp32(f0070000)
> +	vsm3msg1	-2048(%edx), %xmm5, %xmm6	 #SM3 Disp32(00f8ffff)

The numbers in parentheses are odd. I'd prefer if they were omitted,
but I'd also be okay of you flipped their byte order so they properly
correspond (as numbers) to the displacements used.

That said, I'm not sure about their usefulness: The two specific
displacement values chosen are apparently AVX512-inherited, where
they would correspond to the largest/smallest displacements still
compressible. Since these are VEX, not EVEX, encodings, I don't
think these values are of particular interest, and you have memory
forms of the insn earlier. So my suggestion (without insisting)
would be to simply drop these (and similar) lines altogether, or if
at all use forms which in fact use Disp8 encoding.

Other testcase related comments given for the SHA512 patch apply here
as well.

Okay with all of these taken care of.

Jan