From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 2/5] Support Intel SHA512
Date: Tue, 18 Jul 2023 10:11:45 +0200 [thread overview]
Message-ID: <a8bfe790-d857-5f05-f65b-286199bf84ac@suse.com> (raw)
In-Reply-To: <SA1PR11MB59469EEC862793F18E6D48F9EC38A@SA1PR11MB5946.namprd11.prod.outlook.com>
On 18.07.2023 09:20, Jiang, Haochen wrote:
>> As to implying baseline functionality, using AVX (rather than AVX2) makes
>> little sense, so even if the feature check remained (note that various
>> other extensions, including e.g. AVX-VNNI-INT<n>, don't have such a
>> secondary requirement), I'd still be fairly insistent on having the
>> base feature named here (and for SM4) be AVX2 (to be in line with other
>> similar baseline selections).
>
> I confirmed that AVX in doc here means a state of the whole AVX ISA,
> which should include AVX and AVX2.
>
> I will change the imply of SHA512 and SM4 to AVX2 since it looks much more
> reasonable.
Thanks.
> Should we also change the imply of SM3 here?
AVX looks sufficient there, so I'd say only if you have a good justification.
Jan
next prev parent reply other threads:[~2023-07-18 8:11 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 6:32 [PATCH 0/5] Support Intel Arrow Lake/Lunar Lake ISAs Haochen Jiang
2023-07-13 6:32 ` [PATCH 1/5] Support Intel AVX-VNNI-INT16 Haochen Jiang
2023-07-13 9:29 ` Jan Beulich
2023-07-14 5:51 ` Jiang, Haochen
2023-07-13 6:33 ` [PATCH 2/5] Support Intel SHA512 Haochen Jiang
2023-07-13 10:02 ` Jan Beulich
2023-07-14 3:40 ` Jiang, Haochen
2023-07-14 7:12 ` Jan Beulich
2023-07-18 7:20 ` Jiang, Haochen
2023-07-18 7:54 ` [PATCH v2] " Haochen Jiang
2023-07-18 7:59 ` Jiang, Haochen
2023-07-18 8:51 ` Jan Beulich
2023-07-20 8:32 ` Jiang, Haochen
2023-07-20 10:37 ` Jan Beulich
2023-07-20 8:32 ` [PATCH] " Haochen Jiang
2023-07-20 11:07 ` [PATCH v3] " Jan Beulich
2023-07-27 5:52 ` Jiang, Haochen
2023-07-18 8:11 ` Jan Beulich [this message]
2023-07-13 6:33 ` [PATCH 3/5] Support Intel SM3 Haochen Jiang
2023-07-13 10:20 ` Jan Beulich
2023-07-18 8:09 ` [PATCH v2] " Haochen Jiang
2023-07-18 9:03 ` Jan Beulich
2023-07-24 2:54 ` Jiang, Haochen
2023-07-13 6:33 ` [PATCH 4/5] Support Intel SM4 Haochen Jiang
2023-07-13 10:25 ` Jan Beulich
2023-07-18 7:21 ` Jiang, Haochen
2023-07-18 8:13 ` [PATCH v2] " Haochen Jiang
2023-07-18 9:11 ` Jan Beulich
2023-07-13 6:33 ` [PATCH 5/5] Support Intel PBNDKB Haochen Jiang
2023-07-13 10:29 ` Jan Beulich
2023-07-14 7:15 ` Jiang, Haochen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a8bfe790-d857-5f05-f65b-286199bf84ac@suse.com \
--to=jbeulich@suse.com \
--cc=binutils@sourceware.org \
--cc=haochen.jiang@intel.com \
--cc=hjl.tools@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).