[RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions

[Tsukasa OI <research_trasio@irq.a4lg.com>]

This patchset adds support for two recently ratified RISC-V extensions:

-   Zfhmin (Half-precision floating point: conversion only)
-   Zfh    (Half-precision floating point: full arithmetic)

This patchset was intended to be a part of Binutils 2.38 but I was
getting too impatient.  I tested this patchset with Spike simulator and
tested that a few programs with fp16 was working nicely.  However, this
patchset lacks full testsuite.

The only reason I didn't make one was simple: all of floating point
extensions ('F', 'D' and 'Q') didn't have full testsuite.  Thanks to the
fact that this patchset is too late for Binutils 2.38, we have time to
add full testsuite for all floating point extensions.

Also, this patchset lacks pseudoinstructions (intentionally).  Possible
pseudoinstructions to implement later would be:

-   fmv.h
-   fneg.h
-   fabs.h

Besides that, we can begin testing 'Zfh' and 'Zfhmin' extensions with
this patchset.




Tsukasa OI (5):
  RISC-V: Add 'Zfh' and 'Zfhmin' extensions
  RISC-V: Add insn classes for Zfh/Zfhmin extensions
  RISC-V: Add 'Zfh' and 'Zfhmin' instructions
  RISC-V: Add 'flh' and 'fsh' macro instructions
  RISC-V: Add 'Zfh'/'Zfhmin' conflict message

 bfd/elfxx-riscv.c          |  16 +++++-
 gas/config/tc-riscv.c      |  10 ++++
 include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++
 include/opcode/riscv.h     |   6 +++
 opcodes/riscv-opc.c        |  62 +++++++++++++++++++++
 5 files changed, 201 insertions(+), 1 deletion(-)


base-commit: 9ed5be5650ba7c315cd7cfacccc9208de2f555df
-- 
2.32.0