From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>
Cc: binutils@sourceware.org
Subject: [PATCH 0/1] RISC-V: Zfh extension diagnostic addition
Date: Sun, 22 May 2022 18:11:29 +0900 [thread overview]
Message-ID: <cover.1653210663.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1653196480.git.research_trasio@irq.a4lg.com>
Hello,
This is an addition to:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html>
I and Nelson forgot to add extension diagnostics to
`riscv_multi_subset_supports_ext' function (bfd/elfxx-riscv.c).
This patch adds related diagnostics for instruction classes I added in
my Zfh+Zfhmin PATCHSET v2.
Note that, even if instruction class name suggests Zhinx and Zhinxmin,
this is not represented in `riscv_multi_subset_supports_ext' since they
are not officially supported yet.
I note that consensus to place 'H' after 'V' is made:
<https://github.com/riscv/riscv-isa-manual/issues/837>
So, it's going to be canonical to order Zh* extensions after all Zv*.
Considering compatibility and that consensus, we could change
`riscv_ext_canonical_order'...
from "eigmafdqlcbkjtpvn"
to "eigmafdqlcbkjtpvnh" (add H to the tail)
and then we can add Zhinx and Zhinxmin extensions to supported extension
list: `riscv_supported_std_z_ext'. (I'm not sure **when** to do that;
after new ISA manual is ratified? or now?)
Tsukasa OI (1):
RISC-V: Add extension diagnostics to Zfh
bfd/elfxx-riscv.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
base-commit: 7d599d2e1a4fe39de46da8510c4e24bf6b698805
--
2.34.1
next prev parent reply other threads:[~2022-05-22 9:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message Tsukasa OI
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
2022-05-18 9:31 ` Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 0/4] RISC-V: Float16 extensions enhancements Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh' Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh') Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message Tsukasa OI
2022-05-22 9:11 ` Tsukasa OI [this message]
2022-05-22 9:11 ` [PATCH 1/1] RISC-V: Add extension diagnostics to Zfh Tsukasa OI
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