From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 0/4] RISC-V: Float16 extensions enhancements
Date: Sun, 22 May 2022 14:15:10 +0900 [thread overview]
Message-ID: <cover.1653196480.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1641898063.git.research_trasio@irq.a4lg.com>
RFC PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-January/119276.html>
<https://github.com/a4lg/binutils-gdb/tree/a4lg/snapshots/2022-01-11/riscv-zfh-RFC-v1>
This patchset will:
- Add `Zfhmin' extension support
- Refine (refactors) `Zfh' extension support (by Nelson Chu)
- Prepare for `Zhinx' extension
[CHANGES BETWEEN RFC PATCH v1 between PATCH v2]
- Added pseudoinstructions
- Large rebase (based on Nelson Chu's implementation)
- Preparation for `Zhinx' implementation
[Added pseudoinstructions]
I checked into LLVM (llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td) and found
my RFC PATCH v1 ONLY lacked following pseudoinstructions:
- fmv.h
- fneg.h
- fabs.h
In this version, it implements all `Zfh' or `Zfhmin' instructions
implemented in LLVM-CURRENT.
[Preparation for Zhinx implementation]
I mean, `Zhinx' implementation except actual feature support.
Instruction category is refined as follows:
Before:
- INSN_CLASS_ZFH
`Zfh'
- INSN_CLASS_D_AND_ZFH
`Zfh' and `D'
- INSN_CLASS_Q_AND_ZFH
`Zfh' and `Q'
After:
- INSN_CLASS_ZFH_OR_ZHINX
Either `Zfh' or `Zhinx'
Renamed from INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN
`Zfhmin'
Part of former INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN_OR_ZHINXMIN
Either `Zfhmin' or `Zhinxmin'
Part of former INSN_CLASS_ZFH.
- INSN_CLASS_ZFHMIN_AND_D
(`Zfhmin' and `D') or (`Zhinxmin' and `Zdinx')
Renamed from INSN_CLASS_D_AND_ZFH.
- INSN_CLASS_ZFHMIN_AND_Q
(`Zfhmin' and `Q') or (`Zhinxmin' and `Zqinx')
Renamed from INSN_CLASS_Q_AND_ZFH.
INFN_CLASS_ZFHMIN_AND_? do not represent actual required extensions.
This is because it'll be too long if we make this symbol faithful.
Tsukasa OI (4):
RISC-V: Refactor 'Zfh'-related macros
RISC-V: Add instruction declaration for 'Zfh'
RISC-V: Add 'Zfhmin' (and refactor 'Zfh')
RISC-V: Add 'Zfh' / 'Zfhmin' conflict message
bfd/elfxx-riscv.c | 33 ++++---
gas/config/tc-riscv.c | 19 ++--
include/opcode/riscv-opc.h | 180 ++++++++++++++++++++++---------------
include/opcode/riscv.h | 12 +--
opcodes/riscv-opc.c | 126 +++++++++++++-------------
5 files changed, 210 insertions(+), 160 deletions(-)
base-commit: cb3a7614feb82ffdc25161bf60529116c6112ab3
--
2.34.1
next prev parent reply other threads:[~2022-05-22 5:15 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-11 10:47 [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 1/5] RISC-V: Add 'Zfh' and 'Zfhmin' extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 2/5] RISC-V: Add insn classes for Zfh/Zfhmin extensions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 3/5] RISC-V: Add 'Zfh' and 'Zfhmin' instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 4/5] RISC-V: Add 'flh' and 'fsh' macro instructions Tsukasa OI
2022-01-11 10:48 ` [RFC PATCH 5/5] RISC-V: Add 'Zfh'/'Zfhmin' conflict message Tsukasa OI
2022-05-18 1:43 ` [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Kito Cheng
2022-05-18 9:31 ` Tsukasa OI
2022-05-22 5:15 ` Tsukasa OI [this message]
2022-05-22 5:15 ` [PATCH v2 1/4] RISC-V: Refactor 'Zfh'-related macros Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 2/4] RISC-V: Add instruction declaration for 'Zfh' Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 3/4] RISC-V: Add 'Zfhmin' (and refactor 'Zfh') Tsukasa OI
2022-05-22 5:15 ` [PATCH v2 4/4] RISC-V: Add 'Zfh' / 'Zfhmin' conflict message Tsukasa OI
2022-05-22 9:11 ` [PATCH 0/1] RISC-V: Zfh extension diagnostic addition Tsukasa OI
2022-05-22 9:11 ` [PATCH 1/1] RISC-V: Add extension diagnostics to Zfh Tsukasa OI
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