* [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device
@ 2011-07-20 21:01 bugzilla-daemon
2011-07-20 21:02 ` [Bug 1001291] " bugzilla-daemon
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Summary: New HAL for Cortex-M3 Smartfusion device
Product: eCos
Version: CVS
Platform: All
OS/Version: Cortex-M
Status: UNCONFIRMED
Severity: normal
Priority: normal
Component: Patches and contributions
AssignedTo: unassigned@bugs.ecos.sourceware.org
ReportedBy: ecos@hotmail.co.uk
CC: ecos-patches@ecos.sourceware.org
Class: Advice Request
Created an attachment (id=1318)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1318)
Smartfusion HAL
New port for the Actel Smarfusion devices and evaluation board. Supported
peripherals are:
- Serial
- SPI
- I2C
- Ethernet
- DMA
Christophe
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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--- Comment #1 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:02:08 BST ---
Created an attachment (id=1319)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1319)
Evaluation board HAL
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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--- Comment #3 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:03:28 BST ---
Created an attachment (id=1321)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1321)
Ethernet driver for smartfusion
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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Christophe Coutand <ecos@hotmail.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1318|0 |1
is obsolete| |
--- Comment #2 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:02:53 BST ---
Created an attachment (id=1320)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1320)
Smartfusion HAL
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #4 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:04:18 BST ---
Created an attachment (id=1322)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1322)
I2C driver for smartfusion
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #6 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:05:32 BST ---
Created an attachment (id=1324)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1324)
Serial driver for smartfusion
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #5 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:04:53 BST ---
Created an attachment (id=1323)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1323)
SPI driver for smartfusion
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #7 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:06:07 BST ---
Created an attachment (id=1325)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1325)
Flash SPI support for evaluation board
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #8 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:06:47 BST ---
Created an attachment (id=1326)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1326)
Updated doclist
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #9 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:09:13 BST ---
Created an attachment (id=1327)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1327)
Updated ecos.db
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #10 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:11:40 BST ---
The port required the Ethernet PHY posted in :
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001235
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Christophe Coutand <ecos@hotmail.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1322|0 |1
is obsolete| |
--- Comment #11 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-20 22:20:13 BST ---
Created an attachment (id=1328)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1328)
I2C driver for smartfusion
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Christophe Coutand <ecos@hotmail.co.uk> changed:
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----------------------------------------------------------------------------
Attachment #1319|0 |1
is obsolete| |
--- Comment #12 from Christophe Coutand <ecos@hotmail.co.uk> 2011-07-23 12:36:10 BST ---
Created an attachment (id=1330)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1330)
Evaluation board HAL
Updated platform HAL to match latest patch of bugzilla [ 1001235 ]
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John Dallaway <john@dallaway.org.uk> changed:
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CC| |john@dallaway.org.uk
--- Comment #13 from John Dallaway <john@dallaway.org.uk> 2011-07-26 13:46:43 BST ---
Christophe, many thanks for this contribution. Someone will review it in due
course.
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1320| |assignment?(ecos@hotmail.co
Flag| |.uk)
--- Comment #14 from Ilija Kocho <ilijak@siva.com.mk> 2011-10-12 23:05:23 BST ---
(From update of attachment 1320)
Hi Christophe
Thank you for the contribution.
Smartfusion would be a great addition to eCos strength. However in a course of
preparation for processing of your code, while checking your Copyright
assignment, I have noticed that associated copyright disclaimer from STM had
expired 2011-01-12.
As this is hindering inclusion of this port in eCos repository I would ask you
if you could provide a suitable document that will allow inclusion of this
contribution (and possibly your future works) in eCos repository.
Ilija
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #15 from Christophe Coutand <ecos@hotmail.co.uk> 2011-10-13 08:21:37 BST ---
Hi Ilija,
This work falls outside the scope of my work at STM and is not linked to STM
whatsoever, therefore, I believed my FSF assignment should cover it, unless the
assignment is also limited in time?
Regards,
Christophe
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Jonathan Larmour <jifl@ecoscentric.com> changed:
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----------------------------------------------------------------------------
CC| |jifl@ecoscentric.com
--- Comment #16 from Jonathan Larmour <jifl@ecoscentric.com> 2011-10-13 17:36:47 BST ---
Hi Cristophe,
(In reply to comment #15)
> This work falls outside the scope of my work at STM and is not linked to STM
> whatsoever, therefore, I believed my FSF assignment should cover it, unless the
> assignment is also limited in time?
The assignment is not time limited.
However, unfortunately just because it is outside of the scope of the work at
STM does not mean that STM do not "own" it. Many employment contracts in our
industry say that all work performed, and intellectual property (IP) created,
by an employee is owned by the employer. Alternatively some employment
contracts say that all work and IP created using the employer's equipment
(including your development PC) is owned by the employer. This means if you
entirely created and developed it on your home PC, then that would be fine.
So the question is, what does your employment contract say? I would expect all
employment contracts to say something somewhere about the ownership of IP you
create. And if it says nothing then we may have to assume it _might_ be
covered. Of course if, as you say, it is not related to STM and STM have no
interest, then at least it shouldn't be difficult to obtain the copyright
disclaimer again, as a precaution.
Jifl
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--- Comment #17 from Jonathan Larmour <jifl@ecoscentric.com> 2011-11-10 04:32:51 GMT ---
Christophe has been able to get a copyright disclaimer from STM. It looks fine
to me, although it specifically excludes networking stacks. I will have to
consult with the FSF as to whether this could include an ethernet driver -
which could arguably be considered one of the bottom layers of a networking
stack. I doubt it, but I should check. The remainder of the contribution should
be fine to go now though.
Jifl
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1320|assignment?(ecos@hotmail.co |assignment+
Flag|.uk) |
--- Comment #18 from Ilija Kocho <ilijak@siva.com.mk> 2011-11-11 16:37:18 GMT ---
(From update of attachment 1320)
Copyright disclaimer has been sent to FSF.
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1321| |assignment?(ecos@hotmail.co
Flag| |.uk)
--- Comment #19 from Ilija Kocho <ilijak@siva.com.mk> 2011-11-11 16:40:33 GMT ---
(From update of attachment 1321)
Hold on until we get interpretation on Network Stack exception in copyright
disclaimer.
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--- Comment #20 from Ilija Kocho <ilijak@siva.com.mk> 2011-11-11 17:48:11 GMT ---
So we can start with HAL.
First one trivial issue:
CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY is set to 0xE0, and
description is "Set clock ISR priority to lowest priority.", probably carried
from other HAL. Since device is said to have 5 priority bits, please change
either value or description. (I wander if we should consider a CDL for lowest
ISR priority on architecture level).
CYG_HAL_STARTUP: I can see that you have followed our discussion from mailing
list. Please consider the following:
Basic idea is to cover all (or most) memory layouts not employing external
memory on variant level. Since this is a fresh port I would suggest to do it.
1. Placing CYG_HAL_STARTUP in variant tree will avoid it's cloning in
forthcoming (i hope they will come) platform trees and at the same time provide
consistent propagation of it's updates (enhancements and bugs) in each of them.
In order to keep all startup together, platform's CYG_HAL_PLF_STARTUP, if
present, can be "parenthed" by CYG_HAL_STARTUP. Note: "If present means" if
there is external memory, for single-chip boards we can/should omit it.
1.1. Together with CYG_HAL_STARTUP come MLT filesets (fileset = ldi + header)
affected by. Normally, this will require a new pkgconf directory in variant.
Further, all values in MLT files (memory sizes, locations, etc.) can be
parametrized in CDL so it would be possible to cover many, (hopefully all)
combinations of on-chip memory with a handful of MLT filesets.
2. Platforms with external memory is going to use CYG_HAL_PLF_STARTUP as well
as their own MLT filesets in order to override CYG_PLF_STARUP. However they
will also be able to make use of CYG_HAL_STARTUP (for eventual single-chip
emulation, etc.).
Anybody, feel free to comment.
Ilija
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #21 from Jonathan Larmour <jifl@ecoscentric.com> 2011-11-14 00:27:37 GMT ---
(In reply to comment #20)
> So we can start with HAL.
>
> First one trivial issue:
> CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY is set to 0xE0, and
> description is "Set clock ISR priority to lowest priority.", probably carried
> from other HAL. Since device is said to have 5 priority bits, please change
> either value or description. (I wander if we should consider a CDL for lowest
> ISR priority on architecture level).
I would recommend against it at architecture level as it's harder to choose a
good default_value there - it is only in the context of the processor you are
likely to know about other interrupt sources.
> CYG_HAL_STARTUP: I can see that you have followed our discussion from mailing
> list. Please consider the following:
I've missed this discussion, can you tell me what the subject was and on which
list?
> Basic idea is to cover all (or most) memory layouts not employing external
> memory on variant level. Since this is a fresh port I would suggest to do it.
>
> 1. Placing CYG_HAL_STARTUP in variant tree will avoid it's cloning in
> forthcoming (i hope they will come) platform trees and at the same time provide
> consistent propagation of it's updates (enhancements and bugs) in each of them.
> In order to keep all startup together, platform's CYG_HAL_PLF_STARTUP, if
> present, can be "parenthed" by CYG_HAL_STARTUP. Note: "If present means" if
> there is external memory, for single-chip boards we can/should omit it.
>
> 1.1. Together with CYG_HAL_STARTUP come MLT filesets (fileset = ldi + header)
> affected by. Normally, this will require a new pkgconf directory in variant.
> Further, all values in MLT files (memory sizes, locations, etc.) can be
> parametrized in CDL so it would be possible to cover many, (hopefully all)
> combinations of on-chip memory with a handful of MLT filesets.
>
> 2. Platforms with external memory is going to use CYG_HAL_PLF_STARTUP as well
> as their own MLT filesets in order to override CYG_PLF_STARUP. However they
> will also be able to make use of CYG_HAL_STARTUP (for eventual single-chip
> emulation, etc.).
I'm not very keen on the idea of the startup types being split over two
variables.
Let's take a step back. What problem is actually needing to be solved by
CYG_HAL_PLF_STARTUP? I can't help but think that there surely must be a better
way to improve the abstraction in the architectural HAL if there's insufficient
abstraction at the moment.
Just another little issue: in
CYGSEM_HAL_CORTEXM_A2FXXX_DEFINES_IDLE_THREAD_ACTION it talks about
"overwriting" but I believe it was intended to say "overriding".
Jifl
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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--- Comment #22 from Christophe Coutand <ecos@hotmail.co.uk> 2011-11-14 08:33:17 GMT ---
Correct, CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY is not set to
the lowest priority, i can fix that.
For debugging the smartfusion kit, there are several alternatives. Out of the
box, without additional HW, the USB interface as described in all
smartfusion tutorials is used. This method requires the tools provided by Actel
(SoftConsole IDE (Eclipse), Actel flashpro driver and ARM GDB and
Sprite utilities from CodeSourcery). This default debugging setup requires a
special ROM startup type where the FLASH load address is set to 0x60000000 and
the virtual address is set to 0x00000000. Since I also wanted to keep regular
ROM startup type for developer using the JTAG interface, I have introduced the
CDL
CYG_HAL_PLF_STARTUP. Both ROM_SOFTCONSOLE and ROM type leads to use
CYG_HAL_STARTUP=ROM, which is required by the architectural HAL.
Christophe
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #23 from Ilija Kocho <ilijak@siva.com.mk> 2011-11-14 22:04:53 GMT ---
(In reply to comment #21)
> (In reply to comment #20)
> > So we can start with HAL.
> >
> > First one trivial issue:
> > CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY is set to 0xE0, and
> > description is "Set clock ISR priority to lowest priority.", probably carried
> > from other HAL. Since device is said to have 5 priority bits, please change
> > either value or description. (I wander if we should consider a CDL for lowest
> > ISR priority on architecture level).
>
> I would recommend against it at architecture level as it's harder to choose a
> good default_value there - it is only in the context of the processor you are
> likely to know about other interrupt sources.
I am thinking of general macro for lowest interrupt priority (if we find it
useful/desirable). Note: For Cortex-M there is already a CDL for highest
priority. Here is a snippet for lowest:
cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_MIN {
display "Lowest ISR priority"
flavor data
calculated 0xFFFF&\
((((1<<CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)-1)-1)\
<<8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
description "
Calculate the lowest interrupt priority."
}
>
> > CYG_HAL_STARTUP: I can see that you have followed our discussion from mailing
> > list. Please consider the following:
>
> I've missed this discussion, can you tell me what the subject was and on which
> list?
Here it is: http://ecos.sourceware.org/ml/ecos-devel/2011-07/msg00002.html
>
> > Basic idea is to cover all (or most) memory layouts not employing external
> > memory on variant level. Since this is a fresh port I would suggest to do it.
> >
> > 1. Placing CYG_HAL_STARTUP in variant tree will avoid it's cloning in
> > forthcoming (i hope they will come) platform trees and at the same time provide
> > consistent propagation of it's updates (enhancements and bugs) in each of them.
> > In order to keep all startup together, platform's CYG_HAL_PLF_STARTUP, if
> > present, can be "parenthed" by CYG_HAL_STARTUP. Note: "If present means" if
> > there is external memory, for single-chip boards we can/should omit it.
> >
> > 1.1. Together with CYG_HAL_STARTUP come MLT filesets (fileset = ldi + header)
> > affected by. Normally, this will require a new pkgconf directory in variant.
> > Further, all values in MLT files (memory sizes, locations, etc.) can be
> > parametrized in CDL so it would be possible to cover many, (hopefully all)
> > combinations of on-chip memory with a handful of MLT filesets.
> >
> > 2. Platforms with external memory is going to use CYG_HAL_PLF_STARTUP as well
> > as their own MLT filesets in order to override CYG_PLF_STARUP. However they
> > will also be able to make use of CYG_HAL_STARTUP (for eventual single-chip
> > emulation, etc.).
>
> I'm not very keen on the idea of the startup types being split over two
> variables.
>
> Let's take a step back. What problem is actually needing to be solved by
> CYG_HAL_PLF_STARTUP? I can't help but think that there surely must be a better
> way to improve the abstraction in the architectural HAL if there's insufficient
> abstraction at the moment.
The basic idea is to resolve common memory properties for a given
micro-controller family on variant level (for benefits mentioned above).
Commonly the members of controller families generally share common memory
layout, containing similar memory blocks that differ (mainly) in size. This can
be calculated by CDL and presented as a set of simple macros to MLT fileset MLT
fileset={mlt_*.ldi, mlt_*.h}, which makes it possible to cover a number of
chips with a single, relatively simple (i.e. without #ifdef) MLT fileset.
A handful of filesets shall cover all layouts which do not employ external
memory. For configurations with external memory we can continue to use per
platform MLT filesets. Platform shall be able to use both variant/general and
platform/private MLT.
Now we come to CYG_HAL_STARTUP. Startup is closely connected with memory layout
(hence startup types ROM, RAM, SRAM, etc). Essentially startup type determines
the elements for calculation of MLT fileset name. Having both variant and
platform MLT filesets, implies two startup CDL's: CYG_HAL_STARTUP_VAR and
CYG_HAL_STARTUP_PLF.
The easiest way to see relation between variant and platform startup CDLs isby
example. The mechanism is partly described in
http://ecos.sourceware.org/ml/ecos-devel/2011-07/msg00002.html
and is implemented in Kinetis port. However, the Kinetis code presently
available in CVS contains only the variant MLT/STARTUP (no platforms with
external memory). Platform code with external memory is working in our lab but
we're waiting for final HW (memory module) version. (I can provide it but in
this bug it would be alien, maybe i could open a new bug - although early, I
have some questions to discuss regarding external memory anyway - please
advise).
Ilija
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #24 from Ilija Kocho <ilijak@siva.com.mk> 2011-11-14 22:31:31 GMT ---
(In reply to comment #22)
> Correct, CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY is not set to
> the lowest priority, i can fix that.
>
> For debugging the smartfusion kit, there are several alternatives. Out of the
> box, without additional HW, the USB interface as described in all
> smartfusion tutorials is used. This method requires the tools provided by Actel
> (SoftConsole IDE (Eclipse), Actel flashpro driver and ARM GDB and
> Sprite utilities from CodeSourcery). This default debugging setup requires a
> special ROM startup type where the FLASH load address is set to 0x60000000 and
> the virtual address is set to 0x00000000. Since I also wanted to keep regular
> ROM startup type for developer using the JTAG interface, I have introduced the
> CDL
> CYG_HAL_PLF_STARTUP. Both ROM_SOFTCONSOLE and ROM type leads to use
> CYG_HAL_STARTUP=ROM, which is required by the architectural HAL.
OK, So, although construction resembles, you were solving different problem. I
think with little tweaking it is possible to score both goals.
>
> Christophe
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Christophe Coutand <ecos@hotmail.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Attachment #1323|0 |1
is obsolete| |
--- Comment #25 from Christophe Coutand <ecos@hotmail.co.uk> 2011-11-20 13:34:44 GMT ---
Created an attachment (id=1433)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1433)
SPI driver for smartfusion
Fix wrong DMA settings for SPI1
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--- Comment #26 from Christophe Coutand <ecos@hotmail.co.uk> 2011-11-20 13:37:57 GMT ---
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Smartfusion HAL V2
Fix CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY.
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--- Comment #27 from Ilija Kocho <ilijak@siva.com.mk> 2011-12-03 15:47:39 GMT ---
Chhristophe
Thank you for the updates. I tried configuration with default template
(Ethernet driver diff not patched yet).
jifl, have we interpretation from FSF regarding STM disclaimer exception on
networking stacks?
As expected configtool raises warning for missing Ethernet driver, otherwise
creation of build tree proceedes without problem.
However building process raises following warnings (default tpl no changes):
.../spi_a2fxxx.c:466: warning: ‘a2fxxx_transaction_begin’ defined but not used
.../spi_a2fxxx.c:554: warning: ‘a2fxxx_transaction_transfer’ defined but not
used
.../spi_a2fxxx.c:568: warning: ‘a2fxxx_transaction_tick’ defined but not used
.../spi_a2fxxx.c:583: warning: ‘a2fxxx_transaction_end’ defined but not used
.../spi_a2fxxx.c:608: warning: ‘a2fxxx_get_config’ defined but not used
.../spi_a2fxxx.c:614: warning: ‘a2fxxx_set_config’ defined but not used
.../spi_a2fxxx.c:218: warning: ‘a2fxxx_spi_bus_setup’ defined but not used
As expected warnings disappear when a spi bus is enabled, I guess you know what
to do.
Reading spi_a2fxxx.c I have also noticed that you are using \ for extension of
normal (non macro) lines. I would ask you to remove them since some editors
(such as MicroEmacs put warning on such lines.
Also some lines are much longer than famous 78 char boundary (example line 386)
I would ask you to also check other files for similar issues.
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--- Comment #28 from Christophe Coutand <ecos@hotmail.co.uk> 2011-12-03 16:50:13 GMT ---
Hi Ilija,
Thank you for your review and comments, I will update the patches accordingly.
The FSF has rejected the Ethernet driver contribution, I will try to get an
updated disclaimer.
Regards,
Christophe
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Flag|.uk) |
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Ethernet driver for smartfusion
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Flash SPI support for evaluation board
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I2C driver for smartfusion
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--- Comment #32 from Christophe Coutand <ecos@hotmail.co.uk> 2011-12-18 16:26:48 GMT ---
Created an attachment (id=1467)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1467)
Flash SPI support for evaluation board
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #34 from Christophe Coutand <ecos@hotmail.co.uk> 2011-12-18 16:28:27 GMT ---
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Serial driver for smartfusion
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--- Comment #33 from Christophe Coutand <ecos@hotmail.co.uk> 2011-12-18 16:27:56 GMT ---
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SPI driver for smartfusion
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Evaluation board HAL
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Smartfusion HAL
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--- Comment #37 from Christophe Coutand <ecos@hotmail.co.uk> 2011-12-18 16:33:08 GMT ---
Hi Ilija,
I updated the patches according to your comments, I tried to respect better the
78 char boundary whenever possible.
Regards,
Christophe
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--- Comment #38 from Ilija Kocho <ilijak@siva.com.mk> 2012-01-02 18:39:08 GMT ---
Hi Christophe, thank you for the update.
There is some trailing whitespace that I can remove. Just FYI ChangeLogs,
unlike source code, should be with tabs.
I have one suggestion, that is to move at25 flash test:
from devs/flash/cortexm/a2fxxx/a2f200_eval
to devs/flash/spi/at25dfxxx
where it will be available to every platform as a general at25dfxxx test.
Next question is Ethernet driver, it is dependent on disclaimer from your
company.
Ilija
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--- Comment #39 from Christophe Coutand <ecos@hotmail.co.uk> 2012-01-07 14:22:49 GMT ---
Hi Ilija,
I have setteled to locate the at25 flash test in a platform specific location
devs/flash/cortexm/a2fxxx/a2f200_eval/ because the test case requires some
platform specific device instanciation and needs to know about the SPI flash
base address.
At the opposite, the m25pxx SPI test case is located in the driver package but
is specific to the STM3210E board so it's never actually compiled.
I think it's possible to add an interface in the CDL plus a parameter defining
the SPI flash base address to make the test case generic for all platforms. I
will provide a patch seperatly.
I am working with a new disclaimer that will include the Ethernet driver,
should be ready soon.
Regards,
Christophe
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--- Comment #40 from Christophe Coutand <ecos@hotmail.co.uk> 2012-01-07 14:36:57 GMT ---
Hi Ilija,
I think the devs/flash/spi/at25dfxxx/flash_at25dfxxx.cdl could have the
following entry:
cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_TESTS {
display "SPI flash driver tests for Atmel AT95DFxxx flash"
active_if CYGPKG_KERNEL
active_if CYGPKG_IO_SPI
requires { CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE == 1 }
flavor data
no_define
calculated { "tests/at25dfxxx_test.c" }
description "
This option specifies the set of tests for the Atmel AT95DFxxx
SPI flash."
}
The platform specific code shall implement
CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE and define the base address of the SPI
flash with:
CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE0_BASE
Let me know what you think.
Christophe
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--- Comment #41 from Ilija Kocho <ilijak@siva.com.mk> 2012-01-07 22:44:48 GMT ---
(In reply to comment #40)
> Hi Ilija,
>
> I think the devs/flash/spi/at25dfxxx/flash_at25dfxxx.cdl could have the
> following entry:
>
> cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_TESTS {
> display "SPI flash driver tests for Atmel AT95DFxxx flash"
> active_if CYGPKG_KERNEL
> active_if CYGPKG_IO_SPI
> requires { CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE == 1 }
> flavor data
> no_define
> calculated { "tests/at25dfxxx_test.c" }
> description "
> This option specifies the set of tests for the Atmel AT95DFxxx
> SPI flash."
> }
>
> The platform specific code shall implement
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE and define the base address of the SPI
> flash with:
>
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE0_BASE
>
> Let me know what you think.
>
> Christophe
Seem fit. I am dealing with SST25xx and started something similar but this
looks more complete so I would ask you for a permission to borrow it. In return
I'll do some testing.
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--- Comment #42 from Ilija Kocho <ilijak@siva.com.mk> 2012-01-07 23:10:35 GMT ---
(In reply to comment #40)
> Hi Ilija,
>
[SNIP]
> The platform specific code shall implement
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE and define the base address of the SPI
> flash with:
>
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE0_BASE
Could you consider this alternative name CYGNUM_DEVS_FLASH_SPI_AT25XXX_MAP_ADDR
?
The idea is to point out that we actually do map the flash to some (virtual)
address.
>
> Let me know what you think.
>
> Christophe
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--- Comment #43 from Ilija Kocho <ilijak@siva.com.mk> 2012-01-07 23:21:55 GMT ---
(In reply to comment #40)
> Hi Ilija,
>
> I think the devs/flash/spi/at25dfxxx/flash_at25dfxxx.cdl could have the
> following entry:
>
> cdl_option CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_TESTS {
> display "SPI flash driver tests for Atmel AT95DFxxx flash"
> active_if CYGPKG_KERNEL
> active_if CYGPKG_IO_SPI
> requires { CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE == 1 }
> flavor data
> no_define
> calculated { "tests/at25dfxxx_test.c" }
> description "
> This option specifies the set of tests for the Atmel AT95DFxxx
> SPI flash."
> }
>
> The platform specific code shall implement
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE and define the base address of the SPI
> flash with:
>
> CYGHWR_DEVS_FLASH_SPI_AT25DFXXX_DEVICE0_BASE
>
> Let me know what you think.
>
> Christophe
Btw you can also put SPI parameters in this CDL package (bus, chip select,
speed, delays, etc).
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--- Comment #44 from Christophe Coutand <ecos@hotmail.co.uk> 2012-01-08 08:48:43 GMT ---
Hi Ilija,
I opened a different case for the SPI flash:
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001449
Christophe
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--- Comment #45 from Ilija Kocho <ilijak@siva.com.mk> 2012-02-10 13:23:50 GMT ---
(In reply to comment #39)
> Hi Ilija,
>
> I am working with a new disclaimer that will include the Ethernet driver,
> should be ready soon.
Any news? If it takes too much time we may consider checking in without
Ethernet, and add Ethernet when you get the disclaimer.
Ilija
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--- Comment #46 from Christophe Coutand <ecos@hotmail.co.uk> 2012-02-12 10:16:28 GMT ---
Hi Ilija,
I will check again the status of the new disclaimer and revert to you.
However, I would like to fix Bug 1001449 first. I see in your attachment (Flash
driver SST25XX SPI tests 120206) from Bug 1001450
that you have defined CYGNUM_DEVS_FLASH_SPI_SS25XX_MAP_ADDR directly in the
test case (flash_sst25xx_test.c), instead of spreading
CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR.
In my proposal (1001449), I suggested to have a platform specific include in
the test case C file that provides the configuration of the platform flash:
#include CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
And CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL is defined in the platform CDL as
done other places:
define_proc {
puts $::cdl_system_header "#define
CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
<pkgconf/devs_flash_cortexm_a2f200_eval.h>"
}
What do you think?
Regards,
Christophe
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--- Comment #47 from Ilija Kocho <ilijak@siva.com.mk> 2012-02-12 12:15:56 GMT ---
(In reply to comment #46)
> Hi Ilija,
>
> I will check again the status of the new disclaimer and revert to you.
>
> However, I would like to fix Bug 1001449 first. I see in your attachment (Flash
> driver SST25XX SPI tests 120206) from Bug 1001450
> that you have defined CYGNUM_DEVS_FLASH_SPI_SS25XX_MAP_ADDR directly in the
> test case (flash_sst25xx_test.c), instead of spreading
> CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR.
Nice catch. Thank you for pointing this out. It is a ghost from old code.
>
> In my proposal (1001449), I suggested to have a platform specific include in
> the test case C file that provides the configuration of the platform flash:
>
> #include CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
>
> And CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL is defined in the platform CDL as
> done other places:
>
> define_proc {
> puts $::cdl_system_header "#define
> CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
> <pkgconf/devs_flash_cortexm_a2f200_eval.h>"
> }
>
> What do you think?
I have defined CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR in the driver CDL
but you are right. Things like this, I would call them /configurable constants/
should come from the HAL. Every platform can have it's own address space.
I am going to change it, only, I would parent
CYGNUM_DEVS_FLASH_SPI_SST25XX_DEV0_MAP_ADDR (or
CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL) by their respective FLASH drivers.
Regards
Ilija
P.S.
Speaking of HAL /configurable constants/, you may find interesting to see and
comment (and I hope consider for Smartfusion) my discussion
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001397#c13 with Tomas Frydrych
regarding consolidated /Interrupt Priority Scheme/. I think that it will be of
help to application programmers for tuning real-time system behavior.
You can see this feature implemented implemented in the latest Variant and
Platform (as well as affected driver) attachments in Bug 1001450.
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--- Comment #48 from Jonathan Larmour <jifl@ecoscentric.com> 2012-02-13 01:38:37 GMT ---
(In reply to comment #46)
> In my proposal (1001449), I suggested to have a platform specific include in
> the test case C file that provides the configuration of the platform flash:
>
> #include CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
>
> And CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL is defined in the platform CDL as
> done other places:
>
> define_proc {
> puts $::cdl_system_header "#define
> CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_CDL
> <pkgconf/devs_flash_cortexm_a2f200_eval.h>"
> }
>
> What do you think?
Just a little thing but the naming of options like that should be something
like CYGDAT_DEVS_FLASH_SPI_AT25DFXXX_PLF_H, not _CDL. Using _CDL might mislead
some into thinking it has actual CDL in it, which obviously it doesn't.
Jifl
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Attachment #1471|0 |1
is obsolete| |
--- Comment #50 from Christophe Coutand <ecos@hotmail.co.uk> 2012-02-26 11:26:37 GMT ---
Created an attachment (id=1596)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1596)
Smartfusion HAL
Updated Smartfusion HAL with new interrupt priority scheme
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Created an attachment (id=1595)
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Ethernet driver for smartfusion
Updated Ethernet driver with new interrupt priority scheme
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Evaluation board HAL
Updated Evaluation board HAL with new interrupt priority scheme
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Smartfusion HAL
Updated Evaluation board HAL with new interrupt priority scheme
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Flash SPI support for evaluation board
Updated Flash SPI with new interrupt priority scheme
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--- Comment #54 from Christophe Coutand <ecos@hotmail.co.uk> 2012-02-26 11:32:37 GMT ---
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Serial driver for smartfusion
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Jonathan Larmour <jifl@ecoscentric.com> changed:
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Attachment #1595| |assignment+
Flag| |
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--- Comment #55 from Jonathan Larmour <jifl@ecoscentric.com> 2012-02-28 17:49:00 GMT ---
Christophe's assignment and disclaimer has now been approved by the FSF. Once
the ethernet driver has been reviewed, it is allowed to go in.
Thanks for working through the process Christophe!
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Ilija Kocho <ilijak@siva.com.mk> changed:
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----------------------------------------------------------------------------
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--- Comment #56 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-07 21:48:13 GMT ---
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I2C driver for smartfusion 120307
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SPI driver for smartfusion 120307
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Ethernet driver for smartfusion 120307
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Evaluation board HAL 120307
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Smartfusion HAL 120307
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--- Comment #61 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-07 21:54:48 GMT ---
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Flash SPI support for evaluation board 120307
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Ilija Kocho <ilijak@siva.com.mk> changed:
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Attachment #1600|0 |1
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--- Comment #62 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-07 22:00:28 GMT ---
Created an attachment (id=1632)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1632)
Serial driver for smartfusion 120307
Christophe
Programs compile without warnings but there were some trailing whitespace that
I took liberty to trim. I also edited some lines that looked too long.
Compilation is still clean but I haven't a target to test.
Please test submitted patches and if you are happy I would commit.
Ilija
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--- Comment #63 from Christophe Coutand <ecos@hotmail.co.uk> 2012-03-12 18:36:11 GMT ---
Hi Ilija,
Thank you for cleaning the patches. Latest patches are running OK on the
target. I have re-tested the set of patches also including Bug 1001449 for
running the SPI flash test case.
Regards,
Christophe
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--- Comment #64 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-12 22:10:14 GMT ---
Now checked in.
Christophe,
Thank you for contribution of support for very interesting device. Please
update and check how it runs on your target.
Ilija
P.S.: After check-in/update I (by accident) compiled with GCC 4.6.2 and found
out a warning (below). It's an easy fix but let's first try it on your target
as is.
ecos/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c:106:16: warning:
variable ‘res’ set but not used [-Wunused-but-set-variable]
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--- Comment #65 from Christophe Coutand <ecos@hotmail.co.uk> 2012-03-13 19:07:12 GMT ---
Hi Ilija,
Thanks for your valuable time. The code checked-in compiles and run fine on
target.
I could not compile using GCC 4.6.2, something with my cygwin setup I beleive.
Will you fix the warning or shall I provide a patch?
Regards,
Christophe
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--- Comment #66 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-13 20:23:50 GMT ---
(In reply to comment #65)
> Hi Ilija,
>
> Thanks for your valuable time. The code checked-in compiles and run fine on
> target.
>
> I could not compile using GCC 4.6.2, something with my cygwin setup I beleive.
[Off topic] Have you tried Linux VM?
> Will you fix the warning or shall I provide a patch?
Don't bother, I'm involved in fixing 4.6 warnings anyway, I'll do it.
Ilija
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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From: bugzilla-daemon @ 2012-03-31 14:38 UTC (permalink / raw)
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--- Comment #67 from Ilija Kocho <ilijak@siva.com.mk> 2012-03-31 15:37:32 BST ---
Christophe
(In reply to comment #66)
> (In reply to comment #65)
> > Hi Ilija,
> >
> > Thanks for your valuable time. The code checked-in compiles and run fine on
> > target.
> >
> > I could not compile using GCC 4.6.2, something with my cygwin setup I beleive.
>
> [Off topic] Have you tried Linux VM?
> > Will you fix the warning or shall I provide a patch?
>
> Don't bother, I'm involved in fixing 4.6 warnings anyway, I'll do it.
I did try to fix the warnings in Actel port and I'm not sure how should they
resolve, especially the one at spi_a2fxxx.c:337:5.
Can you please fix them?
Below is a capture from the compilation:
Ilija
/home/vae/Proekti/ecos/repo/cvs/maint/ecos_cc/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c:
In function ‘a2fxxx_dma_isr’:
/home/vae/Proekti/ecos/repo/cvs/maint/ecos_cc/packages/hal/cortexm/a2fxxx/var/current/src/hal_dma.c:106:16:
warning: variable ‘res’ set but not used [-Wunused-but-set-variable]
/home/vae/Proekti/ecos/repo/cvs/maint/ecos_cc/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c:
In function ‘a2fxxx_transaction_begin’:
/home/vae/Proekti/ecos/repo/cvs/maint/ecos_cc/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c:337:5:
warning: ‘ss’ may be used uninitialized in this function [-Wuninitialized]
/home/vae/Proekti/ecos/repo/cvs/maint/ecos_cc/packages/devs/spi/cortexm/a2fxxx/current/src/spi_a2fxxx.c:300:16:
note: ‘ss’ was declared here
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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--- Comment #68 from Christophe Coutand <ecos@hotmail.co.uk> 2012-04-01 09:04:26 BST ---
Created an attachment (id=1685)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1685)
GCC compilation warning
Uploaded patch to fix the warnings. Patch not tested yet
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
2011-07-20 21:01 [Bug 1001291] New: New HAL for Cortex-M3 Smartfusion device bugzilla-daemon
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--- Comment #69 from Christophe Coutand <ecos@hotmail.co.uk> 2012-04-01 10:07:01 BST ---
Ilija,
Patch is now retested OK with GCC 4.6.3 and GCC 4.3.2.
Christophe
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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--- Comment #70 from Ilija Kocho <ilijak@siva.com.mk> 2012-04-01 20:37:27 BST ---
(In reply to comment #69)
> Ilija,
>
> Patch is now retested OK with GCC 4.6.3 and GCC 4.3.2.
>
> Christophe
Thank you for the patch Christophe.
Checked in.
Ilija
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* [Bug 1001291] New HAL for Cortex-M3 Smartfusion device
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Ilija Kocho <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution|--- |CURRENTRELEASE
--- Comment #71 from Ilija Kocho <ilijak@siva.com.mk> ---
Checked in long time ago. Closing.
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Ilija Kocho [Илија Кочо] <ilijak@siva.com.mk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |CLOSED
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