[Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

            Bug ID: 109977
           Summary: [14 Regression] ICE: output_operand: incompatible
                    floating point / vector register operand for '%d' at
                    -Og
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: aarch64-unknown-linux-gnu

Created attachment 55161
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55161&action=edit
reduced testcase

Compiler output:
$ aarch64-unknown-linux-gnu-gcc -Og testcase.c
during RTL pass: final
testcase.c: In function 'foo':
testcase.c:14:1: internal compiler error: output_operand: incompatible floating
point / vector register operand for '%d'
   14 | }
      | ^
0xe12aff output_operand_lossage(char const*, ...)
        /repo/gcc-trunk/gcc/final.cc:3190
0xe12cc5 output_operand(rtx_def*, int)
        /repo/gcc-trunk/gcc/final.cc:3632
0xe13a90 output_asm_insn(char const*, rtx_def**)
        /repo/gcc-trunk/gcc/final.cc:3525
0xe1889b output_asm_insn(char const*, rtx_def**)
        /repo/gcc-trunk/gcc/final.cc:3421
0xe1889b final_scan_insn_1
        /repo/gcc-trunk/gcc/final.cc:2841
0xe18bbb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
        /repo/gcc-trunk/gcc/final.cc:2887
0xe18df4 final_1
        /repo/gcc-trunk/gcc/final.cc:1979
0xe19a68 rest_of_handle_final
        /repo/gcc-trunk/gcc/final.cc:4240
0xe19a68 execute
        /repo/gcc-trunk/gcc/final.cc:4318
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ aarch64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-aarch64/bin/aarch64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r14-1235-20230525094833-g0d1e0d7433c-checking-yes-rtl-df-extra-aarch64/bin/../libexec/gcc/aarch64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: aarch64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl
--with-sysroot=/usr/aarch64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=aarch64-unknown-linux-gnu
--with-ld=/usr/bin/aarch64-unknown-linux-gnu-ld
--with-as=/usr/bin/aarch64-unknown-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r14-1235-20230525094833-g0d1e0d7433c-checking-yes-rtl-df-extra-aarch64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.0 20230525 (experimental) (GCC)

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0
               Host|x86_64-pc-linux-gnu         |
   Last reconfirmed|                            |2023-05-26
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(insn 12 11 13 (set (mem/c:V2DF (plus:DI (reg/f:DI 31 sp)
                (const_int 16 [0x10])) [1 w+0 S16 A128])
        (vec_duplicate:V2DF (reg:DF 0 x0 [orig:95 v ] [95])))
"/app/example.cpp":12:5 1392 {aarch64_simd_stpv2df}
     (expr_list:REG_DEAD (reg:DF 0 x0 [orig:95 v ] [95])
        (nil)))


(define_insn "aarch64_simd_stp<mode>"
  [(set (match_operand:VP_2E 0 "aarch64_mem_pair_lanes_operand" "=Umn,Umn")
        (vec_duplicate:VP_2E (match_operand:<VEL> 1 "register_operand"
"w,r")))]
  "TARGET_SIMD"
  "@
   stp\\t%<Vetype>1, %<Vetype>1, %y0
   stp\\t%<vw>1, %<vw>1, %y0"
  [(set_attr "type" "neon_stp, store_<ldpstp_vel_sz>")]
)


;; For scalar usage of vector/FP registers, widening
(define_mode_attr vw [(V8QI "w") (V16QI "w")
                      (V4HI "w") (V8HI "w")
                      (V2SI "w") (V4SI "w")
                      (DI   "x") (V2DI "x")
                      (V2SF "s") (V4SF "s")
                      (V2DF "d")])

Most likely should be using vwcore instead:
;; Corresponding core element mode for each vector mode.  This is a
;; variation on <vw> mapping FP modes to GP regs.
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
                          (V4HI "w") (V8HI "w")
                          (V2SI "w") (V4SI "w")
                          (DI   "x") (V2DI "x")
                          (V4HF "w") (V8HF "w")
                          (V4BF "w") (V8BF "w")
                          (V2SF "w") (V4SF "w")
                          (V2DF "x")
                          (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
                          (VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
                          (VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
                          (VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
                          (VNx4SI "w") (VNx2SI "w")
                          (VNx4SF "w") (VNx2SF "w")
                          (VNx2DI "x")
                          (VNx2DF "x")])

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Introduced by  r14-215-g85279b0bddc1c5 .

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |slyfox at gcc dot gnu.org

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 110880 has been marked as a duplicate of this bug. ***

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I agree with the analysis and
2023-11-24  Andrew Pinski  <pinskia@gmail.com>
            Jakub Jelinek  <jakub@redhat.com>

        * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
        rather than %<vw> for alternative with r constraint on input operand.

        * gcc.dg/pr109977.c: New test.

--- gcc/config/aarch64/aarch64-simd.md.jj       2023-11-22 22:55:20.577075762
+0100
+++ gcc/config/aarch64/aarch64-simd.md  2023-11-24 12:51:22.855215700 +0100
@@ -269,7 +269,7 @@ (define_insn "aarch64_simd_stp<mode>"
   "TARGET_SIMD"
   {@ [ cons: =0 , 1 ; attrs: type            ]
      [ Umn      , w ; neon_stp               ] stp\t%<Vetype>1, %<Vetype>1,
%y0
-     [ Umn      , r ; store_<ldpstp_vel_sz>  ] stp\t%<vw>1, %<vw>1, %y0
+     [ Umn      , r ; store_<ldpstp_vel_sz>  ] stp\t%<vwcore>1, %<vwcore>1,
%y0
   }
 )

--- gcc/testsuite/gcc.dg/pr109977.c.jj  2023-11-24 12:51:04.551473591 +0100
+++ gcc/testsuite/gcc.dg/pr109977.c     2023-11-24 12:50:44.158760916 +0100
@@ -0,0 +1,16 @@
+/* PR target/109977 */
+/* { dg-do compile } */
+/* { dg-options "-Og" } */
+
+typedef double __attribute__((__vector_size__ (8))) V;
+typedef double __attribute__((__vector_size__ (16))) W;
+V v;
+int i;
+extern void bar (void *);
+
+void
+foo (void)
+{
+  W w = __builtin_shufflevector (v, (W) { }, 0, 0);
+  bar (&w);
+}
fixes it (though it will take me a while to find where to bootstrap/regtest
this).

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5

[sjames at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

--- Comment #5 from Sam James <sjames at gcc dot gnu.org> ---
If needed, you can email me an SSH key for a Neoverse-N1 (fp asimd evtstrm aes
pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
ssbs) which should be fast.

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:a6a43a3b763816fec7c4eec6ae7be5b263dff340

commit r14-5840-ga6a43a3b763816fec7c4eec6ae7be5b263dff340
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Nov 25 10:30:39 2023 +0100

    aarch64: Fix up aarch64_simd_stp<mode> [PR109977]

    The aarch64_simd_stp<mode> pattern uses w constraint in one alternative and
    r in another, but for the latter incorrectly uses <vw> iterator in %<vw>1
which
    expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to
    the pattern) and %w1 for others, so it ICEs if the alternative is selected
    during final.  Compared to this, <vwcore> macro has the same values for all
    modes but uses w for V2DF and V2SF.

    2023-11-24  Andrew Pinski  <pinskia@gmail.com>
                Jakub Jelinek  <jakub@redhat.com>

            PR target/109977
            * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use
<vwcore>
            rather than %<vw> for alternative with r constraint on input
operand.

            * gcc.dg/pr109977.c: New test.

[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.