[Bug rtl-optimization/111822] New: [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[Bug rtl-optimization/111822] New: [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

            Bug ID: 111822
           Summary: [12/13/14 Regression] during RTL pass: lr_shrinkage
                    ICE: in operator[], at vec.h:910 with -O2 -m32
                    -flive-range-shrinkage -fno-dce -fnon-call-exceptions
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: x86_64-pc-linux-gnu

Created attachment 56115
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56115&action=edit
reduced testcase

Compiler output:
$ x86_64-pc-linux-gnu-gcc -O2 -m32 -flive-range-shrinkage -fno-dce
-fnon-call-exceptions testcase.C 
during RTL pass: lr_shrinkage
testcase.C: In member function 'void SQVM::CallNative()':
testcase.C:41:1: internal compiler error: in operator[], at vec.h:910
   41 | }
      | ^
0x7f615a vec<edge_def*, va_gc, vl_embed>::operator[](unsigned int)
        /repo/gcc-trunk/gcc/vec.h:910
0x7f63db vec<basic_block_def*, va_gc, vl_embed>::operator[](unsigned int)
        /repo/gcc-trunk/gcc/vec.h:936
0x7f63db pre_and_rev_post_order_compute_fn(function*, int*, int*, bool)
        /repo/gcc-trunk/gcc/cfganal.cc:1066
0x123b947 pre_and_rev_post_order_compute(int*, int*, bool)
        /repo/gcc-trunk/gcc/cfganal.cc:1079
0x1203292 init_alias_analysis()
        /repo/gcc-trunk/gcc/alias.cc:3429
0x285e960 sched_init()
        /repo/gcc-trunk/gcc/haifa-sched.cc:7331
0x286030d haifa_sched_init()
        /repo/gcc-trunk/gcc/haifa-sched.cc:7368
0x174ff5c schedule_insns()
        /repo/gcc-trunk/gcc/sched-rgn.cc:3524
0x175063b schedule_insns()
        /repo/gcc-trunk/gcc/sched-rgn.cc:3518
0x175063b rest_of_handle_live_range_shrinkage
        /repo/gcc-trunk/gcc/sched-rgn.cc:3720
0x175063b execute
        /repo/gcc-trunk/gcc/sched-rgn.cc:3807
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ x86_64-pc-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-amd64/bin/x86_64-pc-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r14-4642-20231015125226-g77faa3e198a-checking-yes-rtl-df-extra-nobootstrap-amd64/bin/../libexec/gcc/x86_64-pc-linux-gnu/14.0.0/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--disable-bootstrap --with-cloog --with-ppl --with-isl
--build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu
--target=x86_64-pc-linux-gnu --with-ld=/usr/bin/x86_64-pc-linux-gnu-ld
--with-as=/usr/bin/x86_64-pc-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r14-4642-20231015125226-g77faa3e198a-checking-yes-rtl-df-extra-nobootstrap-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.0 20231015 (experimental) (GCC)

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |12.4

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-10-22
             Status|UNCONFIRMED                 |NEW
           Keywords|                            |needs-bisection

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

Note changing:
```
  while (oldtop)
    Null();
```
to:
```
  if (oldtop)
    while (true)
      Null();
```

to get the same IR coming into expand, still passes in GCC 11.4.0.

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[sjames at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Sam James <sjames at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |sjames at gcc dot gnu.org

--- Comment #2 from Sam James <sjames at gcc dot gnu.org> ---
I was confused at first while just checking the range because 10 has a
different ICE:

$ g++-10 /tmp/foo.cxx -o /tmp/foo -c -O2 -m32 -flive-range-shrinkage -fno-dce
-fnon-call-exceptions
during RTL pass: lr_shrinkage
/tmp/foo.cxx: In member function 'void SQVM::CallNative()':
/tmp/foo.cxx:41:1: internal compiler error: Segmentation fault
   41 | }
      | ^
0xc86baf crash_signal
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/toplev.c:328
0x84d9a6 pre_and_rev_post_order_compute_fn(function*, int*, int*, bool)
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/cfganal.c:1036
0x84db87 pre_and_rev_post_order_compute(int*, int*, bool)
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/cfganal.c:1049
0x81c940 init_alias_analysis()
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/alias.c:3391
0x14d9f91 sched_init()
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/haifa-sched.c:7326
0x14e4ebd haifa_sched_init()
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/haifa-sched.c:7363
0xc3e02b schedule_insns()
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/sched-rgn.c:3514
0xc3e6db schedule_insns()
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/sched-rgn.c:3508
0xc3e6db rest_of_handle_live_range_shrinkage
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/sched-rgn.c:3710
0xc3e6db execute
        /usr/src/debug/sys-devel/gcc-10.5.0/gcc-10.5.0/gcc/sched-rgn.c:3797
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://bugs.gentoo.org/> for instructions.

Anyway, bisecting.

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[sjames at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #3 from Sam James <sjames at gcc dot gnu.org> ---
bisect says

045206450386bcd774db3bde0c696828402361c6 is the first bad commit
commit 045206450386bcd774db3bde0c696828402361c6
Author: Richard Biener <rguenther@suse.de>
Date:   Fri Nov 12 10:21:22 2021 +0100

    tree-optimization/102880 - improve CD-DCE

i.e. r12-5301-g045206450386bc

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at gcc dot gnu.org
           Priority|P3                          |P1

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |WAITING
           Priority|P1                          |P2

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
We've released with the bug so this cannot be P1.  Note the bisected to rev.
likely just made this latent issue show up.

Btw, I can't reproduce - any implicit options missing?

> ./cc1plus -quiet t.ii -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #5 from Zdenek Sojka <zsojka at seznam dot cz> ---
(In reply to Richard Biener from comment #4)
> We've released with the bug so this cannot be P1.  Note the bisected to rev.
> likely just made this latent issue show up.
> 
> Btw, I can't reproduce - any implicit options missing?
> 
> > ./cc1plus -quiet t.ii -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions

$
/repo/gcc-trunk/binary-trunk-20240305153615-g08ec4adb028-checking-yes-rtl-df-extra-amd64/bin/../libexec/gcc/x86_64-pc-linux-gnu/14.0.1/cc1plus
attachment.txt -m32 "-mtune=generic" "-march=x86-64" -O2 -flive-range-shrinkage
-fno-dce -fnon-call-exceptions
...
attachment.txt: In member function 'void SQVM::CallNative()':
attachment.txt:41:1: internal compiler error: in operator[], at vec.h:910
   41 | }
      | ^
...

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |NEW

--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
Ah, -march=x86-64 was it.  The ICE means that the entry block wasn't reachable
from EXIT_BLOCK which means there are unreachable blocks.

This usually means some pass lacks CFG cleanup or delete_unreachable_blocks ().

A simple fix is the following, but the proper thing to do is track down who
leaves unreachable blocks around in the IL.

diff --git a/gcc/sched-rgn.cc b/gcc/sched-rgn.cc
index eb75d1bdb26..ff455ddd12e 100644
--- a/gcc/sched-rgn.cc
+++ b/gcc/sched-rgn.cc
@@ -65,6 +65,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "dbgcnt.h"
 #include "pretty-print.h"
 #include "print-rtl.h"
+#include "cfgcleanup.h"

 /* Disable warnings about quoting issues in the pp_xxx calls below
    that (intentionally) don't follow GCC diagnostic conventions.  */
@@ -3707,6 +3708,7 @@ rest_of_handle_live_range_shrinkage (void)
 #ifdef INSN_SCHEDULING
   int saved;

+  delete_unreachable_blocks ();
   initialize_live_range_shrinkage ();
   saved = flag_schedule_interblock;
   flag_schedule_interblock = false;

[Bug rtl-optimization/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> ---
IMO verify_flow_info on RTL should ICE with unreachable blocks.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |wrong-code
          Component|rtl-optimization            |target

--- Comment #8 from Richard Biener <rguenth at gcc dot gnu.org> ---
I think it's split1 doing wrong.  We end up with

;; basic block 3, loop depth 0, count 118111600 (estimated locally, freq
1.0000), maybe hot
;;  prev block 2, next block 4, flags: (NEW, HOT_PARTITION, RTL, MODIFIED)
;;  pred:       2 [always]  count:118111600 (estimated locally, freq 1.0000)
(FALLTHRU)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(6){ }u-1(7){ }u-1(16){ }u-1(19){ }}
;; lr  in
;; lr  use
;; lr  def
;; live  in
;; live  gen
;; live  kill
(note 124 10 126 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(jump_insn 126 124 127 3 (set (pc)
        (label_ref 125)) -1
     (nil)
 -> 125)
;;  succ:       6 [always]  count:118111600 (estimated locally, freq 1.0000)
;; lr  out
;; live  out

(barrier 127 126 84)
;; basic block 4, loop depth 0, count 0 (precise, freq 0.0000), probably never
executed
;;  prev block 3, next block 5, flags: (REACHABLE, HOT_PARTITION, RTL,
MODIFIED)
;;  pred:
;; bb 4 artificial_defs: { d-1(0){ }d-1(1){ }}
;; bb 4 artificial_uses: { u-1(6){ }u-1(7){ }u-1(16){ }u-1(19){ }}
;; lr  in        6 [bp] 7 [sp] 16 [argp] 19 [frame]
;; lr  use       6 [bp] 7 [sp] 16 [argp] 19 [frame]
;; lr  def       0 [ax] 1 [dx] 114 115
;; live  in      6 [bp] 7 [sp] 16 [argp] 19 [frame]
;; live  gen     0 [ax] 1 [dx] 114 115
;; live  kill
(code_label/s 84 127 86 4 13 (nil) [1 uses])
(note 86 84 93 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 93 86 85 4 (set (reg:SI 115)
        (reg:SI 0 ax)) "t.ii":22:42 -1
     (expr_list:REG_DEAD (reg:SI 0 ax)

so block 4 is unreachable.  split1 does

   102: r122:DI#0=vec_concat([r98:SI],0)
    10: r102:DI#0=r122:DI#0
-      REG_EH_REGION 0xd
   124: NOTE_INSN_BASIC_BLOCK 3

that looks spurious, so possibly some other pass leaves around the dead EH.
Earlier this was

   10: r102:DI=[r98:SI]
      REG_EH_REGION 0xd
      ; pc falls through to BB 5

and STV2 changes this like

-   10: r102:DI=[r98:SI]
+  102: r122:DI#0=vec_concat([r98:SI],0)
+   10: r102:DI#0=r122:DI#0
       REG_EH_REGION 0xd
       ; pc falls through to BB 5

failing to move EH (or refuse the lowering).

Thus a target issue, even wrong-code I think as we now fail to catch
a trap by the [r98:SI] load.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #9 from Uroš Bizjak <ubizjak at gmail dot com> ---
The offending insn is emitted in general_scalar_chain::convert_op due to
preloading, but I have no idea how EH should be adjusted.  There is another
instance in timode_scalar_chain::convert_op.

emit_insn_before (gen_rtx_SET (gen_rtx_SUBREG (vmode, tmp, 0),
                               gen_gpr_to_xmm_move_src (vmode, *op)),
                  insn);

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #10 from Richard Biener <rguenth at gcc dot gnu.org> ---
The easiest fix would be to refuse applying STV to a insn that
can_throw_internal () (that's an insn that has associated EH info).  Updating
in this case would require splitting the BB or at least moving the now
no longer throwing insn to the next block (along the fallthru edge).

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |liuhongt at gcc dot gnu.org

--- Comment #11 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #10)
> The easiest fix would be to refuse applying STV to a insn that
> can_throw_internal () (that's an insn that has associated EH info).  Updating
> in this case would require splitting the BB or at least moving the now
> no longer throwing insn to the next block (along the fallthru edge).

This would be simply:

--cut here--
diff --git a/gcc/config/i386/i386-features.cc
b/gcc/config/i386/i386-features.cc
index 1de2a07ed75..90acb33db49 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -437,6 +437,10 @@ scalar_chain::add_insn (bitmap candidates, unsigned int
insn_uid,
       && !HARD_REGISTER_P (SET_DEST (def_set)))
     bitmap_set_bit (defs, REGNO (SET_DEST (def_set)));

+  if (cfun->can_throw_non_call_exceptions
+      && can_throw_internal (insn))
+    return false;
+
   /* ???  The following is quadratic since analyze_register_chain
      iterates over all refs to look for dual-mode regs.  Instead this
      should be done separately for all regs mentioned in the chain once.  */
--cut here--

But I think, we could do better. Adding CC.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #12 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #11)
> (In reply to Richard Biener from comment #10)
> > The easiest fix would be to refuse applying STV to a insn that
> > can_throw_internal () (that's an insn that has associated EH info).  Updating
> > in this case would require splitting the BB or at least moving the now
> > no longer throwing insn to the next block (along the fallthru edge).
> 
> This would be simply:
> 
> --cut here--
> diff --git a/gcc/config/i386/i386-features.cc
> b/gcc/config/i386/i386-features.cc
> index 1de2a07ed75..90acb33db49 100644
> --- a/gcc/config/i386/i386-features.cc
> +++ b/gcc/config/i386/i386-features.cc
> @@ -437,6 +437,10 @@ scalar_chain::add_insn (bitmap candidates, unsigned int
> insn_uid,
>        && !HARD_REGISTER_P (SET_DEST (def_set)))
>      bitmap_set_bit (defs, REGNO (SET_DEST (def_set)));
>  
> +  if (cfun->can_throw_non_call_exceptions

that part shouldn't be necessary, can_throw_internal is cheap enough
(but yes, unless STV handles calls it's correct)

> +      && can_throw_internal (insn))
> +    return false;
> +
>    /* ???  The following is quadratic since analyze_register_chain
>       iterates over all refs to look for dual-mode regs.  Instead this
>       should be done separately for all regs mentioned in the chain once.  */
> --cut here--
> 
> But I think, we could do better. Adding CC.

We sure could, but I doubt it's too important?  Maybe for Go/Ada.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #13 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #12)

> > But I think, we could do better. Adding CC.
> 
> We sure could, but I doubt it's too important?  Maybe for Go/Ada.

Preloading stuff is simply loading from the same DImode address, so I'd think
that EH_NOTE should be moved from the original insn to the new insn without
much problems.

Please note that on x86_32 split pass is later splitting DImode memory access
to two SImode loads, this looks somehow harder problem as far as EH notes are
concerned, as the one above.

I'm not versed in this area, so I'll leave the fix to someone else.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ebotcazou at gcc dot gnu.org

--- Comment #14 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #13)
> (In reply to Richard Biener from comment #12)
> 
> > > But I think, we could do better. Adding CC.
> > 
> > We sure could, but I doubt it's too important?  Maybe for Go/Ada.
> 
> Preloading stuff is simply loading from the same DImode address, so I'd
> think that EH_NOTE should be moved from the original insn to the new insn
> without much problems.
> 
> Please note that on x86_32 split pass is later splitting DImode memory
> access to two SImode loads, this looks somehow harder problem as far as EH
> notes are concerned, as the one above.
> 
> I'm not versed in this area, so I'll leave the fix to someone else.

On RTL I'd defer to Eric here.

Note for the correctness issue on branches I'd probably prefer the
"simple" approach (unless a true solution turns out equally simple).

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #15 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> Preloading stuff is simply loading from the same DImode address, so I'd
> think that EH_NOTE should be moved from the original insn to the new insn
> without much problems.

Old reload and LRA need to do that too; see copy_reg_eh_region_note_forward
and its callers for a possible way out.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[liuhongt at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #16 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #11)
> (In reply to Richard Biener from comment #10)
> > The easiest fix would be to refuse applying STV to a insn that
> > can_throw_internal () (that's an insn that has associated EH info).  Updating
> > in this case would require splitting the BB or at least moving the now
> > no longer throwing insn to the next block (along the fallthru edge).
> 
> This would be simply:
> 
> --cut here--
> diff --git a/gcc/config/i386/i386-features.cc
> b/gcc/config/i386/i386-features.cc
> index 1de2a07ed75..90acb33db49 100644
> --- a/gcc/config/i386/i386-features.cc
> +++ b/gcc/config/i386/i386-features.cc
> @@ -437,6 +437,10 @@ scalar_chain::add_insn (bitmap candidates, unsigned int
> insn_uid,
>        && !HARD_REGISTER_P (SET_DEST (def_set)))
>      bitmap_set_bit (defs, REGNO (SET_DEST (def_set)));
>  
> +  if (cfun->can_throw_non_call_exceptions
> +      && can_throw_internal (insn))
> +    return false;
> +
>    /* ???  The following is quadratic since analyze_register_chain
>       iterates over all refs to look for dual-mode regs.  Instead this
>       should be done separately for all regs mentioned in the chain once.  */
> --cut here--
> 
> But I think, we could do better. Adding CC.

It looks like the similar issue we have solved in PR89650 with
r9-6543-g12fb7712a8a20f. We manually split the block after insn.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[liuhongt at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

Hongtao Liu <liuhongt at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #17 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
Forget to add PR to my commit, it's solved by r14-9459-g618e34d56cc38e and
backport to r13-8438-gbdbcfbfcf59138, r12-10214-ga861f940efffae.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #18 from Uroš Bizjak <ubizjak at gmail dot com> ---
When we split
(insn 37 36 38 10 (set (reg:DI 104 [ _18 ])
        (mem:DI (reg/f:SI 98 [ CallNative_nclosure.0_1 ]) [6 MEM[(struct
SQRefCounted *)CallNative_nclosure.0_1]._uiRef+0 S8 A32])) "test.C":22:42 84
{*movdi_internal}
     (expr_list:REG_EH_REGION (const_int -11 [0xfffffffffffffff5])

into

(insn 104 36 37 10 (set (subreg:V2DI (reg:DI 124) 0)
        (vec_concat:V2DI (mem:DI (reg/f:SI 98 [ CallNative_nclosure.0_1 ]) [6
MEM[(struct SQRefCounted *)CallNative_nclosure.0_1]._uiRef+0 S8 A32])
            (const_int 0 [0]))) "test.C":22:42 -1
        (nil)))
(insn 37 104 105 10 (set (subreg:V2DI (reg:DI 104 [ _18 ]) 0)
        (subreg:V2DI (reg:DI 124) 0)) "test.C":22:42 2024 {movv2di_internal}
     (expr_list:REG_EH_REGION (const_int -11 [0xfffffffffffffff5])
        (nil)))

we must copy the REG_EH_REGION note to the first insn and split the block
after the newly added insn.  The REG_EH_REGION on the second insn will be
removed later since it no longer traps.

gcc/ChangeLog:

* config/i386/i386-features.cc
(general_scalar_chain::convert_op): Handle REG_EH_REGION note.
(convert_scalars_to_vector): Ditto.
* config/i386/i386-features.h (class scalar_chain): New
memeber control_flow_insns.

gcc/testsuite/ChangeLog:

* g++.target/i386/pr111822.C: New test.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #19 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:b96c5436880d7926299314a33c953171082ab59e

commit r14-9523-gb96c5436880d7926299314a33c953171082ab59e
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon Mar 18 20:40:29 2024 +0100

    i386: Unify {general,timode}_scalar_chain::convert_op [PR111822]

    Recent PR111822 fix implemented REG_EH_REGION note copying to a STV
converted
    preload instruction in general_scalar_chain::convert_op.  However, the same
    issue remains in timode_scalar_chain::convert_op.  Instead of copying the
    newly introduced code to timode_scalar_chain::convert_op, the patch unifies
    both functions to a common function.

            PR target/111822

    gcc/ChangeLog:

            * config/i386/i386-features.cc (smode_convert_cst): New function
            to handle SImode, DImode and TImode immediates, generalized from
            timode_convert_cst.
            (timode_convert_cst): Remove.
            (scalar_chain::convert_op): Unify from
            general_scalar_chain::convert_op and
timode_scalar_chain::convert_op.
            (general_scalar_chain::convert_op): Remove.
            (timode_scalar_chain::convert_op): Remove.
            (timode_scalar_chain::convert_insn): Update the call to
            renamed timode_convert_cst.
            * config/i386/i386-features.h (class scalar_chain):
            Redeclare convert_op as protected class member.
            (class general_calar_chain): Remove convert_op.
            (class timode_scalar_chain): Ditto.

    gcc/testsuite/ChangeLog:

            * g++.target/i386/pr111822.C (dg-do): Compile only for ia32
targets.
            (dg-options): Add -march=x86-64.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #20 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:1a6d04fce7d78b9e5201333be0c0877390f81bc3

commit r13-8466-g1a6d04fce7d78b9e5201333be0c0877390f81bc3
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Mar 19 16:56:11 2024 +0100

    i386: Unify {general,timode}_scalar_chain::convert_op [PR111822]

    Recent PR111822 fix implemented REG_EH_REGION note copying to a STV
converted
    preload instruction in general_scalar_chain::convert_op.  However, the same
    issue remains in timode_scalar_chain::convert_op.  Instead of copying the
    newly introduced code to timode_scalar_chain::convert_op, the patch unifies
    both functions to a common function.

            PR target/111822

    gcc/ChangeLog:

            * config/i386/i386-features.cc (smode_convert_cst): New function
            to handle SImode, DImode and TImode immediates.
            (scalar_chain::convert_op): Unify from
            general_scalar_chain::convert_op and
timode_scalar_chain::convert_op.
            (general_scalar_chain::convert_op): Remove.
            (timode_scalar_chain::convert_op): Remove.
            * config/i386/i386-features.h (class scalar_chain):
            Redeclare convert_op as protected class member.
            (class general_calar_chain): Remove convert_op.
            (class timode_scalar_chain): Ditto.

    gcc/testsuite/ChangeLog:

            * g++.target/i386/pr111822.C (dg-do): Compile only for ia32
targets.
            (dg-options): Add -march=x86-64.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #21 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:f6ed0466d40de496b14225fae44acf618dac1fd2

commit r12-10284-gf6ed0466d40de496b14225fae44acf618dac1fd2
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Mar 19 16:57:50 2024 +0100

    testsuite/i386: Correct pr111822.C dg-do options [PR111822]

            PR target/111822

    gcc/testsuite/ChangeLog:

            * g++.target/i386/pr111822.C (dg-do): Compile only for ia32
targets.
            (dg-options): Add -march=x86-64.

[Bug target/111822] [12/13/14 Regression] during RTL pass: lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since r12-5301-g045206450386bc

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111822

--- Comment #22 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed also for TImode STV.