public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-12 18:47 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-12 18:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cb46ea1bcb79339010feaa2bae2821765fe881b9
commit cb46ea1bcb79339010feaa2bae2821765fe881b9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 12 14:46:52 2022 -0400
Update ChangeLog.meissner.
2022-04-12 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3fcd2992075..c4fec7b0639 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,67 @@
+==================== Work086, patch #8:
+
+Eliminate power8 fusion options, use power8 tuning, PR target/102059
+
+This is V4 of the patch. Compared to V3 of the patch, GCC will just
+ignore -m{,no-}power8-fusion and -m{,no-}power8-fusion-sign.
+
+The splitting of signed halfword and word loads into unsigned load and
+sign extension is now suppressed with -Os, but it is done normally if we
+are not optimizing for space.
+
+The power8 fusion support used to be set automatically when -mcpu=power8 or
+-mtune=power8 was used, and it was cleared for other cpu's. However, if you
+used the target attribute or target #pragma to change the default cpu type or
+tuning, you would get an error that a target specifiction option mismatch
+occurred.
+
+This occurred because the rs6000_can_inline_p function just compares the ISA
+bits between the called inline function and the caller. If the ISA flags of
+the called function is not a subset of the ISA flags of the caller, we won't do
+the inlinging. When a power9 or power10 function inlines a function that is
+explicitly compiled for power8, the power8 function has the power8 fusion bits
+set and the power9 or power10 functions do not have the fusion bits set.
+
+This code removes the -mpower8-fusion option. It also removes the
+undocumented -mpower8-fusion-sign option. It only enables power8 fusion
+if we are tuning for a power8.
+
+Similarly, I left in the pragma target and attribute target support for
+power8-fusion, but using it doesn't do anything now. This is because I
+told the customer who encountered this problem that one solution was to
+add an explicit no-power8-fusion option in their target pragma or
+attribute to work around the problem.
+
+2022-04-12 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/102059
+ * config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
+ (ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
+ (POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ Delete code that set the power8 fusion options automatically.
+ (rs6000_opt_masks): Allow #pragma target and attribute target
+ power8-fusion option for backwards compatibility.
+ (rs6000_print_options_internal): Skip printing backward
+ compatibility options that are just ignored.
+ * config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro.
+ (TARGET_P8_FUSION_SIGN): Likewise.
+ (MASK_P8_FUSION): Delete.
+ * config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but
+ ignore the no form and warn that the option was removed for the regular
+ form.
+ (-mpower8-fusion-sign): Warn that the option has been removed.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Delete
+ -mpower8-fusion.
+
+gcc/testsuite/
+ PR target/102059
+ * gcc.dg/lto/pr102059-1_0.c: Remove -mno-power8-fusion.
+ * gcc.dg/lto/pr102059-2_0.c: Likewise.
+ * gcc.target/powerpc/pr102059-3.c: Likewise.
+ * gcc.target/powerpc/pr102059-4.c: New test.
+
==================== Work086, patch #7:
Optimize multiply/add of DImode extended to TImode.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-14 20:19 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-14 20:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:053c68d9cb8422460874ab6daaf110c4b42e1126
commit 053c68d9cb8422460874ab6daaf110c4b42e1126
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 14 16:19:03 2022 -0400
Update ChangeLog.meissner.
2022-04-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c4fec7b0639..459e8e4e9d1 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,21 @@
+==================== Work086, patch #9:
+
+Generate vadduqm and vsubuqm for TImode add/subtract
+
+If the TImode variable is in an Altivec register instead of a GPR
+register, then generate vadduqm and vsubuqm instead of having to move the
+value to the GPR registers and doing the add and subtract with carry
+instructions. To do this, we have to delay the splitting of the addition
+and subtraction until after register allocation.
+
+2022-03-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/rs6000.md (addti3): Generate vadduqm if we are
+ using the Altivec registers.
+ (subti3): Generate vsubuqm if we using the Altivec registers.
+ (negti3): New insn.
+
==================== Work086, patch #8:
Eliminate power8 fusion options, use power8 tuning, PR target/102059
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-11 18:14 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-11 18:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7fb4061124bbcb8010f4190dbe4db4c1cac5b4b7
commit 7fb4061124bbcb8010f4190dbe4db4c1cac5b4b7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 11 14:14:13 2022 -0400
Update ChangeLog.meissner.
2022-04-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9c1e8865b25..a1b6ed52c67 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,41 @@
+==================== Work086, patch #7:
+
+Optimize multiply/add of DImode extended to TImode.
+
+On power9 and power10 systems, we have instructions that support doing
+64-bit integers converted to 128-bit integers and producing 128-bit
+results. This patch adds support to generate these instructions.
+
+Previously GCC had define_expands to handle conversion of the 64-bit
+extend to 128-bit and multiply. This patch changes these define_expands
+to define_insn_and_split and then it provides combiner patterns to
+generate thes multiply/add instructions.
+
+To support using this optimization on power9, this patch extend the sign
+extend DImode to TImode to also run on power9 (added for PR
+target/104698).
+
+This patch needs the previous patch to add unsigned DImode to TImode
+conversion so that the combiner can combine the extend, multiply, and add
+instructions.
+
+
+2022-04-05 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/103109
+ * config/rs6000/rs6000.md (su_int32): New code attribute.
+ (<u>mul<mode><dmode>3): Convert from define_expand to
+ define_insn_and_split.
+ (maddld<mode>4): Add generator function.
+ (<u>mulditi3_<u>adddi3): New insn.
+ (<u>mulditi3_add_const): New insn.
+ (<u>mulditi3_<u>adddi3_upper): New insn.
+
+gcc/testsuite/
+ PR target/103109
+ * gcc.target/powerpc/pr103109.c: New test.
+
==================== Work086, patch #6:
Add zero_extendditi2. Improve lxvr*x code generation.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-11 18:04 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-11 18:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bbdae9310ac14e81e9e5c1898f0f50c70e24a9bb
commit bbdae9310ac14e81e9e5c1898f0f50c70e24a9bb
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 11 14:04:15 2022 -0400
Update ChangeLog.meissner.
2022-04-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 2354ed8df96..9c1e8865b25 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,53 @@
+==================== Work086, patch #6:
+
+Add zero_extendditi2. Improve lxvr*x code generation.
+
+This pattern adds zero_extendditi2 so that if we are extending DImode to
+TImode, and we want the result in a vector register, the compiler can
+generate MTVSRDDD.
+
+In addition the patterns for generating lxvr{b,h,w,d}x were tuned to allow
+loading to gpr registers. This prevents needlessly doing direct moves to
+get the value into the vector registers if the gpr register was already
+selected.
+
+In updating the insn counts for two tests due to these changes, I noticed
+the tests were done at -O0. I changed this so that the tests are now done
+at the normal -O2 optimization level.
+
+2022-04-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/vsx.md (vsx_lxvr<wd>x): Add support for loading to
+ GPR registers.
+ (vsx_stxvr<wd>x): Add support for storing from GPR registers.
+ (zero_extendditi2): New insn.
+
+gcc/testsuite/
+ * gcc.target/powerpc/vsx-load-element-extend-int.c: Use -O2
+ instead of -O0 and update insn counts.
+ * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
+ * gcc.target/powerpc/zero-extend-di-ti.c: New test.
+
+==================== Work086, patch #5:
+
+Make addti3/subti3 be define_insn_and_split, instead of define_expand
+
+This patch makes addti3 and subti3 be define_insn_and_split instead of
+define_expand. This patch will be a building block to support in a future
+patch PR target/103109 which wants to optimize 128-bit some integer
+multiply-add combinations to use the power9 maddld, maddhd, maddhdu
+instructions. In order to support recognizing the multiply and add
+combination, we need to keep the addti3 and subti3 as complete insns
+through the combiner phase.
+
+2022-04-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/rs6000.md (addti3): Don't immediately expand the
+ insn. Delay expansion until the split passes.
+ (subti3): Likewise.
+
==================== Work086, patch #4:
Eliminate power8 fusion options, use power8 tuning, PR target/102059
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-07 22:24 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-07 22:24 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6f2db8ad0736fa36fd8a56946c8a63c165a77f1e
commit 6f2db8ad0736fa36fd8a56946c8a63c165a77f1e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 7 18:23:58 2022 -0400
Update ChangeLog.meissner.
2022-04-07 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index f7eef06b3e6..2354ed8df96 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,65 @@
+==================== Work086, patch #4:
+
+Eliminate power8 fusion options, use power8 tuning, PR target/102059
+
+The power8 fusion support used to be set automatically when -mcpu=power8 or
+-mtune=power8 was used, and it was cleared for other cpu's. However, if you
+used the target attribute or target #pragma to change the default cpu type or
+tuning, you would get an error that a target specifiction option mismatch
+occurred.
+
+This occurred because the rs6000_can_inline_p function just compares the ISA
+bits between the called inline function and the caller. If the ISA flags of
+the called function is not a subset of the ISA flags of the caller, we won't do
+the inlinging. When a power9 or power10 function inlines a function that is
+explicitly compiled for power8, the power8 function has the power8 fusion bits
+set and the power9 or power10 functions do not have the fusion bits set.
+
+This code removes the -mpower8-fusion option. It also removes the
+undocumented -mpower8-fusion-sign option. It only enables power8 fusion
+if we are tuning for a power8. Power8 sign fusion is only enabled if we
+are tuning for a power8 and we have -O3 optimization or higher.
+
+I left the -mno-power8-fusion in rs6000.opt and made it so it doesn't
+issue a warning. If the user explicitly used -mpower8-fusion, then they
+will get a warning that the swtich has been removed.
+
+Similarly, I left in the pragma target and attribute target support for
+power8-fusion, but using it doesn't do anything now. This is because I
+believe the customer who encountered this problem now is explicitly
+setting the no-power8-fusion option in the pragma or attribute to avoid
+the warning.
+
+2022-04-07 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/102059
+ * config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
+ (ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
+ (POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ Delete code that set the power8 fusion options automatically.
+ (rs6000_opt_masks): Allow #pragma target and attribute target to set
+ power8-fusion, but these no longer represent an option that the
+ user can set.
+ (rs6000_print_options_internal): Skip printing nop options.
+ * config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro.
+ (TARGET_P8_FUSION_SIGN): Likewise.
+ (MASK_P8_FUSION): Delete.
+ * config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but
+ ignore the no form and warn that the option was removed for the regular
+ form.
+ (-mpower8-fusion-sign): Warn that the option has been removed.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Delete
+ -mpower8-fusion.
+
+gcc/testsuite/
+ PR target/102059
+ * gcc.dg/lto/pr102059-1_0.c: Remove -mno-power8-fusion.
+ * gcc.dg/lto/pr102059-2_0.c: Likewise.
+ * gcc.target/powerpc/pr102059-3.c: Likewise.
+ * gcc.target/powerpc/pr102059-4.c: New test.
+
==================== Work086, patch #3:
Replace UNSPEC with RTL code for extendditi2.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-07 20:24 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-07 20:24 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3fb9446e67d8a3bb81eda0f64d3b82622999999c
commit 3fb9446e67d8a3bb81eda0f64d3b82622999999c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 7 16:23:45 2022 -0400
Update ChangeLog.meissner.
2022-04-07 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 102 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4e39b994616..f7eef06b3e6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,105 @@
+==================== Work086, patch #3:
+
+Replace UNSPEC with RTL code for extendditi2.
+
+When I submitted my patch on March 12th for extendditi2, Segher wished I
+had removed the use of the UNSPEC for the vextsd2q instruction. This
+patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC.
+
+
+2022-03-31 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.
+ (extendditi2_vector): Rewrite to use VEC_SELECT as a
+ define_expand.
+ (extendditi2_vector2): New insn.
+
+==================== Work086, patch #2:
+
+Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
+
+This is version 2 of the patch. The original patch was:
+
+| Date: Mon, 28 Mar 2022 12:26:02 -0400
+| Subject: [PATCH 1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
+| Message-ID: <YkHhmvwSJF7DUDhJ@toto.the-meissners.org>
+| https://gcc.gnu.org/pipermail/gcc-patches/2022-March/592420.html
+
+In PR target/99293, it was pointed out that doing:
+
+ vector long long dest0, dest1, src;
+ /* ... */
+ dest0 = vec_splats (vec_extract (src, 0));
+ dest1 = vec_splats (vec_extract (src, 1));
+
+would generate slower code.
+
+It generates the following code on power8:
+
+ ;; vec_splats (vec_extract (src, 0))
+ xxpermdi 0,34,34,3
+ xxpermdi 34,0,0,0
+
+ ;; vec_splats (vec_extract (src, 1))
+ xxlor 0,34,34
+ xxpermdi 34,0,0,0
+
+However on power9 and power10 it generates:
+
+ ;; vec_splats (vec_extract (src, 0))
+ mfvsld 3,34
+ mtvsrdd 34,9,9
+
+ ;; vec_splats (vec_extract (src, 1))
+ mfvsrd 9,34
+ mtvsrdd 34,9,9
+
+This is due to the power9 having the mfvsrld instruction which can extract
+either 64-bit element into a GPR. While there are alternatives for both
+vector registers and GPR registers, the register allocator prefers to put
+DImode into GPR registers.
+
+However in this case, it is better to have a single combiner pattern that
+can generate a single xxpermdi, instead of doing 2 insnsns (the extract
+and then the concat). This is particularly true if the two operations are
+move from vector register and move to vector register. As Segher pointed
+out in a previous version of the patch, the combiner already tries doing
+creating a (vec_duplicate (vec_select ...)) pattern, but we didn't provide
+one.
+
+This patch reworks vsx_xxspltd_<mode> for V2DImode and V2DFmode so that it
+no longer uses an UNSPEC. Instead it uses VEC_DUPLICATE, which the
+combiner checks for.
+
+I have built Spec 2017 with this patch installed, and the cam4_r benchmark
+is the only benchmark that generated different code (3 mfvsrld/mtvsrdd
+pairs of instructions were replaced with xxpermdi).
+
+I have built bootstrap versions on the following systems and I have run
+the regression tests. There were no regressions in the runs:
+
+ Power9 little endian, --with-cpu=power9
+ Power10 little endian, --with-cpu=power10
+ Power8 big endian, --with-cpu=power8 (both 32-bit & 64-bit tests)
+
+Can I install this into the trunk? After a burn-in period, can I backport
+and install this into GCC 11 and GCC 10 branches?
+
+2022-03-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/99293
+ * config/rs6000/rs6000-p8swap.cc (rtx_is_swappable_p): Remove
+ UNSPEC_VSX_XXSPLTD case.
+ * config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): Delete.
+ (vsx_xxspltd_<mode>): Rewrite to use VEC_DUPLICATE.
+
+gcc/testsuite:
+ PR target/99293
+ * gcc.target/powerpc/builtins-1.c: Update insn count.
+ * gcc.target/powerpc/pr99293.c: New test.
+
==================== Work086, patch #1:
Disable float128 tests on VxWorks.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner.
@ 2022-04-06 22:54 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-04-06 22:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:891cf99f6a4007f2851ca4eb5f7e56edd5d9cc1e
commit 891cf99f6a4007f2851ca4eb5f7e56edd5d9cc1e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 6 18:54:05 2022 -0400
Update ChangeLog.meissner.
2022-04-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 3e96d3f36c8..4e39b994616 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,28 @@
+==================== Work086, patch #1:
+
+Disable float128 tests on VxWorks.
+
+In PR target/104253, it was pointed out the that test case added as part
+of fixing the PR does not work on VxWorks because float128 is not
+supported on that system. I have modified the three tests for float128 so
+that they are manually excluded on VxWorks systems. In looking at the
+code, I also added checks in check_effective_target_ppc_ieee128_ok to
+disable the systems that will never support VSX instructions which are
+required for float128 support (eabi, eabispe, darwin).
+
+2022-04-06 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+ PR target/104253
+ * lib/target-supports.exp (check_ppc_float128_sw_available): Do
+ not run float128 tests on VxWorks.
+ (check_ppc_float128_hw_available): Likewise.
+ (check_effective_target_ppc_ieee128_ok): Do not run float128 tests
+ on VxWorks. Also disable systems that do not support VSX
+ instructions.
+
+==================== Work086, branch head:
+
2022-04-06 Michael Meissner <meissner@linux.ibm.com>
Clone branch
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-04-14 20:19 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-12 18:47 [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2022-04-14 20:19 Michael Meissner
2022-04-11 18:14 Michael Meissner
2022-04-11 18:04 Michael Meissner
2022-04-07 22:24 Michael Meissner
2022-04-07 20:24 Michael Meissner
2022-04-06 22:54 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).