public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-26 15:45 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-26 15:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d3b51e1e2ed8a45976292fa4fb008aa710652036
commit d3b51e1e2ed8a45976292fa4fb008aa710652036
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 11:44:55 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-29 3:31 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-29 3:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cb0a13ead1f258353f1e3142288ba1f291674848
commit cb0a13ead1f258353f1e3142288ba1f291674848
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 23:31:35 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly.
2023-04-28 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d64e03ae53b..59a3e83b7fa 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4159,23 +4159,25 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-28 18:30 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-28 18:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ae852218fb682cc99389da854dda9efbf9457360
commit ae852218fb682cc99389da854dda9efbf9457360
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:30:16 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation. In doing so, I restricted the
optimization to only occur if the memory address did not use an Altivec style
address with AND -16.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation. Restrict
vector addresses to not use Altivec addressing.
Diff:
---
gcc/config/rs6000/vsx.md | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index feb7fc753a6..9d98b962f66 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4085,23 +4085,28 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
+;; on power8 due to the vector byte swap support which creates Altivec
+;; addresses. These are eliminated after register allocation since we use 'Q'
+;; or 'Z' constraints.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-28 18:25 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-28 18:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:adf1281cb08bd1548419e9290b7bc5f1eed4f799
commit adf1281cb08bd1548419e9290b7bc5f1eed4f799
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:25:18 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation. In doing so, I restricted the
optimization to only occur if the memory address did not use an Altivec style
address with AND -16.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation. Restrict
vector addresses to not use Altivec addressing.
Diff:
---
gcc/config/rs6000/vsx.md | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index feb7fc753a6..dc8d45d30e7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4085,23 +4085,28 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
+;; on power8 due to the vector byte swap support which creates Altivec
+;; addresses. These are eliminated after register allocation since we use 'Q'
+;; or 'Z' constraints.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "non_altivec_memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-28 3:28 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-28 3:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:91e48ad1a58856e4fd0bdce67e91551c7a0f8d65
commit 91e48ad1a58856e4fd0bdce67e91551c7a0f8d65
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 23:28:18 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6b1975df847..2696d93becf 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4085,23 +4085,28 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
+;; on power8 due to the vector byte swap support which creates Altivec
+;; addresses. These are eliminated after register allocation since we use 'Q'
+;; or 'Z' constraints.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-27 2:57 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-27 2:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:67b9b179a830ee4a8708d2f7bdc50e5891adbc3e
commit 67b9b179a830ee4a8708d2f7bdc50e5891adbc3e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:56:49 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..19a502b99a3 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4087,23 +4087,28 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory
+;; Variable V16QI/V8HI/V4SI extract from memory. We need to split after reload
+;; on power8 due to the vector byte swap support which creates Altivec
+;; addresses. These are eliminated after register allocation since we use 'Q'
+;; or 'Z' constraints.
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-25 15:55 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 15:55 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:939a23c44a0e8c01638b249350d60ac887596d49
commit 939a23c44a0e8c01638b249350d60ac887596d49
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 11:54:44 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-25 6:30 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 6:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7e189c9dcaa4449a3720bad1e981ae6e24571317
commit 7e189c9dcaa4449a3720bad1e981ae6e24571317
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:30:26 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_<mode>_var_load): Allow vector
registers to be loaded. Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-25 2:18 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 2:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c13c9b2c2c7c0db68cb23cafd3c16d53f192f2f7
commit c13c9b2c2c7c0db68cb23cafd3c16d53f192f2f7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 22:17:40 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
(vsx_extract_<mode>_var_load): Allow vector registers to be loaded.
Split before register allocation.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..497aac24319 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,23 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,<VSX_EX_ISA>")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers.
@ 2023-04-25 2:11 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 2:11 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7f5887b68e9018ce346823aa06560ba99992a88e
commit 7f5887b68e9018ce346823aa06560ba99992a88e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 22:11:21 2023 -0400
Allow variable element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded into vector registers directly. It also
will be split before register allocation.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
(vsx_extract_<mode>_var_load): Allow vector registers to be loaded.
Diff:
---
gcc/config/rs6000/vsx.md | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 003bd534119..cc3bc83ff9b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4089,21 +4089,22 @@
;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b"))]
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], <VEC_base>mode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VEC_base>mode);
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load,fpload")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-04-29 3:31 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-26 15:45 [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be loaded into vector registers Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2023-04-29 3:31 Michael Meissner
2023-04-28 18:30 Michael Meissner
2023-04-28 18:25 Michael Meissner
2023-04-28 3:28 Michael Meissner
2023-04-27 2:57 Michael Meissner
2023-04-25 15:55 Michael Meissner
2023-04-25 6:30 Michael Meissner
2023-04-25 2:18 Michael Meissner
2023-04-25 2:11 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).