[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

[jiawei]

Current epilogue will generate "addi sp,sp,0" redundant instruction.

```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        addi    sp,sp,0
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```

Optimize it by check if adjust equal to zero, remove redundant insn gen.

```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```

Thanks for Kito and Jeff's suggestion, add testcase and fix code format.

jiawei (2):
  RISC-V: Add spill sp adjust check testcase.
  RISC-V: Optimize RVV epilogue logic.

 gcc/config/riscv/riscv.cc                     | 35 ++++++++++---------
 .../riscv/rvv/base/spill-sp-adjust.c          | 13 +++++++
 2 files changed, 32 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

-- 
2.25.1

[PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.

[jiawei]

This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

---
 .../gcc.target/riscv/rvv/base/spill-sp-adjust.c     | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 00000000000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)v; 
+}
+
+/* Make sure we do not have a useless SP adjustment.  */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */
-- 
2.25.1

Re: [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.

[Jeff Law]

On 11/15/22 01:33, jiawei wrote:
> This testcase mix exist spill-1.c and adding new fun to check if
> there have redundant addi intructions. Idea provided by Jeff Law.
>
> gcc/testsuite/ChangeLog:
>
>          * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

I made several whitespace/formatting fixes to the riscv.cc part of this 
series, improved the Changelog and and committed it for you.


Thanks,

Jeff

[PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic.

[jiawei]

Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction 
"addi sp,sp,0". Add checking segement to skip that case.

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_expand_epilogue): 
						New check segement.

---
 gcc/config/riscv/riscv.cc | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..433b9b13eb6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5185,25 +5185,28 @@ riscv_expand_epilogue (int style)
 	  step1 -= scalable_frame;
 	}
 
-      /* Get an rtx for STEP1 that we can add to BASE.  */
-      rtx adjust = GEN_INT (step1.to_constant ());
-      if (!SMALL_OPERAND (step1.to_constant ()))
-	{
-	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
-	  adjust = RISCV_PROLOGUE_TEMP (Pmode);
-	}
-
-      insn = emit_insn (
-	       gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
-
-      rtx dwarf = NULL_RTX;
-      rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+      /* Get an rtx for STEP1 that we can add to BASE.  
+         Skip if adjust equal to zero.  */
+      if (step1.to_constant () != 0)
+      {
+	 rtx adjust = GEN_INT (step1.to_constant ());
+	 if (!SMALL_OPERAND (step1.to_constant ()))
+	 {
+	   riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
+	   adjust = RISCV_PROLOGUE_TEMP (Pmode);
+	 }
+
+	 insn = emit_insn (
+		gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
+	 rtx dwarf = NULL_RTX;
+	 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
 					 GEN_INT (step2));
 
-      dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
-      RTX_FRAME_RELATED_P (insn) = 1;
+	 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+	 RTX_FRAME_RELATED_P (insn) = 1;
 
-      REG_NOTES (insn) = dwarf;
+	 REG_NOTES (insn) = dwarf;
+     }
     }
   else if (frame_pointer_needed)
     {
-- 
2.25.1

Re: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 1322 bytes --]

LGTM. Thanks for fixing my mistake. 
Let's see whether other RISC-V folks are happy with this patch.



juzhe.zhong@rivai.ai
 
From: jiawei
Date: 2022-11-15 16:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; jeffreyalaw; christoph.muellner; philipp.tomsich; wuwei2016; jiawei
Subject: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Current epilogue will generate "addi sp,sp,0" redundant instruction.
 
```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        addi    sp,sp,0
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```
 
Optimize it by check if adjust equal to zero, remove redundant insn gen.
 
```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```
 
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
 
jiawei (2):
  RISC-V: Add spill sp adjust check testcase.
  RISC-V: Optimize RVV epilogue logic.
 
gcc/config/riscv/riscv.cc                     | 35 ++++++++++---------
.../riscv/rvv/base/spill-sp-adjust.c          | 13 +++++++
2 files changed, 32 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
 
-- 
2.25.1