[PATCH] RISCV: Add vector psabi checking.

[PATCH] RISCV: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_scalable_vector_type_p):
	(riscv_arg_has_vector):
	(riscv_pass_in_vector_p):
	(riscv_get_arg_info):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv.cc                     | 73 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 ++++
 6 files changed, 146 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..06e9fe7d924 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3728,6 +3728,76 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3812,6 +3882,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
 	}
     }
 
+  /* Only check existing of vector type.  */
+  riscv_pass_in_vector_p (type);
+
   /* Work out the size of the argument.  */
   num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
   num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..114ee6de483
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..fd4569535cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..844a5db4027
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..a5dc2dffaac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..1fe83c8fc87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
-- 
2.39.2

Re: [PATCH] RISCV: Add vector psabi checking.

[Kito Cheng]

> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_scalable_vector_type_p):
>         (riscv_arg_has_vector):
>         (riscv_pass_in_vector_p):
>         (riscv_get_arg_info):

You need to write something for changelog...:P

[PATCH v2] RISCV: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

gcc/ChangeLog:

	* config/riscv/riscv.cc:
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_get_arg_info): Add the checking.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv.cc                     | 73 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 ++++
 6 files changed, 146 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..06e9fe7d924 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3728,6 +3728,76 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3812,6 +3882,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
 	}
     }
 
+  /* Only check existing of vector type.  */
+  riscv_pass_in_vector_p (type);
+
   /* Work out the size of the argument.  */
   num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
   num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..114ee6de483
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..fd4569535cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..844a5db4027
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..a5dc2dffaac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..1fe83c8fc87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
-- 
2.40.0

[PATCH v3] RISCV: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

gcc/ChangeLog:

	* config/riscv/riscv.cc:
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_get_arg_info): Add the checking.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv.cc                     | 73 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 ++++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 ++++
 6 files changed, 146 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..06e9fe7d924 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3728,6 +3728,76 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3812,6 +3882,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
 	}
     }
 
+  /* Only check existing of vector type.  */
+  riscv_pass_in_vector_p (type);
+
   /* Work out the size of the argument.  */
   num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
   num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..b752760b76f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
-- 
2.40.0

Re: [PATCH v3] RISCV: Add vector psabi checking.

[Kito Cheng]

Ooops, I found that it also warns on intrinsic functions, could you
try to find some way to exclude that?

e.g.
#include "riscv_vector.h"

void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
size_t n, int cond) {

 size_t vl;
 if (cond)
   vl = __riscv_vsetvlmax_e32m1();
 else
   vl = __riscv_vsetvlmax_e16mf2();
 for (size_t i = 0; i < n; i += 1) {
   vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); // warning: ABI for
the scalable vector type is currently in experimental stage and may
changes in the upcoming version of GCC. [-Wpsabi]
   vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
   vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
   __riscv_vse32_v_i32m1(out, c, vl);

}
}

On Thu, Apr 27, 2023 at 11:13 AM yanzhang.wang--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Yanzhang Wang <yanzhang.wang@intel.com>
>
> This patch adds support to check function's argument or return is vector type
> and throw warning if yes.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc:
>         (riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
>         (riscv_arg_has_vector): Determine whether the arg is vector type.
>         (riscv_pass_in_vector_p): Check the vector type param is passed by value.
>         (riscv_get_arg_info): Add the checking.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/vector-abi-1.c: New test.
>         * gcc.target/riscv/vector-abi-2.c: New test.
>         * gcc.target/riscv/vector-abi-3.c: New test.
>         * gcc.target/riscv/vector-abi-4.c: New test.
>         * gcc.target/riscv/vector-abi-5.c: New test.
>
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  gcc/config/riscv/riscv.cc                     | 73 +++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 ++++
>  gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 ++++
>  gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 ++++
>  gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 ++++
>  gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 ++++
>  6 files changed, 146 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 76eee4a55e9..06e9fe7d924 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3728,6 +3728,76 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
>                                    GEN_INT (offset2))));
>  }
>
> +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
> +   intrinsic vector type.  Because we can't get the decl for the params.  */
> +
> +static bool
> +riscv_scalable_vector_type_p (const_tree type)
> +{
> +  tree size = TYPE_SIZE (type);
> +  if (size && TREE_CODE (size) == INTEGER_CST)
> +    return false;
> +
> +  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
> +  return true;
> +}
> +
> +static bool
> +riscv_arg_has_vector (const_tree type)
> +{
> +  bool is_vector = false;
> +
> +  switch (TREE_CODE (type))
> +    {
> +    case RECORD_TYPE:
> +      if (!COMPLETE_TYPE_P (type))
> +       break;
> +
> +      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
> +       if (TREE_CODE (f) == FIELD_DECL)
> +         {
> +           tree field_type = TREE_TYPE (f);
> +           if (!TYPE_P (field_type))
> +             break;
> +
> +           /* Ignore it if it's fixed length vector.  */
> +           if (VECTOR_TYPE_P (field_type))
> +             is_vector = riscv_scalable_vector_type_p (field_type);
> +           else
> +             is_vector = riscv_arg_has_vector (field_type);
> +         }
> +
> +      break;
> +
> +    case VECTOR_TYPE:
> +      is_vector = riscv_scalable_vector_type_p (type);
> +      break;
> +
> +    default:
> +      is_vector = false;
> +      break;
> +    }
> +
> +  return is_vector;
> +}
> +
> +/* Pass the type to check whether it's a vector type or contains vector type.
> +   Only check the value type and no checking for vector pointer type.  */
> +
> +static void
> +riscv_pass_in_vector_p (const_tree type)
> +{
> +  static int warned = 0;
> +
> +  if (type && riscv_arg_has_vector (type) && !warned)
> +    {
> +      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
> +              "experimental stage and may changes in the upcoming version of "
> +              "GCC.");
> +      warned = 1;
> +    }
> +}
> +
>  /* Fill INFO with information about a single argument, and return an
>     RTL pattern to pass or return the argument.  CUM is the cumulative
>     state for earlier arguments.  MODE is the mode of this argument and
> @@ -3812,6 +3882,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
>         }
>      }
>
> +  /* Only check existing of vector type.  */
> +  riscv_pass_in_vector_p (type);
> +
>    /* Work out the size of the argument.  */
>    num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
>    num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> new file mode 100644
> index 00000000000..969f14277a4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +void
> +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> new file mode 100644
> index 00000000000..b752760b76f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t
> +fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> new file mode 100644
> index 00000000000..90ece60cc6f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t*
> +fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> new file mode 100644
> index 00000000000..ecf6d4cc26b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef int v4si __attribute__ ((vector_size (16)));
> +
> +v4si
> +fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  v4si a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> new file mode 100644
> index 00000000000..6053e0783b6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +typedef int v4si __attribute__ ((vector_size (16)));
> +struct A { int a; v4si b; };
> +
> +void
> +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  struct A a;
> +  fun (a);
> +}
> --
> 2.40.0
>

[PATCH v4] RISC-V: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

There're two exceptions,
  - The vector_size attribute.
  - The intrinsic functions.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
	  warning flag if func is not builtin
	* config/riscv/riscv.cc
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_init_cumulative_args): The same as header.
	(riscv_get_arg_info): Add the checking.
	(riscv_function_value): Check the func return and set warning flag
	* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
	  determine whether warning psabi or not.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.
	* gcc.target/riscv/vector-abi-6.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
 gcc/config/riscv/riscv.h                      |   5 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
 9 files changed, 211 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e41f65a0894..d8f42778565 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -235,4 +235,6 @@ extern const char*
 th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
 #endif
 
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..3286656ecba 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3728,6 +3728,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+			    tree fntype,
+			    rtx libname,
+			    tree fndecl,
+			    int caller)
+{
+  memset (cum, 0, sizeof (*cum));
+
+  if (fndecl)
+    {
+      const tree_function_decl &fn
+	= FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+      if (fn.built_in_class == NOT_BUILT_IN)
+	  cum->rvv_psabi_warning = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3812,6 +3905,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
 	}
     }
 
+  if (cum->rvv_psabi_warning)
+    {
+      /* Only check existing of vector type.  */
+      riscv_pass_in_vector_p (type);
+    }
+
   /* Work out the size of the argument.  */
   num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
   num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
@@ -3899,7 +3998,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
     }
 
   memset (&args, 0, sizeof args);
-  return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+  const_tree arg_type = type;
+  if (func && DECL_RESULT (func))
+    {
+      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+      if (fn.built_in_class == NOT_BUILT_IN)
+	args.rvv_psabi_warning = 1;
+
+      arg_type = TREE_TYPE (DECL_RESULT (func));
+    }
+
+  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
 }
 
 /* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..cb10b63ef10 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -671,6 +671,8 @@ typedef struct {
 
   /* Number of floating-point registers used so far, likewise.  */
   unsigned int num_fprs;
+
+  int rvv_psabi_warning;
 } CUMULATIVE_ARGS;
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -678,7 +680,8 @@ typedef struct {
    For a library call, FNTYPE is 0.  */
 
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
-  memset (&(CUM), 0, sizeof (CUM))
+  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
+			(N_NAMED_ARGS) != -1)
 
 #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
 
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..63d97d30fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644
index 00000000000..63bc4a89805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+    size_t n, int cond) {
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2();
+  for (size_t i = 0; i < n; i += 1)
+    {
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+      __riscv_vse32_v_i32m1(out, c, vl);
+    }
+}
-- 
2.40.1

Re: [PATCH v4] RISC-V: Add vector psabi checking.

[Kito Cheng]

Hmmm, I still saw some fail on testsuite after applying this patch,
most are because the testcase has used vector type as argument or
return value, but .. vector-abi-1.c should not fail I think?

For other fails, I would suggest you could just add -Wno-psabi to rvv.exp

                === gcc: Unexpected fails for rv64imafdcv lp64d medlow ===
FAIL: gcc.target/riscv/vector-abi-1.c   -O0   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c   -O1   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c   -O2   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c   -O2 -flto
-fno-use-linker-plugin -flto-partition=none   (test for warnings, line
7)
FAIL: gcc.target/riscv/vector-abi-1.c   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c   -O3 -g   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c   -Os   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c  -Og -g   (test for warnings, line 7)
FAIL: gcc.target/riscv/vector-abi-1.c  -Oz   (test for warnings, line 7)
FAIL: gcc.target/riscv/rvv/base/binop_vx_constraint-120.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c (test
for excess errors)
FAIL: gcc.target/riscv/rvv/base/mask_insn_shortcut.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c (test
for excess errors)
FAIL: gcc.target/riscv/rvv/base/pr110109-2.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/scalar_move-9.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/vlmul_ext-1.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
(test for excess errors)
FAIL: gcc.target/riscv/rvv/base/zvfh-intrinsic.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c (test for excess errors)

              ========= Summary of gcc testsuite =========
                           | # of unexpected case / # of unique unexpected case
                           |          gcc |          g++ |     gfortran |
rv32imafdc/ ilp32d/ medlow |   20 /    12 |    0 /     0 |    0 /     0 |
rv32imafdcv/ ilp32d/ medlow |   25 /    14 |   22 /    22 |    0 /     0 |
rv64imafdc/  lp64d/ medlow |   20 /    12 |    0 /     0 |    0 /     0 |
rv64imafdcv/  lp64d/ medlow |   20 /    12 |   21 /    21 |    0 /     0 |

On Fri, Jun 9, 2023 at 2:02 PM yanzhang.wang--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Yanzhang Wang <yanzhang.wang@intel.com>
>
> This patch adds support to check function's argument or return is vector type
> and throw warning if yes.
>
> There're two exceptions,
>   - The vector_size attribute.
>   - The intrinsic functions.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
>           warning flag if func is not builtin
>         * config/riscv/riscv.cc
>         (riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
>         (riscv_arg_has_vector): Determine whether the arg is vector type.
>         (riscv_pass_in_vector_p): Check the vector type param is passed by value.
>         (riscv_init_cumulative_args): The same as header.
>         (riscv_get_arg_info): Add the checking.
>         (riscv_function_value): Check the func return and set warning flag
>         * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
>           determine whether warning psabi or not.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/vector-abi-1.c: New test.
>         * gcc.target/riscv/vector-abi-2.c: New test.
>         * gcc.target/riscv/vector-abi-3.c: New test.
>         * gcc.target/riscv/vector-abi-4.c: New test.
>         * gcc.target/riscv/vector-abi-5.c: New test.
>         * gcc.target/riscv/vector-abi-6.c: New test.
>
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  gcc/config/riscv/riscv-protos.h               |   2 +
>  gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
>  gcc/config/riscv/riscv.h                      |   5 +-
>  gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
>  gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
>  gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
>  gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
>  gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
>  gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
>  9 files changed, 211 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index e41f65a0894..d8f42778565 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -235,4 +235,6 @@ extern const char*
>  th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
>  #endif
>
> +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
> +
>  #endif /* ! GCC_RISCV_PROTOS_H */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 76eee4a55e9..3286656ecba 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3728,6 +3728,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
>                                    GEN_INT (offset2))));
>  }
>
> +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
> +   intrinsic vector type.  Because we can't get the decl for the params.  */
> +
> +static bool
> +riscv_scalable_vector_type_p (const_tree type)
> +{
> +  tree size = TYPE_SIZE (type);
> +  if (size && TREE_CODE (size) == INTEGER_CST)
> +    return false;
> +
> +  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
> +  return true;
> +}
> +
> +static bool
> +riscv_arg_has_vector (const_tree type)
> +{
> +  bool is_vector = false;
> +
> +  switch (TREE_CODE (type))
> +    {
> +    case RECORD_TYPE:
> +      if (!COMPLETE_TYPE_P (type))
> +       break;
> +
> +      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
> +       if (TREE_CODE (f) == FIELD_DECL)
> +         {
> +           tree field_type = TREE_TYPE (f);
> +           if (!TYPE_P (field_type))
> +             break;
> +
> +           /* Ignore it if it's fixed length vector.  */
> +           if (VECTOR_TYPE_P (field_type))
> +             is_vector = riscv_scalable_vector_type_p (field_type);
> +           else
> +             is_vector = riscv_arg_has_vector (field_type);
> +         }
> +
> +      break;
> +
> +    case VECTOR_TYPE:
> +      is_vector = riscv_scalable_vector_type_p (type);
> +      break;
> +
> +    default:
> +      is_vector = false;
> +      break;
> +    }
> +
> +  return is_vector;
> +}
> +
> +/* Pass the type to check whether it's a vector type or contains vector type.
> +   Only check the value type and no checking for vector pointer type.  */
> +
> +static void
> +riscv_pass_in_vector_p (const_tree type)
> +{
> +  static int warned = 0;
> +
> +  if (type && riscv_arg_has_vector (type) && !warned)
> +    {
> +      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
> +              "experimental stage and may changes in the upcoming version of "
> +              "GCC.");
> +      warned = 1;
> +    }
> +}
> +
> +/* Initialize a variable CUM of type CUMULATIVE_ARGS
> +   for a call to a function whose data type is FNTYPE.
> +   For a library call, FNTYPE is 0.  */
> +
> +void
> +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
> +                           tree fntype,
> +                           rtx libname,
> +                           tree fndecl,
> +                           int caller)
> +{
> +  memset (cum, 0, sizeof (*cum));
> +
> +  if (fndecl)
> +    {
> +      const tree_function_decl &fn
> +       = FUNCTION_DECL_CHECK (fndecl)->function_decl;
> +
> +      if (fn.built_in_class == NOT_BUILT_IN)
> +         cum->rvv_psabi_warning = 1;
> +    }
> +}
> +
>  /* Fill INFO with information about a single argument, and return an
>     RTL pattern to pass or return the argument.  CUM is the cumulative
>     state for earlier arguments.  MODE is the mode of this argument and
> @@ -3812,6 +3905,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
>         }
>      }
>
> +  if (cum->rvv_psabi_warning)
> +    {
> +      /* Only check existing of vector type.  */
> +      riscv_pass_in_vector_p (type);
> +    }
> +
>    /* Work out the size of the argument.  */
>    num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
>    num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
> @@ -3899,7 +3998,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
>      }
>
>    memset (&args, 0, sizeof args);
> -  return riscv_get_arg_info (&info, &args, mode, type, true, true);
> +
> +  const_tree arg_type = type;
> +  if (func && DECL_RESULT (func))
> +    {
> +      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
> +      if (fn.built_in_class == NOT_BUILT_IN)
> +       args.rvv_psabi_warning = 1;
> +
> +      arg_type = TREE_TYPE (DECL_RESULT (func));
> +    }
> +
> +  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
>  }
>
>  /* Implement TARGET_PASS_BY_REFERENCE. */
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 66fb07d6652..cb10b63ef10 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -671,6 +671,8 @@ typedef struct {
>
>    /* Number of floating-point registers used so far, likewise.  */
>    unsigned int num_fprs;
> +
> +  int rvv_psabi_warning;
>  } CUMULATIVE_ARGS;
>
>  /* Initialize a variable CUM of type CUMULATIVE_ARGS
> @@ -678,7 +680,8 @@ typedef struct {
>     For a library call, FNTYPE is 0.  */
>
>  #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
> -  memset (&(CUM), 0, sizeof (CUM))
> +  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
> +                       (N_NAMED_ARGS) != -1)
>
>  #define EPILOGUE_USES(REGNO)   riscv_epilogue_uses (REGNO)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> new file mode 100644
> index 00000000000..969f14277a4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +void
> +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> new file mode 100644
> index 00000000000..63d97d30fc5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t
> +fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> new file mode 100644
> index 00000000000..90ece60cc6f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t*
> +fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> new file mode 100644
> index 00000000000..ecf6d4cc26b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef int v4si __attribute__ ((vector_size (16)));
> +
> +v4si
> +fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  v4si a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> new file mode 100644
> index 00000000000..6053e0783b6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +typedef int v4si __attribute__ ((vector_size (16)));
> +struct A { int a; v4si b; };
> +
> +void
> +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  struct A a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> new file mode 100644
> index 00000000000..63bc4a89805
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +#include "riscv_vector.h"
> +
> +void
> +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
> +    size_t n, int cond) {
> +  size_t vl;
> +  if (cond)
> +    vl = __riscv_vsetvlmax_e32m1();
> +  else
> +    vl = __riscv_vsetvlmax_e16mf2();
> +  for (size_t i = 0; i < n; i += 1)
> +    {
> +      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
> +      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
> +      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
> +      __riscv_vse32_v_i32m1(out, c, vl);
> +    }
> +}
> --
> 2.40.1
>

RE: [PATCH v4] RISC-V: Add vector psabi checking.

[Wang, Yanzhang]

I reproduce the failure too. Because it returns early in get_arg_info for
v-ext mode. I'll move the checking to the beginning.

> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Friday, June 9, 2023 5:52 PM
> To: Wang, Yanzhang <yanzhang.wang@intel.com>
> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com;
> Li, Pan2 <pan2.li@intel.com>
> Subject: Re: [PATCH v4] RISC-V: Add vector psabi checking.
> 
> Hmmm, I still saw some fail on testsuite after applying this patch, most
> are because the testcase has used vector type as argument or return value,
> but .. vector-abi-1.c should not fail I think?
> 
> For other fails, I would suggest you could just add -Wno-psabi to rvv.exp
> 
>                 === gcc: Unexpected fails for rv64imafdcv lp64d medlow ===
> FAIL: gcc.target/riscv/vector-abi-1.c   -O0   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -O1   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -O2   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -O2 -flto
> -fno-use-linker-plugin -flto-partition=none   (test for warnings, line
> 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -O2 -flto -fuse-linker-plugin
> -fno-fat-lto-objects   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -O3 -g   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c   -Os   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c  -Og -g   (test for warnings, line 7)
> FAIL: gcc.target/riscv/vector-abi-1.c  -Oz   (test for warnings, line 7)
> FAIL: gcc.target/riscv/rvv/base/binop_vx_constraint-120.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c (test for
> excess errors)
> FAIL: gcc.target/riscv/rvv/base/mask_insn_shortcut.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c (test for
> excess errors)
> FAIL: gcc.target/riscv/rvv/base/pr110109-2.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/scalar_move-9.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/vlmul_ext-1.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/zvfh-intrinsic.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c (test for excess errors)
> 
>               ========= Summary of gcc testsuite =========
>                            | # of unexpected case / # of unique unexpected
> case
>                            |          gcc |          g++ |     gfortran |
> rv32imafdc/ ilp32d/ medlow |   20 /    12 |    0 /     0 |    0 /     0 |
> rv32imafdcv/ ilp32d/ medlow |   25 /    14 |   22 /    22 |    0 /     0 |
> rv64imafdc/  lp64d/ medlow |   20 /    12 |    0 /     0 |    0 /     0 |
> rv64imafdcv/  lp64d/ medlow |   20 /    12 |   21 /    21 |    0 /     0 |
> 
> On Fri, Jun 9, 2023 at 2:02 PM yanzhang.wang--- via Gcc-patches <gcc-
> patches@gcc.gnu.org> wrote:
> >
> > From: Yanzhang Wang <yanzhang.wang@intel.com>
> >
> > This patch adds support to check function's argument or return is
> > vector type and throw warning if yes.
> >
> > There're two exceptions,
> >   - The vector_size attribute.
> >   - The intrinsic functions.
> >
> > gcc/ChangeLog:
> >
> >         * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
> >           warning flag if func is not builtin
> >         * config/riscv/riscv.cc
> >         (riscv_scalable_vector_type_p): Determine whether the type is
> scalable vector.
> >         (riscv_arg_has_vector): Determine whether the arg is vector type.
> >         (riscv_pass_in_vector_p): Check the vector type param is passed
> by value.
> >         (riscv_init_cumulative_args): The same as header.
> >         (riscv_get_arg_info): Add the checking.
> >         (riscv_function_value): Check the func return and set warning
> flag
> >         * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
> >           determine whether warning psabi or not.
> >
> > gcc/testsuite/ChangeLog:
> >
> >         * gcc.target/riscv/vector-abi-1.c: New test.
> >         * gcc.target/riscv/vector-abi-2.c: New test.
> >         * gcc.target/riscv/vector-abi-3.c: New test.
> >         * gcc.target/riscv/vector-abi-4.c: New test.
> >         * gcc.target/riscv/vector-abi-5.c: New test.
> >         * gcc.target/riscv/vector-abi-6.c: New test.
> >
> > Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> > Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> > ---
> >  gcc/config/riscv/riscv-protos.h               |   2 +
> >  gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
> >  gcc/config/riscv/riscv.h                      |   5 +-
> >  gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
> > gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
> > gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
> > gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
> > gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
> > gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
> >  9 files changed, 211 insertions(+), 2 deletions(-)  create mode
> > 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h
> > b/gcc/config/riscv/riscv-protos.h index e41f65a0894..d8f42778565
> > 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -235,4 +235,6 @@ extern const char*  th_mempair_output_move
> > (rtx[4], bool, machine_mode, RTX_CODE);  #endif
> >
> > +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
> > +int);
> > +
> >  #endif /* ! GCC_RISCV_PROTOS_H */
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 76eee4a55e9..3286656ecba 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -3728,6 +3728,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned
> regno1,
> >                                    GEN_INT (offset2))));  }
> >
> > +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute
> and
> > +   intrinsic vector type.  Because we can't get the decl for the
> > +params.  */
> > +
> > +static bool
> > +riscv_scalable_vector_type_p (const_tree type) {
> > +  tree size = TYPE_SIZE (type);
> > +  if (size && TREE_CODE (size) == INTEGER_CST)
> > +    return false;
> > +
> > +  /* For the data type like vint32m1_t, the size code is
> > +POLY_INT_CST.  */
> > +  return true;
> > +}
> > +
> > +static bool
> > +riscv_arg_has_vector (const_tree type) {
> > +  bool is_vector = false;
> > +
> > +  switch (TREE_CODE (type))
> > +    {
> > +    case RECORD_TYPE:
> > +      if (!COMPLETE_TYPE_P (type))
> > +       break;
> > +
> > +      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
> > +       if (TREE_CODE (f) == FIELD_DECL)
> > +         {
> > +           tree field_type = TREE_TYPE (f);
> > +           if (!TYPE_P (field_type))
> > +             break;
> > +
> > +           /* Ignore it if it's fixed length vector.  */
> > +           if (VECTOR_TYPE_P (field_type))
> > +             is_vector = riscv_scalable_vector_type_p (field_type);
> > +           else
> > +             is_vector = riscv_arg_has_vector (field_type);
> > +         }
> > +
> > +      break;
> > +
> > +    case VECTOR_TYPE:
> > +      is_vector = riscv_scalable_vector_type_p (type);
> > +      break;
> > +
> > +    default:
> > +      is_vector = false;
> > +      break;
> > +    }
> > +
> > +  return is_vector;
> > +}
> > +
> > +/* Pass the type to check whether it's a vector type or contains vector
> type.
> > +   Only check the value type and no checking for vector pointer type.
> > +*/
> > +
> > +static void
> > +riscv_pass_in_vector_p (const_tree type) {
> > +  static int warned = 0;
> > +
> > +  if (type && riscv_arg_has_vector (type) && !warned)
> > +    {
> > +      warning (OPT_Wpsabi, "ABI for the scalable vector type is
> currently in "
> > +              "experimental stage and may changes in the upcoming
> version of "
> > +              "GCC.");
> > +      warned = 1;
> > +    }
> > +}
> > +
> > +/* Initialize a variable CUM of type CUMULATIVE_ARGS
> > +   for a call to a function whose data type is FNTYPE.
> > +   For a library call, FNTYPE is 0.  */
> > +
> > +void
> > +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
> > +                           tree fntype,
> > +                           rtx libname,
> > +                           tree fndecl,
> > +                           int caller) {
> > +  memset (cum, 0, sizeof (*cum));
> > +
> > +  if (fndecl)
> > +    {
> > +      const tree_function_decl &fn
> > +       = FUNCTION_DECL_CHECK (fndecl)->function_decl;
> > +
> > +      if (fn.built_in_class == NOT_BUILT_IN)
> > +         cum->rvv_psabi_warning = 1;
> > +    }
> > +}
> > +
> >  /* Fill INFO with information about a single argument, and return an
> >     RTL pattern to pass or return the argument.  CUM is the cumulative
> >     state for earlier arguments.  MODE is the mode of this argument
> > and @@ -3812,6 +3905,12 @@ riscv_get_arg_info (struct riscv_arg_info
> *info, const CUMULATIVE_ARGS *cum,
> >         }
> >      }
> >
> > +  if (cum->rvv_psabi_warning)
> > +    {
> > +      /* Only check existing of vector type.  */
> > +      riscv_pass_in_vector_p (type);
> > +    }
> > +
> >    /* Work out the size of the argument.  */
> >    num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE
> (mode).to_constant ();
> >    num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; @@
> > -3899,7 +3998,18 @@ riscv_function_value (const_tree type, const_tree
> func, machine_mode mode)
> >      }
> >
> >    memset (&args, 0, sizeof args);
> > -  return riscv_get_arg_info (&info, &args, mode, type, true, true);
> > +
> > +  const_tree arg_type = type;
> > +  if (func && DECL_RESULT (func))
> > +    {
> > +      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)-
> >function_decl;
> > +      if (fn.built_in_class == NOT_BUILT_IN)
> > +       args.rvv_psabi_warning = 1;
> > +
> > +      arg_type = TREE_TYPE (DECL_RESULT (func));
> > +    }
> > +
> > +  return riscv_get_arg_info (&info, &args, mode, arg_type, true,
> > + true);
> >  }
> >
> >  /* Implement TARGET_PASS_BY_REFERENCE. */ diff --git
> > a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index
> > 66fb07d6652..cb10b63ef10 100644
> > --- a/gcc/config/riscv/riscv.h
> > +++ b/gcc/config/riscv/riscv.h
> > @@ -671,6 +671,8 @@ typedef struct {
> >
> >    /* Number of floating-point registers used so far, likewise.  */
> >    unsigned int num_fprs;
> > +
> > +  int rvv_psabi_warning;
> >  } CUMULATIVE_ARGS;
> >
> >  /* Initialize a variable CUM of type CUMULATIVE_ARGS @@ -678,7 +680,8
> > @@ typedef struct {
> >     For a library call, FNTYPE is 0.  */
> >
> >  #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT,
> > N_NAMED_ARGS) \
> > -  memset (&(CUM), 0, sizeof (CUM))
> > +  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),
> \
> > +                       (N_NAMED_ARGS) != -1)
> >
> >  #define EPILOGUE_USES(REGNO)   riscv_epilogue_uses (REGNO)
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> > new file mode 100644
> > index 00000000000..969f14277a4
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> > @@ -0,0 +1,14 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
> > +
> > +#include "riscv_vector.h"
> > +
> > +void
> > +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" }
> > +*/
> > +
> > +void
> > +bar ()
> > +{
> > +  vint32m1_t a;
> > +  fun (a);
> > +}
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> > new file mode 100644
> > index 00000000000..63d97d30fc5
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> > @@ -0,0 +1,15 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> > +/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
> > +
> > +#include "riscv_vector.h"
> > +
> > +vint32m1_t
> > +fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable
> > +vector type" } */
> > +
> > +void
> > +bar ()
> > +{
> > +  vint32m1_t a;
> > +  fun (&a);
> > +}
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> > new file mode 100644
> > index 00000000000..90ece60cc6f
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> > @@ -0,0 +1,14 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> > +
> > +#include "riscv_vector.h"
> > +
> > +vint32m1_t*
> > +fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable
> > +vector type" } */
> > +
> > +void
> > +bar ()
> > +{
> > +  vint32m1_t a;
> > +  fun (&a);
> > +}
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> > new file mode 100644
> > index 00000000000..ecf6d4cc26b
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> > @@ -0,0 +1,16 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> > +
> > +#include "riscv_vector.h"
> > +
> > +typedef int v4si __attribute__ ((vector_size (16)));
> > +
> > +v4si
> > +fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type"
> > +} */
> > +
> > +void
> > +bar ()
> > +{
> > +  v4si a;
> > +  fun (a);
> > +}
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> > new file mode 100644
> > index 00000000000..6053e0783b6
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> > @@ -0,0 +1,15 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> > +
> > +typedef int v4si __attribute__ ((vector_size (16))); struct A { int
> > +a; v4si b; };
> > +
> > +void
> > +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
> > +
> > +void
> > +bar ()
> > +{
> > +  struct A a;
> > +  fun (a);
> > +}
> > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> > b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> > new file mode 100644
> > index 00000000000..63bc4a89805
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> > @@ -0,0 +1,20 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ #include
> > +"riscv_vector.h"
> > +
> > +void
> > +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
> > +    size_t n, int cond) {
> > +  size_t vl;
> > +  if (cond)
> > +    vl = __riscv_vsetvlmax_e32m1();
> > +  else
> > +    vl = __riscv_vsetvlmax_e16mf2();
> > +  for (size_t i = 0; i < n; i += 1)
> > +    {
> > +      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the
> scalable vector type" } */
> > +      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
> > +      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
> > +      __riscv_vse32_v_i32m1(out, c, vl);
> > +    }
> > +}
> > --
> > 2.40.1
> >

[PATCH v5] RISC-V: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

There're two exceptions,
  - The vector_size attribute.
  - The intrinsic functions.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
	  warning flag if func is not builtin
	* config/riscv/riscv.cc
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_init_cumulative_args): The same as header.
	(riscv_get_arg_info): Add the checking.
	(riscv_function_value): Check the func return and set warning flag
	* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
	  determine whether warning psabi or not.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Add -Wno-psabi
	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.
	* gcc.target/riscv/vector-abi-6.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
 gcc/config/riscv/riscv.h                      |   5 +-
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |   2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
 10 files changed, 212 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 66c1f535d60..90fde5f8be3 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -302,4 +302,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
 #endif
 
 extern bool riscv_use_divmod_expander (void);
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index de30bf4e567..dd5361c2bd2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+			    tree fntype ATTRIBUTE_UNUSED,
+			    rtx libname ATTRIBUTE_UNUSED,
+			    tree fndecl,
+			    int caller ATTRIBUTE_UNUSED)
+{
+  memset (cum, 0, sizeof (*cum));
+
+  if (fndecl)
+    {
+      const tree_function_decl &fn
+	= FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+      if (fn.built_in_class == NOT_BUILT_IN)
+	  cum->rvv_psabi_warning = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
   info->gpr_offset = cum->num_gprs;
   info->fpr_offset = cum->num_fprs;
 
+  if (cum->rvv_psabi_warning)
+    {
+      /* Only check existing of vector type.  */
+      riscv_pass_in_vector_p (type);
+    }
+
   /* TODO: Currently, it will cause an ICE for --param
      riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
      let GCC generate loads/stores. Ideally, we should either warn the user not
@@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
     }
 
   memset (&args, 0, sizeof args);
-  return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+  const_tree arg_type = type;
+  if (func && DECL_RESULT (func))
+    {
+      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+      if (fn.built_in_class == NOT_BUILT_IN)
+	args.rvv_psabi_warning = 1;
+
+      arg_type = TREE_TYPE (DECL_RESULT (func));
+    }
+
+  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
 }
 
 /* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..bfd9b7551bc 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -677,6 +677,8 @@ typedef struct {
 
   /* Number of floating-point registers used so far, likewise.  */
   unsigned int num_fprs;
+
+  int rvv_psabi_warning;
 } CUMULATIVE_ARGS;
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -684,7 +686,8 @@ typedef struct {
    For a library call, FNTYPE is 0.  */
 
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
-  memset (&(CUM), 0, sizeof (CUM))
+  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
+			(N_NAMED_ARGS) != -1)
 
 #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 5e69235a268..ad79d0e9a8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -43,7 +43,7 @@ dg-init
 # Main loop.
 set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
-	"" $CFLAGS
+	"-Wno-psabi" $CFLAGS
 gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
 	"" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..63d97d30fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644
index 00000000000..63bc4a89805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+    size_t n, int cond) {
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2();
+  for (size_t i = 0; i < n; i += 1)
+    {
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+      __riscv_vse32_v_i32m1(out, c, vl);
+    }
+}
-- 
2.40.1

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Wang, Yanzhang]

I found there're still some test cases that does not pass. I'll push
another version soon. Sorry for the inconvenience.

> -----Original Message-----
> From: Wang, Yanzhang <yanzhang.wang@intel.com>
> Sent: Monday, June 12, 2023 4:08 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2
> <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH v5] RISC-V: Add vector psabi checking.
> 
> From: Yanzhang Wang <yanzhang.wang@intel.com>
> 
> This patch adds support to check function's argument or return is vector
> type and throw warning if yes.
> 
> There're two exceptions,
>   - The vector_size attribute.
>   - The intrinsic functions.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
> 	  warning flag if func is not builtin
> 	* config/riscv/riscv.cc
> 	(riscv_scalable_vector_type_p): Determine whether the type is scalable
> vector.
> 	(riscv_arg_has_vector): Determine whether the arg is vector type.
> 	(riscv_pass_in_vector_p): Check the vector type param is passed by
> value.
> 	(riscv_init_cumulative_args): The same as header.
> 	(riscv_get_arg_info): Add the checking.
> 	(riscv_function_value): Check the func return and set warning flag
> 	* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
> 	  determine whether warning psabi or not.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/rvv/rvv.exp: Add -Wno-psabi
> 	* gcc.target/riscv/vector-abi-1.c: New test.
> 	* gcc.target/riscv/vector-abi-2.c: New test.
> 	* gcc.target/riscv/vector-abi-3.c: New test.
> 	* gcc.target/riscv/vector-abi-4.c: New test.
> 	* gcc.target/riscv/vector-abi-5.c: New test.
> 	* gcc.target/riscv/vector-abi-6.c: New test.
> 
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  gcc/config/riscv/riscv-protos.h               |   2 +
>  gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
>  gcc/config/riscv/riscv.h                      |   5 +-
>  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |   2 +-
>  gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
> gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
> gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
> gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
> gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
> gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
>  10 files changed, 212 insertions(+), 3 deletions(-)  create mode 100644
> gcc/testsuite/gcc.target/riscv/vector-abi-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-
> protos.h index 66c1f535d60..90fde5f8be3 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -302,4 +302,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode,
> RTX_CODE);  #endif
> 
>  extern bool riscv_use_divmod_expander (void);
> +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
> +int);
> +
>  #endif /* ! GCC_RISCV_PROTOS_H */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index
> de30bf4e567..dd5361c2bd2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned
> regno1,
>  				   GEN_INT (offset2))));
>  }
> 
> +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute
> and
> +   intrinsic vector type.  Because we can't get the decl for the
> +params.  */
> +
> +static bool
> +riscv_scalable_vector_type_p (const_tree type) {
> +  tree size = TYPE_SIZE (type);
> +  if (size && TREE_CODE (size) == INTEGER_CST)
> +    return false;
> +
> +  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.
> +*/
> +  return true;
> +}
> +
> +static bool
> +riscv_arg_has_vector (const_tree type)
> +{
> +  bool is_vector = false;
> +
> +  switch (TREE_CODE (type))
> +    {
> +    case RECORD_TYPE:
> +      if (!COMPLETE_TYPE_P (type))
> +	break;
> +
> +      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
> +	if (TREE_CODE (f) == FIELD_DECL)
> +	  {
> +	    tree field_type = TREE_TYPE (f);
> +	    if (!TYPE_P (field_type))
> +	      break;
> +
> +	    /* Ignore it if it's fixed length vector.  */
> +	    if (VECTOR_TYPE_P (field_type))
> +	      is_vector = riscv_scalable_vector_type_p (field_type);
> +	    else
> +	      is_vector = riscv_arg_has_vector (field_type);
> +	  }
> +
> +      break;
> +
> +    case VECTOR_TYPE:
> +      is_vector = riscv_scalable_vector_type_p (type);
> +      break;
> +
> +    default:
> +      is_vector = false;
> +      break;
> +    }
> +
> +  return is_vector;
> +}
> +
> +/* Pass the type to check whether it's a vector type or contains vector
> type.
> +   Only check the value type and no checking for vector pointer type.
> +*/
> +
> +static void
> +riscv_pass_in_vector_p (const_tree type) {
> +  static int warned = 0;
> +
> +  if (type && riscv_arg_has_vector (type) && !warned)
> +    {
> +      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently
> in "
> +	       "experimental stage and may changes in the upcoming version of "
> +	       "GCC.");
> +      warned = 1;
> +    }
> +}
> +
> +/* Initialize a variable CUM of type CUMULATIVE_ARGS
> +   for a call to a function whose data type is FNTYPE.
> +   For a library call, FNTYPE is 0.  */
> +
> +void
> +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
> +			    tree fntype ATTRIBUTE_UNUSED,
> +			    rtx libname ATTRIBUTE_UNUSED,
> +			    tree fndecl,
> +			    int caller ATTRIBUTE_UNUSED)
> +{
> +  memset (cum, 0, sizeof (*cum));
> +
> +  if (fndecl)
> +    {
> +      const tree_function_decl &fn
> +	= FUNCTION_DECL_CHECK (fndecl)->function_decl;
> +
> +      if (fn.built_in_class == NOT_BUILT_IN)
> +	  cum->rvv_psabi_warning = 1;
> +    }
> +}
> +
>  /* Fill INFO with information about a single argument, and return an
>     RTL pattern to pass or return the argument.  CUM is the cumulative
>     state for earlier arguments.  MODE is the mode of this argument and @@
> -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const
> CUMULATIVE_ARGS *cum,
>    info->gpr_offset = cum->num_gprs;
>    info->fpr_offset = cum->num_fprs;
> 
> +  if (cum->rvv_psabi_warning)
> +    {
> +      /* Only check existing of vector type.  */
> +      riscv_pass_in_vector_p (type);
> +    }
> +
>    /* TODO: Currently, it will cause an ICE for --param
>       riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX
> here
>       let GCC generate loads/stores. Ideally, we should either warn the
> user not @@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type,
> const_tree func, machine_mode mode)
>      }
> 
>    memset (&args, 0, sizeof args);
> -  return riscv_get_arg_info (&info, &args, mode, type, true, true);
> +
> +  const_tree arg_type = type;
> +  if (func && DECL_RESULT (func))
> +    {
> +      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)-
> >function_decl;
> +      if (fn.built_in_class == NOT_BUILT_IN)
> +	args.rvv_psabi_warning = 1;
> +
> +      arg_type = TREE_TYPE (DECL_RESULT (func));
> +    }
> +
> +  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
>  }
> 
>  /* Implement TARGET_PASS_BY_REFERENCE. */ diff --git
> a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index
> 4541255a8ae..bfd9b7551bc 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -677,6 +677,8 @@ typedef struct {
> 
>    /* Number of floating-point registers used so far, likewise.  */
>    unsigned int num_fprs;
> +
> +  int rvv_psabi_warning;
>  } CUMULATIVE_ARGS;
> 
>  /* Initialize a variable CUM of type CUMULATIVE_ARGS @@ -684,7 +686,8 @@
> typedef struct {
>     For a library call, FNTYPE is 0.  */
> 
>  #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS)
> \
> -  memset (&(CUM), 0, sizeof (CUM))
> +  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),
> \
> +			(N_NAMED_ARGS) != -1)
> 
>  #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
> 
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -	"" $CFLAGS
> +	"-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]]
> \
>  	"" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> new file mode 100644
> index 00000000000..969f14277a4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +void
> +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> new file mode 100644
> index 00000000000..63d97d30fc5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t
> +fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable
> +vector type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> new file mode 100644
> index 00000000000..90ece60cc6f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +vint32m1_t*
> +fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector
> +type" } */
> +
> +void
> +bar ()
> +{
> +  vint32m1_t a;
> +  fun (&a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> new file mode 100644
> index 00000000000..ecf6d4cc26b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef int v4si __attribute__ ((vector_size (16)));
> +
> +v4si
> +fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" }
> +*/
> +
> +void
> +bar ()
> +{
> +  v4si a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> new file mode 100644
> index 00000000000..6053e0783b6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
> +
> +typedef int v4si __attribute__ ((vector_size (16))); struct A { int a;
> +v4si b; };
> +
> +void
> +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
> +
> +void
> +bar ()
> +{
> +  struct A a;
> +  fun (a);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> new file mode 100644
> index 00000000000..63bc4a89805
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ #include
> +"riscv_vector.h"
> +
> +void
> +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
> +    size_t n, int cond) {
> +  size_t vl;
> +  if (cond)
> +    vl = __riscv_vsetvlmax_e32m1();
> +  else
> +    vl = __riscv_vsetvlmax_e16mf2();
> +  for (size_t i = 0; i < n; i += 1)
> +    {
> +      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the
> scalable vector type" } */
> +      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
> +      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
> +      __riscv_vse32_v_i32m1(out, c, vl);
> +    }
> +}
> --
> 2.40.1

Re: [PATCH v5] RISC-V: Add vector psabi checking.

[Kito Cheng]

Hi Yan-Zhang:

OK with one minor, go ahead IF the regression is clean.

Hi Pan:

Could you help to verify this patch and commit if the regression is clean?

thanks :)

> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"

Add -Wno-psabi here rather than below, and also add it for
g++.target/riscv/rvv/rvv.exp

>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -       "" $CFLAGS
> +       "-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
>         "" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Li, Pan2]

Sure thing, will commit it after all riscv.exp rvv.exp pass.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@sifive.com> 
Sent: Monday, June 12, 2023 8:43 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hi Yan-Zhang:

OK with one minor, go ahead IF the regression is clean.

Hi Pan:

Could you help to verify this patch and commit if the regression is clean?

thanks :)

> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"

Add -Wno-psabi here rather than below, and also add it for
g++.target/riscv/rvv/rvv.exp

>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -       "" $CFLAGS
> +       "-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
>         "" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Wang, Yanzhang]

I found that add the -Wno-psabi to CFLAGS will be overrode by
dg-options. It seems we can only add this option to the third
arg of dg-runtest. Attach the dg-runtest comments,

# dg-runtest -- simple main loop useful to most testsuites
#
# OPTIONS is a set of options to always pass.
# DEFAULT_EXTRA_OPTIONS is a set of options to pass if the testcase
# doesn't specify any (with dg-option).

> -----Original Message-----
> From: Kito Cheng <kito.cheng@sifive.com>
> Sent: Monday, June 12, 2023 8:43 PM
> To: Wang, Yanzhang <yanzhang.wang@intel.com>
> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Li, Pan2
> <pan2.li@intel.com>
> Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
> 
> Hi Yan-Zhang:
> 
> OK with one minor, go ahead IF the regression is clean.
> 
> Hi Pan:
> 
> Could you help to verify this patch and commit if the regression is clean?
> 
> thanks :)
> 
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > index 5e69235a268..ad79d0e9a8d 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > @@ -43,7 +43,7 @@ dg-init
> >  # Main loop.
> >  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
> 
> Add -Wno-psabi here rather than below, and also add it for
> g++.target/riscv/rvv/rvv.exp
> 
> >  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> > -       "" $CFLAGS
> > +       "-Wno-psabi" $CFLAGS
> >  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]]
> \
> >         "" $CFLAGS
> >  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

Re: [PATCH v5] RISC-V: Add vector psabi checking.

[Kito Cheng]

How about appending to DEFAULT_CFLAGS?

On Mon, Jun 12, 2023 at 9:38 PM Wang, Yanzhang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> I found that add the -Wno-psabi to CFLAGS will be overrode by
> dg-options. It seems we can only add this option to the third
> arg of dg-runtest. Attach the dg-runtest comments,
>
> # dg-runtest -- simple main loop useful to most testsuites
> #
> # OPTIONS is a set of options to always pass.
> # DEFAULT_EXTRA_OPTIONS is a set of options to pass if the testcase
> # doesn't specify any (with dg-option).
>
> > -----Original Message-----
> > From: Kito Cheng <kito.cheng@sifive.com>
> > Sent: Monday, June 12, 2023 8:43 PM
> > To: Wang, Yanzhang <yanzhang.wang@intel.com>
> > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Li, Pan2
> > <pan2.li@intel.com>
> > Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
> >
> > Hi Yan-Zhang:
> >
> > OK with one minor, go ahead IF the regression is clean.
> >
> > Hi Pan:
> >
> > Could you help to verify this patch and commit if the regression is clean?
> >
> > thanks :)
> >
> > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > index 5e69235a268..ad79d0e9a8d 100644
> > > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > @@ -43,7 +43,7 @@ dg-init
> > >  # Main loop.
> > >  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
> >
> > Add -Wno-psabi here rather than below, and also add it for
> > g++.target/riscv/rvv/rvv.exp
> >
> > >  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> > > -       "" $CFLAGS
> > > +       "-Wno-psabi" $CFLAGS
> > >  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]]
> > \
> > >         "" $CFLAGS
> > >  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Wang, Yanzhang]

It's the same behavior. Because the DEFAULT_CFLAGS will be copied to
CFLAGS and then passed as the DEFAULT_EXTRA_OPTIONS to dg-runtest.

> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Monday, June 12, 2023 10:08 PM
> To: Wang, Yanzhang <yanzhang.wang@intel.com>
> Cc: Kito Cheng <kito.cheng@sifive.com>; gcc-patches@gcc.gnu.org;
> juzhe.zhong@rivai.ai; Li, Pan2 <pan2.li@intel.com>
> Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
> 
> How about appending to DEFAULT_CFLAGS?
> 
> On Mon, Jun 12, 2023 at 9:38 PM Wang, Yanzhang via Gcc-patches <gcc-
> patches@gcc.gnu.org> wrote:
> >
> > I found that add the -Wno-psabi to CFLAGS will be overrode by
> > dg-options. It seems we can only add this option to the third arg of
> > dg-runtest. Attach the dg-runtest comments,
> >
> > # dg-runtest -- simple main loop useful to most testsuites # # OPTIONS
> > is a set of options to always pass.
> > # DEFAULT_EXTRA_OPTIONS is a set of options to pass if the testcase #
> > doesn't specify any (with dg-option).
> >
> > > -----Original Message-----
> > > From: Kito Cheng <kito.cheng@sifive.com>
> > > Sent: Monday, June 12, 2023 8:43 PM
> > > To: Wang, Yanzhang <yanzhang.wang@intel.com>
> > > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Li, Pan2
> > > <pan2.li@intel.com>
> > > Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
> > >
> > > Hi Yan-Zhang:
> > >
> > > OK with one minor, go ahead IF the regression is clean.
> > >
> > > Hi Pan:
> > >
> > > Could you help to verify this patch and commit if the regression is
> clean?
> > >
> > > thanks :)
> > >
> > > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > > index 5e69235a268..ad79d0e9a8d 100644
> > > > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> > > > @@ -43,7 +43,7 @@ dg-init
> > > >  # Main loop.
> > > >  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
> > >
> > > Add -Wno-psabi here rather than below, and also add it for
> > > g++.target/riscv/rvv/rvv.exp
> > >
> > > >  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]]
> \
> > > > -       "" $CFLAGS
> > > > +       "-Wno-psabi" $CFLAGS
> > > >  gcc-dg-runtest [lsort [glob -nocomplain
> > > > $srcdir/$subdir/vsetvl/*.\[cS\]]]
> > > \
> > > >         "" $CFLAGS
> > > >  dg-runtest [lsort [glob -nocomplain
> > > > $srcdir/$subdir/autovec/*.\[cS\]]] \

Re: [PATCH v5] RISC-V: Add vector psabi checking.

[Jeff Law]

On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote:
> I found that add the -Wno-psabi to CFLAGS will be overrode by
> dg-options. It seems we can only add this option to the third
> arg of dg-runtest. Attach the dg-runtest comments,
I think we default to -Wno-psabi to avoid triggering diagnostics in the 
common case where we aren't concerned about such issues.  So not a 
surprise that we'll need to work a bit harder to get it added when we do 
want to check for psabi issues.

jeff

Re: [PATCH v5] RISC-V: Add vector psabi checking.

[Kito Cheng]

Hmmm, yeah, I think let's add it case by case...I assume we should get
it rid before GCC 14, it is mostly used for the transition period
before we settle down the ABI and for GCC 13.

On Mon, Jun 12, 2023 at 10:34 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote:
> > I found that add the -Wno-psabi to CFLAGS will be overrode by
> > dg-options. It seems we can only add this option to the third
> > arg of dg-runtest. Attach the dg-runtest comments,
> I think we default to -Wno-psabi to avoid triggering diagnostics in the
> common case where we aren't concerned about such issues.  So not a
> surprise that we'll need to work a bit harder to get it added when we do
> want to check for psabi issues.
>
> jeff

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Wang, Yanzhang]

I think it's ok to add it to specific cases and will not affect other cases.
There's not so many cases. And we can revert it after the finalization.

> -----Original Message-----
> From: Kito Cheng <kito.cheng@sifive.com>
> Sent: Monday, June 12, 2023 10:53 PM
> To: Jeff Law <jeffreyalaw@gmail.com>
> Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; gcc-patches@gcc.gnu.org;
> juzhe.zhong@rivai.ai; Li, Pan2 <pan2.li@intel.com>
> Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.
> 
> Hmmm, yeah, I think let's add it case by case...I assume we should get it
> rid before GCC 14, it is mostly used for the transition period before we
> settle down the ABI and for GCC 13.
> 
> On Mon, Jun 12, 2023 at 10:34 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
> >
> >
> >
> > On 6/12/23 07:36, Wang, Yanzhang via Gcc-patches wrote:
> > > I found that add the -Wno-psabi to CFLAGS will be overrode by
> > > dg-options. It seems we can only add this option to the third arg of
> > > dg-runtest. Attach the dg-runtest comments,
> > I think we default to -Wno-psabi to avoid triggering diagnostics in
> > the common case where we aren't concerned about such issues.  So not a
> > surprise that we'll need to work a bit harder to get it added when we
> > do want to check for psabi issues.
> >
> > jeff

[PATCH v6] RISC-V: Add vector psabi checking.

[yanzhang.wang]

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch adds support to check function's argument or return is vector type
and throw warning if yes.

There're two exceptions,
  - The vector_size attribute.
  - The intrinsic functions.

Some cases that need to add -Wno-psabi to ignore the warning.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
	  warning flag if func is not builtin
	* config/riscv/riscv.cc
	(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
	(riscv_arg_has_vector): Determine whether the arg is vector type.
	(riscv_pass_in_vector_p): Check the vector type param is passed by value.
	(riscv_init_cumulative_args): The same as header.
	(riscv_get_arg_info): Add the checking.
	(riscv_function_value): Check the func return and set warning flag
	* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
	  determine whether warning psabi or not.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/pr109244.C: Add the -Wno-psabi.
	* g++.target/riscv/rvv/base/pr109535.C: Same
	* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Same
	* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c:
	  Same
	* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Same
	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Same
	* gcc.target/riscv/rvv/base/pr110109-2.c: Same
	* gcc.target/riscv/rvv/base/scalar_move-9.c: Same
	* gcc.target/riscv/rvv/base/spill-10.c: Same
	* gcc.target/riscv/rvv/base/spill-11.c: Same
	* gcc.target/riscv/rvv/base/spill-9.c: Same
	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Same
	* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c:
	  Same
	* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Same
	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Same
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Same
	* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Same
	* gcc.target/riscv/vector-abi-1.c: New test.
	* gcc.target/riscv/vector-abi-2.c: New test.
	* gcc.target/riscv/vector-abi-3.c: New test.
	* gcc.target/riscv/vector-abi-4.c: New test.
	* gcc.target/riscv/vector-abi-5.c: New test.
	* gcc.target/riscv/vector-abi-6.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv.cc                     | 112 +++++++++++++++++-
 gcc/config/riscv/riscv.h                      |   5 +-
 .../g++.target/riscv/rvv/base/pr109244.C      |   2 +-
 .../g++.target/riscv/rvv/base/pr109535.C      |   2 +-
 .../riscv/rvv/base/binop_vx_constraint-120.c  |   2 +-
 .../rvv/base/integer_compare_insn_shortcut.c  |   2 +-
 .../riscv/rvv/base/mask_insn_shortcut.c       |   2 +-
 .../rvv/base/misc_vreinterpret_vbool_vint.c   |   2 +-
 .../gcc.target/riscv/rvv/base/pr110109-2.c    |   2 +-
 .../gcc.target/riscv/rvv/base/scalar_move-9.c |   2 +-
 .../gcc.target/riscv/rvv/base/spill-10.c      |   2 +-
 .../gcc.target/riscv/rvv/base/spill-11.c      |   2 +-
 .../gcc.target/riscv/rvv/base/spill-9.c       |   2 +-
 .../gcc.target/riscv/rvv/base/vlmul_ext-1.c   |   2 +-
 .../base/zero_base_load_store_optimization.c  |   2 +-
 .../riscv/rvv/base/zvfh-intrinsic.c           |   2 +-
 .../riscv/rvv/base/zvfh-over-zvfhmin.c        |   2 +-
 .../riscv/rvv/base/zvfhmin-intrinsic.c        |   2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    |   2 +-
 gcc/testsuite/gcc.target/riscv/vector-abi-1.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-2.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-3.c |  14 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-4.c |  16 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-5.c |  15 +++
 gcc/testsuite/gcc.target/riscv/vector-abi-6.c |  20 ++++
 26 files changed, 228 insertions(+), 19 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 66c1f535d60..90fde5f8be3 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -302,4 +302,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
 #endif
 
 extern bool riscv_use_divmod_expander (void);
+void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index de30bf4e567..dd5361c2bd2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
+/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
+   intrinsic vector type.  Because we can't get the decl for the params.  */
+
+static bool
+riscv_scalable_vector_type_p (const_tree type)
+{
+  tree size = TYPE_SIZE (type);
+  if (size && TREE_CODE (size) == INTEGER_CST)
+    return false;
+
+  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
+  return true;
+}
+
+static bool
+riscv_arg_has_vector (const_tree type)
+{
+  bool is_vector = false;
+
+  switch (TREE_CODE (type))
+    {
+    case RECORD_TYPE:
+      if (!COMPLETE_TYPE_P (type))
+	break;
+
+      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
+	if (TREE_CODE (f) == FIELD_DECL)
+	  {
+	    tree field_type = TREE_TYPE (f);
+	    if (!TYPE_P (field_type))
+	      break;
+
+	    /* Ignore it if it's fixed length vector.  */
+	    if (VECTOR_TYPE_P (field_type))
+	      is_vector = riscv_scalable_vector_type_p (field_type);
+	    else
+	      is_vector = riscv_arg_has_vector (field_type);
+	  }
+
+      break;
+
+    case VECTOR_TYPE:
+      is_vector = riscv_scalable_vector_type_p (type);
+      break;
+
+    default:
+      is_vector = false;
+      break;
+    }
+
+  return is_vector;
+}
+
+/* Pass the type to check whether it's a vector type or contains vector type.
+   Only check the value type and no checking for vector pointer type.  */
+
+static void
+riscv_pass_in_vector_p (const_tree type)
+{
+  static int warned = 0;
+
+  if (type && riscv_arg_has_vector (type) && !warned)
+    {
+      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
+	       "experimental stage and may changes in the upcoming version of "
+	       "GCC.");
+      warned = 1;
+    }
+}
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+void
+riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
+			    tree fntype ATTRIBUTE_UNUSED,
+			    rtx libname ATTRIBUTE_UNUSED,
+			    tree fndecl,
+			    int caller ATTRIBUTE_UNUSED)
+{
+  memset (cum, 0, sizeof (*cum));
+
+  if (fndecl)
+    {
+      const tree_function_decl &fn
+	= FUNCTION_DECL_CHECK (fndecl)->function_decl;
+
+      if (fn.built_in_class == NOT_BUILT_IN)
+	  cum->rvv_psabi_warning = 1;
+    }
+}
+
 /* Fill INFO with information about a single argument, and return an
    RTL pattern to pass or return the argument.  CUM is the cumulative
    state for earlier arguments.  MODE is the mode of this argument and
@@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
   info->gpr_offset = cum->num_gprs;
   info->fpr_offset = cum->num_fprs;
 
+  if (cum->rvv_psabi_warning)
+    {
+      /* Only check existing of vector type.  */
+      riscv_pass_in_vector_p (type);
+    }
+
   /* TODO: Currently, it will cause an ICE for --param
      riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
      let GCC generate loads/stores. Ideally, we should either warn the user not
@@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
     }
 
   memset (&args, 0, sizeof args);
-  return riscv_get_arg_info (&info, &args, mode, type, true, true);
+
+  const_tree arg_type = type;
+  if (func && DECL_RESULT (func))
+    {
+      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
+      if (fn.built_in_class == NOT_BUILT_IN)
+	args.rvv_psabi_warning = 1;
+
+      arg_type = TREE_TYPE (DECL_RESULT (func));
+    }
+
+  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
 }
 
 /* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..bfd9b7551bc 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -677,6 +677,8 @@ typedef struct {
 
   /* Number of floating-point registers used so far, likewise.  */
   unsigned int num_fprs;
+
+  int rvv_psabi_warning;
 } CUMULATIVE_ARGS;
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -684,7 +686,8 @@ typedef struct {
    For a library call, FNTYPE is 0.  */
 
 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
-  memset (&(CUM), 0, sizeof (CUM))
+  riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT),     \
+			(N_NAMED_ARGS) != -1)
 
 #define EPILOGUE_USES(REGNO)	riscv_epilogue_uses (REGNO)
 
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
index eebfc239d3a..b0ce04f4921 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */
 typedef int a;
 using c = float;
 template < typename > using e = int;
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
index 7013cfcf4ee..aec613f3f97 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */
 
 typedef long size_t;
 typedef signed char int8_t;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index 809b185dd65..cc373465957 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
 #include "riscv_vector.h"
 
 vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 1bca8467a16..2942e0b2e53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index 57d0241675a..a6df1215c60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 9563c8d27fa..276173d02db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 #include "riscv_vector.h"
 
 vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index e8b5bf8c714..c1df69ace57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 80ee1b5f0c9..9c310bbf590 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index d37857e24ab..89c96c8ef5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index aa2e5e75330..179be1c8c5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index ec673575b4b..5464a297670 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 501d98c5897..51f4fac0a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index fbcfb7b8501..b27e5ccad09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index c951644de4b..0e7c7cdbdd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 2afc105e2da..09b7070b084 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index f1a29b639e0..c899fbfe5dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64 -O3 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index b82e2490815..0e76f676515 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
new file mode 100644
index 00000000000..969f14277a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
new file mode 100644
index 00000000000..63d97d30fc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
new file mode 100644
index 00000000000..90ece60cc6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t*
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  vint32m1_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
new file mode 100644
index 00000000000..ecf6d4cc26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
new file mode 100644
index 00000000000..6053e0783b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+struct A { int a; v4si b; };
+
+void
+fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+
+void
+bar ()
+{
+  struct A a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
new file mode 100644
index 00000000000..63bc4a89805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+#include "riscv_vector.h"
+
+void
+foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
+    size_t n, int cond) {
+  size_t vl;
+  if (cond)
+    vl = __riscv_vsetvlmax_e32m1();
+  else
+    vl = __riscv_vsetvlmax_e16mf2();
+  for (size_t i = 0; i < n; i += 1)
+    {
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
+      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
+      __riscv_vse32_v_i32m1(out, c, vl);
+    }
+}
-- 
2.40.1

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Li, Pan2]

Committed v6 with riscv.exp and rvv.exp passed, thanks Kito.

Pan

-----Original Message-----
From: Li, Pan2 
Sent: Monday, June 12, 2023 8:49 PM
To: Kito Cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai
Subject: RE: [PATCH v5] RISC-V: Add vector psabi checking.

Sure thing, will commit it after all riscv.exp rvv.exp pass.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@sifive.com> 
Sent: Monday, June 12, 2023 8:43 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hi Yan-Zhang:

OK with one minor, go ahead IF the regression is clean.

Hi Pan:

Could you help to verify this patch and commit if the regression is clean?

thanks :)

> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"

Add -Wno-psabi here rather than below, and also add it for
g++.target/riscv/rvv/rvv.exp

>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -       "" $CFLAGS
> +       "-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
>         "" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \