From: Christoph Muellner <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu
Date: Fri, 28 Apr 2023 08:12:02 +0200 [thread overview]
Message-ID: <20230428061210.2988035-2-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
* config/riscv/riscv.md: No base-ISA extension splitter for XThead*.
* config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
New XThead extension INSN.
(*zero_extendsidi2_th_extu): New XThead extension INSN.
(*zero_extendhi<GPR:mode>2_th_extu): New XThead extension INSN.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbb-ext-1.c: New test.
* gcc.target/riscv/xtheadbb-extu-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/riscv.md | 6 +-
gcc/config/riscv/thead.md | 31 +++++++++
.../gcc.target/riscv/xtheadbb-ext-1.c | 67 +++++++++++++++++++
.../gcc.target/riscv/xtheadbb-extu-1.c | 67 +++++++++++++++++++
4 files changed, 168 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1fb29da8a0b..f4cc99187ed 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:SI 1 "nonimmediate_operand" " r,m")))]
- "TARGET_64BIT && !TARGET_ZBA
+ "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB
&& !(register_operand (operands[1], SImode)
&& reg_or_subregno (operands[1]) == VL_REGNUM)"
"@
@@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi<GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=r,r")
(zero_extend:GPR
(match_operand:HI 1 "nonimmediate_operand" " r,m")))]
- "!TARGET_ZBB"
+ "!TARGET_ZBB && !TARGET_XTHEADBB"
"@
#
lhu\t%0,%1"
@@ -1451,7 +1451,7 @@ (define_insn_and_split "*extend<SHORT:mode><SUPERQI:mode>2"
[(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
(sign_extend:SUPERQI
(match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
- "!TARGET_ZBB"
+ "!TARGET_ZBB && !TARGET_XTHEADBB"
"@
#
l<SHORT:size>\t%0,%1"
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 0623607d3dc..6a06d0dfcf2 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -59,6 +59,17 @@ (define_insn "*th_ext<mode>4"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<GPR:MODE>")])
+(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_th_ext"
+ [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
+ (sign_extend:SUPERQI
+ (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_XTHEADBB"
+ "@
+ th.ext\t%0,%1,15,0
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "<SUPERQI:MODE>")])
+
(define_insn "*th_extu<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=r")
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
@@ -72,6 +83,26 @@ (define_insn "*th_extu<mode>4"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<GPR:MODE>")])
+(define_insn "*zero_extendsidi2_th_extu"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_64BIT && TARGET_XTHEADBB"
+ "@
+ th.extu\t%0,%1,31,0
+ lwu\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "SI")])
+
+(define_insn "*zero_extendhi<GPR:mode>2_th_extu"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ "TARGET_XTHEADBB"
+ "@
+ th.extu\t%0,%1,15,0
+ lhu\t%0,%1"
+ [(set_attr "type" "bitmanip,load")
+ (set_attr "mode" "HI")])
+
(define_insn "*th_clz<mode>2"
[(set (match_operand:X 0 "register_operand" "=r")
(clz:X (match_operand:X 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
new file mode 100644
index 00000000000..02f6ec1417d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+long sext64_32(int s32)
+{
+ return s32;
+}
+
+long sext64_16(short s16)
+{
+ return s16;
+}
+
+long sext64_8(char s8)
+{
+ return s8;
+}
+
+int sext32_64(long s64)
+{
+ return s64;
+}
+
+int sext32_16(short s16)
+{
+ return s16;
+}
+
+int sext32_8(char s8)
+{
+ return s8;
+}
+
+short sext16_64(long s64)
+{
+ return s64;
+}
+
+short sext16_32(int s32)
+{
+ return s32;
+}
+
+short sext16_8(char s8)
+{
+ return s8;
+}
+
+char sext8_64(long s64)
+{
+ return s64;
+}
+
+char sext8_32(int s32)
+{
+ return s32;
+}
+
+char sext8_16(short s16)
+{
+ return s16;
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-final { scan-assembler-not "srli" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
new file mode 100644
index 00000000000..01e3eda7df2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+unsigned long zext64_32(unsigned int u32)
+{
+ return u32; //th.extu a0, a0, 31, 0
+}
+
+unsigned long zext64_16(unsigned short u16)
+{
+ return u16;
+}
+
+unsigned long zext64_8(unsigned char u8)
+{
+ return u8;
+}
+
+unsigned int zext32_64(unsigned long u64)
+{
+ return u64;
+}
+
+unsigned int zext32_16(unsigned short u16)
+{
+ return u16;
+}
+
+unsigned int zext32_8(unsigned char u8)
+{
+ return u8;
+}
+
+unsigned short zext16_64(unsigned long u64)
+{
+ return u64;
+}
+
+unsigned short zext16_32(unsigned int u32)
+{
+ return u32;
+}
+
+unsigned short zext16_8(unsigned char u8)
+{
+ return u8;
+}
+
+unsigned char zext8_64(unsigned long u64)
+{
+ return u64;
+}
+
+unsigned char zext8_32(unsigned int u32)
+{
+ return u32;
+}
+
+unsigned char zext8_16(unsigned short u16)
+{
+ return u16;
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-final { scan-assembler-not "srli" } } */
--
2.40.1
next prev parent reply other threads:[~2023-04-28 6:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 6:12 [PATCH 00/11] Improvements for XThead* support Christoph Muellner
2023-04-28 6:12 ` Christoph Muellner [this message]
2023-04-28 7:17 ` [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu Kito Cheng
2023-04-28 6:12 ` [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes Christoph Muellner
2023-04-28 7:17 ` Kito Cheng
2024-03-17 20:22 ` Christoph Müllner
2024-03-18 3:25 ` Jeff Law
2023-04-28 6:12 ` [PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands() Christoph Muellner
2023-04-28 7:18 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN Christoph Muellner
2023-04-28 7:19 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 05/11] riscv: Simplify output of MEM addresses Christoph Muellner
2023-04-28 7:21 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 06/11] riscv: Define Xmode macro Christoph Muellner
2023-04-28 7:23 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 07/11] riscv: Move address classification info types to riscv-protos.h Christoph Muellner
2023-04-28 7:23 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 08/11] riscv: Prepare backend for index registers Christoph Muellner
2023-04-28 8:34 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes Christoph Muellner
2023-04-28 8:37 ` Kito Cheng
2023-04-28 8:35 ` [PATCH 00/11] Improvements for XThead* support Kito Cheng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230428061210.2988035-2-christoph.muellner@vrull.eu \
--to=christoph.muellner@vrull.eu \
--cc=andrew@sifive.com \
--cc=cooper.qu@linux.alibaba.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jim.wilson.gcc@gmail.com \
--cc=kito.cheng@sifive.com \
--cc=lifang_xia@linux.alibaba.com \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
--cc=yunhai@linux.alibaba.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).