Re: [PATCH 00/11] Improvements for XThead* support

[Kito Cheng <kito.cheng@sifive.com>]

Feel free to just commit those patch got approved, I think last two
patch will take longer time to review than others :P

On Fri, Apr 28, 2023 at 2:12 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This series improves the support for the XThead* ISA extensions
> which are available e.g. on the T-Head XuanTie C906.
>
> The ISA spec can be found here:
>   https://github.com/T-head-Semi/thead-extension-spec
>
> So far the following extension support has been merged in GCC:
> * XTheadBa
> * XTheadBb
> * XTheadBs
> * XTheadCmo
> * XTheadCondMov
> * XTheadMemPair
>
> This patchset builds upon that and contains the following changes:
> * Fix for sign/zero extension support for th.ext and th.extu
>   This is actually a resend, that has not been merged.
>   Jeff Law acked the patch last Friday.
> * Fix for CFA reg notes creation
> * Small fix for documentation of th_mempair_order_operands()
> * Introduction of Xmode macro
> * Two non-functional preparation commits for additional addressing modes
> * A patch that moves XThead* specific peephole passes in its own file
> * Support for XTheadMemIdx and its addressing modes
> * Support for XTheadFMemIdx, which is similar to XTheadMemIdx
>
> All patches have been tested and don't introduce regressions
> for RV32 or RV64. The patches have also been tested with
> SPEC CPU2017 on QEMU (multiple combinations of extensions).
>
> Support patches of these extensions for Binutils, QEMU, and
> LLVM have already been merged in the corresponding upstream
> projects.
>
> Support patches for XTheadMemIdx and XTheadFMemIdx have been
> submitted in an earlier series as well and received a couple of
> rework-comments from Kito. We rewrote the whole support to
> better meet the (reasonable) goal of keeping vendor extension
> code separated from RISC-V standard code and to address other issues.
> The resulting code is structured much better, which can be seen
> in the small number of changes that are required for the last patch
> (XTheadFMemIdx support).
>
> Christoph Müllner (11):
>   riscv: xtheadbb: Add sign/zero extension support for th.ext and
>     th.extu
>   riscv: xtheadmempair: Fix CFA reg notes
>   riscv: xtheadmempair: Fix doc for th_mempair_order_operands()
>   riscv: thead: Adjust constraints of th_addsl INSN
>   riscv: Simplify output of MEM addresses
>   riscv: Define Xmode macro
>   riscv: Move address classification info types to riscv-protos.h
>   riscv: Prepare backend for index registers
>   riscv: thead: Factor out XThead*-specific peepholes
>   riscv: thead: Add support for the XTheadMemIdx ISA extension
>   riscv: thead: Add support for the XTheadFMemIdx ISA extension
>
>  gcc/config/riscv/constraints.md               |  24 +
>  gcc/config/riscv/peephole.md                  |  56 --
>  gcc/config/riscv/riscv-protos.h               |  74 +++
>  gcc/config/riscv/riscv.cc                     |  87 ++-
>  gcc/config/riscv/riscv.h                      |  13 +-
>  gcc/config/riscv/riscv.md                     |  26 +-
>  gcc/config/riscv/thead-peephole.md            | 292 ++++++++++
>  gcc/config/riscv/thead.cc                     | 506 +++++++++++++++++-
>  gcc/config/riscv/thead.md                     | 240 ++++++++-
>  .../gcc.target/riscv/xtheadbb-ext-1.c         |  67 +++
>  .../gcc.target/riscv/xtheadbb-extu-1.c        |  67 +++
>  .../riscv/xtheadfmemidx-index-update.c        |  20 +
>  .../xtheadfmemidx-index-xtheadbb-update.c     |  20 +
>  .../riscv/xtheadfmemidx-index-xtheadbb.c      |  22 +
>  .../gcc.target/riscv/xtheadfmemidx-index.c    |  22 +
>  .../riscv/xtheadfmemidx-uindex-update.c       |  20 +
>  .../xtheadfmemidx-uindex-xtheadbb-update.c    |  20 +
>  .../riscv/xtheadfmemidx-uindex-xtheadbb.c     |  24 +
>  .../gcc.target/riscv/xtheadfmemidx-uindex.c   |  25 +
>  .../gcc.target/riscv/xtheadmemidx-helpers.h   | 222 ++++++++
>  .../riscv/xtheadmemidx-index-update.c         |  27 +
>  .../xtheadmemidx-index-xtheadbb-update.c      |  27 +
>  .../riscv/xtheadmemidx-index-xtheadbb.c       |  36 ++
>  .../gcc.target/riscv/xtheadmemidx-index.c     |  36 ++
>  .../riscv/xtheadmemidx-modify-xtheadbb.c      |  74 +++
>  .../gcc.target/riscv/xtheadmemidx-modify.c    |  74 +++
>  .../riscv/xtheadmemidx-uindex-update.c        |  27 +
>  .../xtheadmemidx-uindex-xtheadbb-update.c     |  27 +
>  .../riscv/xtheadmemidx-uindex-xtheadbb.c      |  44 ++
>  .../gcc.target/riscv/xtheadmemidx-uindex.c    |  44 ++
>  30 files changed, 2146 insertions(+), 117 deletions(-)
>  create mode 100644 gcc/config/riscv/thead-peephole.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c
>
> --
> 2.40.1
>