From: Kito Cheng <kito.cheng@gmail.com>
To: Christoph Muellner <christoph.muellner@vrull.eu>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 06/11] riscv: Define Xmode macro
Date: Fri, 28 Apr 2023 15:23:13 +0800 [thread overview]
Message-ID: <CA+yXCZBhykD-61Q3rTo2po42gHOCYE83-yJpPS72XJiBpxz=_A@mail.gmail.com> (raw)
In-Reply-To: <20230428061210.2988035-7-christoph.muellner@vrull.eu>
My first impression is that it should be the same as Pmode, but I
admit it has more clear semantics, and would be useful when we have
ilp32 on rv64.
So LGTM
On Fri, Apr 28, 2023 at 2:16 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> Define a Xmode macro that specifies the registers size (XLEN)
> similar to Pmode. This allows the backend code to write generic
> RV32/RV64 C code (under certain circumstances).
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (Xmode): New macro.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> ---
> gcc/config/riscv/riscv.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 66fb07d6652..90746fe14e3 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -791,6 +791,10 @@ typedef struct {
>
> #define Pmode word_mode
>
> +/* Specify the machine mode that registers have. */
> +
> +#define Xmode (TARGET_64BIT ? DImode : SImode)
> +
> /* Give call MEMs SImode since it is the "most permissive" mode
> for both 32-bit and 64-bit targets. */
>
> --
> 2.40.1
>
next prev parent reply other threads:[~2023-04-28 7:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 6:12 [PATCH 00/11] Improvements for XThead* support Christoph Muellner
2023-04-28 6:12 ` [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu Christoph Muellner
2023-04-28 7:17 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes Christoph Muellner
2023-04-28 7:17 ` Kito Cheng
2024-03-17 20:22 ` Christoph Müllner
2024-03-18 3:25 ` Jeff Law
2023-04-28 6:12 ` [PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands() Christoph Muellner
2023-04-28 7:18 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN Christoph Muellner
2023-04-28 7:19 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 05/11] riscv: Simplify output of MEM addresses Christoph Muellner
2023-04-28 7:21 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 06/11] riscv: Define Xmode macro Christoph Muellner
2023-04-28 7:23 ` Kito Cheng [this message]
2023-04-28 6:12 ` [PATCH 07/11] riscv: Move address classification info types to riscv-protos.h Christoph Muellner
2023-04-28 7:23 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 08/11] riscv: Prepare backend for index registers Christoph Muellner
2023-04-28 8:34 ` Kito Cheng
2023-04-28 6:12 ` [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes Christoph Muellner
2023-04-28 8:37 ` Kito Cheng
2023-04-28 8:35 ` [PATCH 00/11] Improvements for XThead* support Kito Cheng
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