From: Xiao Zeng <zengxiao@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: jeffreyalaw@gmail.com, research_trasio@irq.a4lg.com,
kito.cheng@gmail.com, zhengyu@eswincomputing.com,
eri-sw-toolchain@eswincomputing.com,
Xiao Zeng <zengxiao@eswincomputing.com>
Subject: [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics
Date: Wed, 19 Jul 2023 18:11:53 +0800 [thread overview]
Message-ID: <20230719101156.21771-3-zengxiao@eswincomputing.com> (raw)
In-Reply-To: <20230719101156.21771-1-zengxiao@eswincomputing.com>
This patch completes the recognition of the basic semantics
defined in the spec, namely:
Conditional zero, if condition is equal to zero
rd = (rs2 == 0) ? 0 : rs1
Conditional zero, if condition is non zero
rd = (rs2 != 0) ? 0 : rs1
gcc/ChangeLog:
* config/riscv/riscv.md: Include zicond.md
* config/riscv/zicond.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-primitiveSemantics.c: New test.
---
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/zicond.md | 84 +++++++++++++++++++
.../riscv/zicond-primitiveSemantics.c | 49 +++++++++++
3 files changed, 134 insertions(+)
create mode 100644 gcc/config/riscv/zicond.md
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d63b584a4c1..6b8c2e8e268 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3317,3 +3317,4 @@
(include "sifive-7.md")
(include "thead.md")
(include "vector.md")
+(include "zicond.md")
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
new file mode 100644
index 00000000000..1cf28589c87
--- /dev/null
+++ b/gcc/config/riscv/zicond.md
@@ -0,0 +1,84 @@
+;; Machine description for the RISC-V Zicond extension
+;; Copyright (C) 2022-23 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr eqz [(eq "nez") (ne "eqz")])
+(define_code_attr nez [(eq "eqz") (ne "nez")])
+
+;; Zicond
+(define_insn "*czero.<eqz>.<GPR:mode><ANYI:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (eq_or_ne (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:GPR 2 "register_operand" "r")
+ (const_int 0)))]
+ "TARGET_ZICOND"
+ "czero.<eqz>\t%0,%2,%1"
+)
+
+(define_insn "*czero.<nez>.<GPR:mode><ANYI:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (eq_or_ne (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (const_int 0)
+ (match_operand:GPR 2 "register_operand" "r")))]
+ "TARGET_ZICOND"
+ "czero.<nez>\t%0,%2,%1"
+)
+
+;; Special optimization under eq/ne in primitive semantics
+(define_insn "*czero.eqz.<GPR:mode><ANYI:mode>.opt1"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (eq (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:GPR 2 "register_operand" "1")
+ (match_operand:GPR 3 "register_operand" "r")))]
+ "TARGET_ZICOND && operands[1] == operands[2]"
+ "czero.eqz\t%0,%3,%1"
+)
+
+(define_insn "*czero.eqz.<GPR:mode><ANYI:mode>.opt2"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (eq (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:GPR 2 "register_operand" "r")
+ (match_operand:GPR 3 "register_operand" "1")))]
+ "TARGET_ZICOND && operands[1] == operands[3]"
+ "czero.nez\t%0,%2,%1"
+)
+
+(define_insn "*czero.nez.<GPR:mode><ANYI:mode>.opt3"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (ne (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:GPR 2 "register_operand" "r")
+ (match_operand:GPR 3 "register_operand" "1")))]
+ "TARGET_ZICOND && operands[1] == operands[3]"
+ "czero.eqz\t%0,%2,%1"
+)
+
+(define_insn "*czero.nez.<GPR:mode><ANYI:mode>.opt4"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (if_then_else:GPR (ne (match_operand:ANYI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:GPR 2 "register_operand" "1")
+ (match_operand:GPR 3 "register_operand" "r")))]
+ "TARGET_ZICOND && operands[1] == operands[2]"
+ "czero.nez\t%0,%3,%1"
+)
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c
new file mode 100644
index 00000000000..76c5019a992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */
+/* { dg-final { scan-assembler-times "czero.nez" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
--
2.17.1
next prev parent reply other threads:[~2023-07-19 10:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35 ` Jeff Law
2023-07-26 21:11 ` Jeff Law
2023-07-19 10:11 ` Xiao Zeng [this message]
2023-07-25 16:35 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Jeff Law
2023-07-26 17:53 ` Jeff Law
2023-08-01 11:18 ` Richard Sandiford
2023-08-02 6:22 ` Jeff Law
2023-08-02 10:05 ` Richard Sandiford
2023-08-02 16:56 ` Jeff Law
2023-07-26 21:14 ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32 ` Jeff Law
2023-07-25 17:55 ` Andreas Schwab
2023-07-27 5:44 ` Xiao Zeng
2023-07-28 15:09 ` Jeff Law
2023-07-29 9:48 ` Xiao Zeng
2023-07-28 20:59 ` Jeff Law
2023-07-29 9:14 ` Xiao Zeng
2023-08-03 4:59 ` Jeff Law
2023-08-02 6:34 ` Jeff Law
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36 ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27 8:43 ` Xiao Zeng
2023-07-27 14:43 ` Jeff Law
2023-07-28 6:34 ` Xiao Zeng
2023-07-28 15:03 ` Jeff Law
2023-07-29 10:01 ` Xiao Zeng
2023-08-03 2:59 ` Jeff Law
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