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From: "Xiao Zeng" <zengxiao@eswincomputing.com>
To: jeffreyalaw <jeffreyalaw@gmail.com>,
	 gcc-patches <gcc-patches@gcc.gnu.org>
Cc: research_trasio <research_trasio@irq.a4lg.com>,
	 kito.cheng <kito.cheng@gmail.com>,
	 zhengyu <zhengyu@eswincomputing.com>,
	 eri-sw-toolchain <eri-sw-toolchain@eswincomputing.com>
Subject: Re: Re: [PATCH 0/5] Recognize Zicond extension
Date: Thu, 27 Jul 2023 16:43:49 +0800	[thread overview]
Message-ID: <2023072716434903717718@eswincomputing.com> (raw)
In-Reply-To: <c7d39918-ed70-b95a-bdc9-ab3a3e4660fd@gmail.com>

On Wed, Jul 26, 2023 at 01:51:00 AM  Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
>On 7/19/23 04:11, Xiao Zeng wrote:
>> Hi all RISC-V folks:
>>
>> This series of patches completes support for the riscv architecture's
>> Zicond standard extension instruction set.
>>
>> Currently, Zicond is in a frozen state.
>>
>> See the Zicond specification for details:
>> https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
>>
>> Prior to this, other community members have also done related work, as shown in:
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611767.html
>> https://sourceware.org/pipermail/binutils/2023-January/125773.html
>>
>> Xiao Zeng (5):
>>    [RISC-V] Recognize Zicond extension
>>    [RISC-V] Generate Zicond instruction for basic semantics
>>    [RISC-V] Generate Zicond instruction for select pattern with condition
>>      eq or neq to 0
>>    [RISC-V] Generate Zicond instruction for select pattern with condition
>>      eq or neq to non-zero
>>    [RISC-V] Generate Zicond instruction for conditional execution
>[ ... ]
>So what I'm thinking for the overall kit is to stage it in a bit
>differently given we have some bits which clearly can go forward as-is
>or with very minor changes and others that are going to need some
>iteration/refinement.
>
>So I'm going to suggest a few changes so that bits which are non
>controversial can move forward immediately.
>
>1/5 looked fine as-is.
>
>I would split 2/5.  The first two patterns you added are
>non-controversial and could go in immediately.  The other 4 patterns
>(which require some operand matching) will likely need at least one
>round of iteration and should be a distinct patch.
>
>
>I would split 3/5 as well.  3a would be the costing which I think just
>needs to use COSTS_N_INSNS (1) rather than 0 for the cost of a
>conditional move and could then move forward immediately.  The bits to
>wire everything up into the conditional move pattern would be a distinct
>patch.  We did something similar internally in Ventana and I'd like to
>take the time to make sure the issues we ran into are addressed in your
>version then do an evaluation of the two approaches.
>
>I think patch 4 is probably going to need some work too.  I *think* what
>we did internally at Ventana will work better (utilizing scc for a
>non-trivial condition).
>
>Let's defer patch #5 initially as well.  It's going to get tangled up in
>a whole bunch of changes I think we need to make to ifcvt.cc.
>
>The point being that with the bits from #1, #2 and #3 we can get some
>initial support in immediately.  eswincomputing and ventana can both
>reduce our divergence from the trunk and work together on the rest of
>the bits.
>
>Does that work for you?
>
>jeff 

1 Thanks Jeff for your code review feedback.

2. According to your opinions, I have modified the code, but out of caution
for upstream, I conducted a complete regression tests on patch V2, which took
some time. I was unable to reply to emails and upload patch V2 in a timely manner.

3 After you and other maintainers made minor modifications to my patch[1/5] 
and patch[2/5], it has been merged into the master, so I will no longer upload patch V2.

4 patch[1/5] and patch[2/5], which have been merged into the master, have only
completed basic support for Zicond, and further optimization work needs to be
completed. These further optimization reactions are reflected in my patch[3/5]
patch[4/5] and patch[5/5].

5 As you mentioned in your previous email https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625427.html
"eswincomputing and ventana can both reduce our divergence from the trunk
and work together on the rest of the bits...". I will reorganize patch[3/5] patch[4/5]
and patch[5/5], provide more detailed explanations, and submit them as an alternative
solution for further optimization of Zicond.

Does that work for you?

Xiao Zeng

  reply	other threads:[~2023-07-27  8:43 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-19 10:11 Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 21:11   ` Jeff Law
2023-07-19 10:11 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 17:53   ` Jeff Law
2023-08-01 11:18     ` Richard Sandiford
2023-08-02  6:22       ` Jeff Law
2023-08-02 10:05         ` Richard Sandiford
2023-08-02 16:56           ` Jeff Law
2023-07-26 21:14   ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32   ` Jeff Law
2023-07-25 17:55   ` Andreas Schwab
2023-07-27  5:44     ` Xiao Zeng
2023-07-28 15:09     ` Jeff Law
2023-07-29  9:48       ` Xiao Zeng
2023-07-28 20:59   ` Jeff Law
2023-07-29  9:14     ` Xiao Zeng
2023-08-03  4:59       ` Jeff Law
2023-08-02  6:34   ` Jeff Law
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36   ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27  8:43   ` Xiao Zeng [this message]
2023-07-27 14:43     ` Jeff Law
2023-07-28  6:34       ` Xiao Zeng
2023-07-28 15:03         ` Jeff Law
2023-07-29 10:01           ` Xiao Zeng
2023-08-03  2:59         ` Jeff Law

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