From: Andreas Schwab <schwab@linux-m68k.org>
To: Xiao Zeng <zengxiao@eswincomputing.com>
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com,
research_trasio@irq.a4lg.com, kito.cheng@gmail.com,
zhengyu@eswincomputing.com, eri-sw-toolchain@eswincomputing.com
Subject: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
Date: Tue, 25 Jul 2023 19:55:36 +0200 [thread overview]
Message-ID: <87tttrj2p3.fsf@igel.home> (raw)
In-Reply-To: <20230719101156.21771-4-zengxiao@eswincomputing.com> (Xiao Zeng's message of "Wed, 19 Jul 2023 18:11:54 +0800")
On Jul 19 2023, Xiao Zeng wrote:
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 38d8eb2fcf5..7e6b24bd232 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
> *total = COSTS_N_INSNS (1);
> return true;
> }
> + else if (TARGET_ZICOND && outer_code == SET &&
> + ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
> + (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
> + XEXP (x, 2) == XEXP (XEXP (x, 0), 0))))
Line breaks before the operator, not after.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
next prev parent reply other threads:[~2023-07-25 17:55 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35 ` Jeff Law
2023-07-26 21:11 ` Jeff Law
2023-07-19 10:11 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Xiao Zeng
2023-07-25 16:35 ` Jeff Law
2023-07-26 17:53 ` Jeff Law
2023-08-01 11:18 ` Richard Sandiford
2023-08-02 6:22 ` Jeff Law
2023-08-02 10:05 ` Richard Sandiford
2023-08-02 16:56 ` Jeff Law
2023-07-26 21:14 ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32 ` Jeff Law
2023-07-25 17:55 ` Andreas Schwab [this message]
2023-07-27 5:44 ` Xiao Zeng
2023-07-28 15:09 ` Jeff Law
2023-07-29 9:48 ` Xiao Zeng
2023-07-28 20:59 ` Jeff Law
2023-07-29 9:14 ` Xiao Zeng
2023-08-03 4:59 ` Jeff Law
2023-08-02 6:34 ` Jeff Law
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36 ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27 8:43 ` Xiao Zeng
2023-07-27 14:43 ` Jeff Law
2023-07-28 6:34 ` Xiao Zeng
2023-07-28 15:03 ` Jeff Law
2023-07-29 10:01 ` Xiao Zeng
2023-08-03 2:59 ` Jeff Law
2023-08-03 9:27 [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 juzhe.zhong
2023-08-03 13:49 ` Jeff Law
2023-08-03 13:56 ` Kito Cheng
2023-08-03 14:08 ` Jeff Law
2023-08-03 14:31 ` Kito Cheng
2023-08-03 14:41 ` Jeff Law
2023-08-03 14:56 ` Kito Cheng
2023-08-03 15:09 ` Jeff Law
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