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From: Richard Sandiford <richard.sandiford@arm.com>
To: Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Xiao Zeng <zengxiao@eswincomputing.com>,
	 research_trasio@irq.a4lg.com,  kito.cheng@gmail.com,
	 zhengyu@eswincomputing.com,
	 eri-sw-toolchain@eswincomputing.com,
	 Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics
Date: Wed, 02 Aug 2023 11:05:59 +0100	[thread overview]
Message-ID: <mptmsz992t4.fsf@arm.com> (raw)
In-Reply-To: <d6f0d1f8-583e-30e5-9b70-c3f30451512b@gmail.com> (Jeff Law via Gcc-patches's message of "Wed, 2 Aug 2023 00:22:55 -0600")

Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> On 8/1/23 05:18, Richard Sandiford wrote:
>> 
>> Where were you seeing the requirement for pointer equality?  genrecog.cc
>> at least uses rtx_equal_p, and I think it has to.  E.g. some patterns
>> use (match_dup ...) to match output and input mems, and mem rtxes
>> shouldn't be shared.
> It's a general concern due to the way we handle transforming pseudos 
> into hard registers after allocation is complete.   We can end up with 
> two REG expressions that will compare equal according to rtx_equal_p, 
> but which are not pointer equal.

But isn't that OK?  I don't think there's a requirement for match_dup
pointer equality either before or after RA.  Or at least, there
shouldn't be.  If something happens to rely on pointer equality
for match_dups then I think we should fix it.

So IMO, like you said originally, match_dup would be the right way to
handle this kind of pattern.

The reason I'm interested is that AArch64 makes pretty extensive use
of match_dup for this purpose.  E.g.:

(define_insn "aarch64_<su>abd<mode><vczle><vczbe>"
  [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
	(minus:VDQ_BHSI
	  (USMAX:VDQ_BHSI
	    (match_operand:VDQ_BHSI 1 "register_operand" "w")
	    (match_operand:VDQ_BHSI 2 "register_operand" "w"))
	  (<max_opp>:VDQ_BHSI
	    (match_dup 1)
	    (match_dup 2))))]

So if this isn't working correctly for subregs (or for anythine else),
then I'd be keen to do something about it :)

I don't want to labour the point though.

Thanks,
Richard

  reply	other threads:[~2023-08-02 10:06 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 21:11   ` Jeff Law
2023-07-19 10:11 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 17:53   ` Jeff Law
2023-08-01 11:18     ` Richard Sandiford
2023-08-02  6:22       ` Jeff Law
2023-08-02 10:05         ` Richard Sandiford [this message]
2023-08-02 16:56           ` Jeff Law
2023-07-26 21:14   ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32   ` Jeff Law
2023-07-25 17:55   ` Andreas Schwab
2023-07-27  5:44     ` Xiao Zeng
2023-07-28 15:09     ` Jeff Law
2023-07-29  9:48       ` Xiao Zeng
2023-07-28 20:59   ` Jeff Law
2023-07-29  9:14     ` Xiao Zeng
2023-08-03  4:59       ` Jeff Law
2023-08-02  6:34   ` Jeff Law
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36   ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27  8:43   ` Xiao Zeng
2023-07-27 14:43     ` Jeff Law
2023-07-28  6:34       ` Xiao Zeng
2023-07-28 15:03         ` Jeff Law
2023-07-29 10:01           ` Xiao Zeng
2023-08-03  2:59         ` Jeff Law

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