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From: Jeff Law <jeffreyalaw@gmail.com>
To: Xiao Zeng <zengxiao@eswincomputing.com>, gcc-patches@gcc.gnu.org
Cc: research_trasio@irq.a4lg.com, kito.cheng@gmail.com,
	zhengyu@eswincomputing.com, eri-sw-toolchain@eswincomputing.com
Subject: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0
Date: Wed, 2 Aug 2023 00:34:31 -0600	[thread overview]
Message-ID: <de511abe-e260-b0f6-dfb6-7a986c095090@gmail.com> (raw)
In-Reply-To: <20230719101156.21771-4-zengxiao@eswincomputing.com>

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On 7/19/23 04:11, Xiao Zeng wrote:
> This patch completes the recognition of Zicond when the select pattern
> with condition eq or neq to 0 (using equality as an example), namely:
[ ... ]
I've committed the attached patch which implements a simple cost model 
for using Zicond to implement conditional moves.

I've changed it to give the proper cost (COSTS_N_INSNS (1) and removed 
the extraneous GET_CODE (object) tests adjusted the ChangeLog a bit and 
pushed it to the trunk.

Thanks!

Jeff

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commit 5b501863ac7da57858fdd464dfb7a776143f22a2
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date:   Wed Aug 2 00:17:12 2023 -0600

    [PATCH 3/5] [RISC-V] Cost model for Zicond.
    
    This patch implements a reasonable cost model for using Zicond to
    implement conditional moves.  Essentially the Zicond insns are always
    COSTS_N_INSNS (1).
    
    Note there is still a problem with the costing model in general that
    results in failure to if-convert as often as we should.  In simplest
    terms the insn costing model sums the cost of the SET_SRC and the
    cost of the SET_DEST.  Thus the conditional move is considered twice
    as costly as it should be.  That will have to be addressed separately.
    
    gcc/
            * config/riscv/riscv.cc (riscv_rtx_costs): Add costing for
            using Zicond to implement some conditional moves.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8c474503080..785e09c76ce 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2518,6 +2518,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  *total = COSTS_N_INSNS (1);
 	  return true;
 	}
+      else if (TARGET_ZICOND
+	       && outer_code == SET
+	       && ((GET_CODE (XEXP (x, 1)) == REG
+		    && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
+		   || (GET_CODE (XEXP (x, 2)) == REG
+		       && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 2))))
+		   || (GET_CODE (XEXP (x, 1)) == REG
+		       && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0)))
+		   || (GET_CODE (XEXP (x, 1)) == REG
+		       && rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0)))))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
       else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
 	{
 	  if (equality_operator (XEXP (x, 0), mode)

  parent reply	other threads:[~2023-08-02  6:34 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 21:11   ` Jeff Law
2023-07-19 10:11 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 17:53   ` Jeff Law
2023-08-01 11:18     ` Richard Sandiford
2023-08-02  6:22       ` Jeff Law
2023-08-02 10:05         ` Richard Sandiford
2023-08-02 16:56           ` Jeff Law
2023-07-26 21:14   ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32   ` Jeff Law
2023-07-25 17:55   ` Andreas Schwab
2023-07-27  5:44     ` Xiao Zeng
2023-07-28 15:09     ` Jeff Law
2023-07-29  9:48       ` Xiao Zeng
2023-07-28 20:59   ` Jeff Law
2023-07-29  9:14     ` Xiao Zeng
2023-08-03  4:59       ` Jeff Law
2023-08-02  6:34   ` Jeff Law [this message]
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36   ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27  8:43   ` Xiao Zeng
2023-07-27 14:43     ` Jeff Law
2023-07-28  6:34       ` Xiao Zeng
2023-07-28 15:03         ` Jeff Law
2023-07-29 10:01           ` Xiao Zeng
2023-08-03  2:59         ` Jeff Law
2023-08-03  9:27 [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 juzhe.zhong
2023-08-03 13:49 ` Jeff Law
2023-08-03 13:56   ` Kito Cheng
2023-08-03 14:08     ` Jeff Law
2023-08-03 14:31       ` Kito Cheng
2023-08-03 14:41         ` Jeff Law
2023-08-03 14:56           ` Kito Cheng
2023-08-03 15:09             ` Jeff Law

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