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From: Jeff Law <jeffreyalaw@gmail.com>
To: Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org>,
	Xiao Zeng <zengxiao@eswincomputing.com>,
	research_trasio@irq.a4lg.com, kito.cheng@gmail.com,
	zhengyu@eswincomputing.com, eri-sw-toolchain@eswincomputing.com,
	richard.sandiford@arm.com
Subject: Re: [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics
Date: Wed, 2 Aug 2023 00:22:55 -0600	[thread overview]
Message-ID: <d6f0d1f8-583e-30e5-9b70-c3f30451512b@gmail.com> (raw)
In-Reply-To: <mpttttj80yw.fsf@arm.com>



On 8/1/23 05:18, Richard Sandiford wrote:
> 
> Where were you seeing the requirement for pointer equality?  genrecog.cc
> at least uses rtx_equal_p, and I think it has to.  E.g. some patterns
> use (match_dup ...) to match output and input mems, and mem rtxes
> shouldn't be shared.
It's a general concern due to the way we handle transforming pseudos 
into hard registers after allocation is complete.   We can end up with 
two REG expressions that will compare equal according to rtx_equal_p, 
but which are not pointer equal.

For this kit I think the worst that would happen would be a failure to 
optimize cases post-reload.  But it's still good RTL hygene IMHO.



> 
> I'd always understood using matching constraints against other inputs
> to be a no-no, since the RA doesn't (and can't reasonably be expected to)
> make two non-identical inputs match.  So AIUI, using "1" won't lead to
> different code generation compared to "r".  Both are relying on the RA
> happening to do the right thing.  But "1" would presumably trigger an
> ICE if something goes wrong.
Yea, I think you're right.  The constraint isn't terribly important for 
these patterns -- the condition is really the enforcement mechanism.

Jeff

  reply	other threads:[~2023-08-02  6:23 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-19 10:11 [PATCH 0/5] Recognize Zicond extension Xiao Zeng
2023-07-19 10:11 ` [PATCH 1/5] [RISC-V] " Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 21:11   ` Jeff Law
2023-07-19 10:11 ` [PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics Xiao Zeng
2023-07-25 16:35   ` Jeff Law
2023-07-26 17:53   ` Jeff Law
2023-08-01 11:18     ` Richard Sandiford
2023-08-02  6:22       ` Jeff Law [this message]
2023-08-02 10:05         ` Richard Sandiford
2023-08-02 16:56           ` Jeff Law
2023-07-26 21:14   ` Jeff Law
2023-07-19 10:11 ` [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 Xiao Zeng
2023-07-25 17:32   ` Jeff Law
2023-07-25 17:55   ` Andreas Schwab
2023-07-27  5:44     ` Xiao Zeng
2023-07-28 15:09     ` Jeff Law
2023-07-29  9:48       ` Xiao Zeng
2023-07-28 20:59   ` Jeff Law
2023-07-29  9:14     ` Xiao Zeng
2023-08-03  4:59       ` Jeff Law
2023-08-02  6:34   ` Jeff Law
2023-07-19 10:11 ` [PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero Xiao Zeng
2023-08-07 17:36   ` Jeff Law
2023-07-19 10:11 ` [PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution Xiao Zeng
2023-07-25 17:51 ` [PATCH 0/5] Recognize Zicond extension Jeff Law
2023-07-27  8:43   ` Xiao Zeng
2023-07-27 14:43     ` Jeff Law
2023-07-28  6:34       ` Xiao Zeng
2023-07-28 15:03         ` Jeff Law
2023-07-29 10:01           ` Xiao Zeng
2023-08-03  2:59         ` Jeff Law

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