[PATCH v4] RISC-V: Support XTheadVector extension

["Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>]

This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html

Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html

Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, 
and all the tests passed.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>

RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
RISC-V: ...

---
 gcc/common/config/riscv/riscv-common.cc       |   23 +
 gcc/config.gcc                                |    4 +-
 gcc/config/riscv/autovec.md                   |    2 +-
 gcc/config/riscv/predicates.md                |    8 +-
 gcc/config/riscv/riscv-c.cc                   |    8 +-
 gcc/config/riscv/riscv-protos.h               |    1 +
 gcc/config/riscv/riscv-string.cc              |    3 +
 gcc/config/riscv/riscv-v.cc                   |   13 +-
 .../riscv/riscv-vector-builtins-bases.cc      |   18 +-
 .../riscv/riscv-vector-builtins-bases.h       |   19 +
 .../riscv/riscv-vector-builtins-shapes.cc     |  149 +
 .../riscv/riscv-vector-builtins-shapes.h      |    3 +
 .../riscv/riscv-vector-builtins-types.def     |  120 +
 gcc/config/riscv/riscv-vector-builtins.cc     |  315 +-
 gcc/config/riscv/riscv-vector-builtins.h      |    5 +-
 gcc/config/riscv/riscv-vector-switch.def      |  150 +-
 gcc/config/riscv/riscv.cc                     |   46 +-
 gcc/config/riscv/riscv.h                      |    4 +
 gcc/config/riscv/riscv.opt                    |    2 +
 gcc/config/riscv/riscv_th_vector.h            |   49 +
 gcc/config/riscv/t-riscv                      |   16 +
 .../riscv/thead-vector-builtins-functions.def |  659 ++++
 gcc/config/riscv/thead-vector-builtins.cc     |  887 ++++++
 gcc/config/riscv/thead-vector-builtins.h      |  123 +
 gcc/config/riscv/thead-vector.md              | 2827 +++++++++++++++++
 gcc/config/riscv/vector-iterators.md          |  186 +-
 gcc/config/riscv/vector.md                    |   44 +-
 .../riscv/predef-__riscv_th_v_intrinsic.c     |   11 +
 .../gcc.target/riscv/rvv/base/abi-1.c         |    2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c      |    2 +-
 .../gcc.target/riscv/rvv/xtheadvector.c       |   13 +
 .../riscv/rvv/xtheadvector/prefix.c           |   12 +
 .../riscv/rvv/xtheadvector/vlb-vsb.c          |   68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c         |   68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c          |   68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c         |   68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c          |   68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c         |   68 +
 gcc/testsuite/lib/target-supports.exp         |   12 +
 39 files changed, 5931 insertions(+), 213 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
 create mode 100644 gcc/config/riscv/thead-vector-builtins.h
 create mode 100644 gcc/config/riscv/thead-vector.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c