From: "joshua" <cooper.joshua@linux.alibaba.com>
To: 钟居哲 <juzhe.zhong@rivai.ai>, "rdapp.gcc" <rdapp.gcc@gmail.com>,
gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "jim.wilson.gcc" <jim.wilson.gcc@gmail.com>,
palmer <palmer@dabbelt.com>, andrew <andrew@sifive.com>,
"philipp.tomsich" <philipp.tomsich@vrull.eu>,
"Jeff Law" <jeffreyalaw@gmail.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
jinma <jinma@linux.alibaba.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>
Subject: Re:Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions
Date: Thu, 11 Jan 2024 10:40:56 +0800 [thread overview]
Message-ID: <38245137-71b4-44bb-9cf6-18652ff5ee0b.cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <144AA95ABAD559BA+2024011021430256896060@rivai.ai>
Hi Robin,
Thank you for your suggestions!
The patch has been updated by adding a new attribute to
disable alternative for xtheadvector or RVV1.0 instead of
overlaoding group_overlap.
Joshua
------------------------------------------------------------------
发件人:钟居哲 <juzhe.zhong@rivai.ai>
发送时间:2024年1月10日(星期三) 21:43
收件人:"rdapp.gcc"<rdapp.gcc@gmail.com>; "cooper.joshua"<cooper.joshua@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org>
抄 送:"rdapp.gcc"<rdapp.gcc@gmail.com>; "jim.wilson.gcc"<jim.wilson.gcc@gmail.com>; palmer<palmer@dabbelt.com>; andrew<andrew@sifive.com>; "philipp.tomsich"<philipp.tomsich@vrull.eu>; Jeff Law<jeffreyalaw@gmail.com>; "Christoph Müllner"<christoph.muellner@vrull.eu>; jinma<jinma@linux.alibaba.com>; Cooper Qu<cooper.qu@linux.alibaba.com>
主 题:Re: Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions
>> For the other insns, I wonder if we could get away with not really
>>disabling the newly added early-clobber alternatives for RVV but
>>just disparaging ("?") them? That way we could re-use "full" for
>>the thv-disabled alternatives and "none" for the newly added ones.
>>("none" will still be misleading then, though :/)
I prefer to disable those early-clobber alternatives added of theadvector for RVV,
since disparage still make RA possible reaches the early clobber alternatives.
>>If this doesn't work or others feel the separation is not strict
>>enough, I'd prefer a separate attribute rather than overloading
>>group_overlap. Maybe something like "spec_restriction" or similar
>>with two values "rvv" and "thv"?
I like this idea, it makes more sense to me. So I think it's better to add an attribute to
disable alternative for theadvector or RVV1.0.
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2024-01-10 21:36
To: Jun Sha (Joshua); gcc-patches
CC: rdapp.gcc; jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions
Hi Joshua,
> For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
> and floating-point compare instructions, an illegal instruction
> exception will be raised if the destination vector register overlaps
> a source vector register group.
>
> To handle this issue, we use "group_overlap" and "enabled" attribute
> to disable some alternatives for xtheadvector.
> ;; Widening instructions have group-overlap constraints. Those are only
> ;; valid for certain register-group sizes. This attribute marks the
> ;; alternatives not matching the required register-group size as disabled.
> -(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
> +(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0,thv_disabled,rvv_disabled"
> (const_string "none"))
I realize there have been some discussions before but I find the naming
misleading. The group_overlap attribute is supposed to specify whether
groups overlap (and mark the respective alternatives accepting
only this overlap).
Then we check if the groups overlap and disable all non-matching
alternatives. "none" i.e. "no overlap" always matches.
Your first goal seems to be to disable existing non-early-clobber
alternatives for thv. For this, maybe "full", "same" (or "any"?) would
work? Please also add a comment in group_overlap_valid then that we
need not actually check for register equality.
For the other insns, I wonder if we could get away with not really
disabling the newly added early-clobber alternatives for RVV but
just disparaging ("?") them? That way we could re-use "full" for
the thv-disabled alternatives and "none" for the newly added ones.
("none" will still be misleading then, though :/)
If this doesn't work or others feel the separation is not strict
enough, I'd prefer a separate attribute rather than overloading
group_overlap. Maybe something like "spec_restriction" or similar
with two values "rvv" and "thv"?
Regards
Robin
next prev parent reply other threads:[~2024-01-11 2:41 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-29 4:03 [PATCH v4] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2023-12-29 4:05 ` [PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-29 4:06 ` [PATCH v4] RISC-V: Change csr_operand into Jun Sha (Joshua)
2023-12-29 4:10 ` [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns Jun Sha (Joshua)
2024-01-02 1:35 ` juzhe.zhong
2024-01-02 19:50 ` Christoph Müllner
2024-01-02 1:35 ` [PATCH v4] RISC-V: Change csr_operand into juzhe.zhong
2023-12-29 4:13 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-04 9:28 ` Jun Sha (Joshua)
2023-12-29 4:19 ` [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-31 17:43 ` Jeff Law
2024-01-01 22:57 ` 钟居哲
2024-01-03 2:54 ` Andrew Pinski
2024-01-03 3:06 ` juzhe.zhong
2024-01-03 3:19 ` Andrew Pinski
2024-01-03 3:25 ` juzhe.zhong
2024-01-03 3:32 ` Andrew Pinski
2024-01-03 3:32 ` Kito Cheng
2024-01-04 9:15 ` Re:Re: " joshua
2024-01-04 9:18 ` juzhe.zhong
2024-01-04 10:04 ` Christoph Müllner
2024-01-08 2:11 ` Re:Re: " joshua
2024-01-08 3:06 ` Kito Cheng
2024-01-08 3:17 ` Re:Re: " joshua
2024-01-08 3:40 ` Kito Cheng
2024-01-10 3:01 ` Re:Re: " joshua
2024-01-03 6:08 ` Jun Sha (Joshua)
2024-01-08 23:04 ` 钟居哲
2024-01-09 17:49 ` Jeff Law
2024-01-09 22:35 ` 钟居哲
2023-12-29 4:21 ` [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-02 2:00 ` juzhe.zhong
2024-01-02 3:03 ` Re:[PATCH " joshua
2024-01-02 3:10 ` juzhe.zhong
2024-01-02 3:40 ` Re:Re:[PATCH " joshua
2024-01-02 3:41 ` Re:[PATCH " juzhe.zhong
2024-01-02 9:48 ` joshua
2024-01-02 9:52 ` juzhe.zhong
2024-01-02 12:39 ` [PATCH " Jun Sha (Joshua)
2024-01-03 3:11 ` Kito Cheng
2024-01-03 6:15 ` Jun Sha (Joshua)
2024-01-04 2:29 ` Jun Sha (Joshua)
2024-01-09 3:18 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-09 22:33 ` 钟居哲
2024-01-10 2:22 ` Jun Sha (Joshua)
2024-01-10 2:34 ` juzhe.zhong
2024-01-10 2:57 ` Re:[PATCH " joshua
2024-01-10 3:02 ` juzhe.zhong
2024-01-10 6:54 ` juzhe.zhong
2024-01-10 7:01 ` juzhe.zhong
2024-01-10 7:16 ` Re:Re:[PATCH " joshua
2024-01-10 7:17 ` Re:[PATCH " juzhe.zhong
2024-01-10 7:26 ` 回复:Re:[PATCH " joshua
2024-01-10 7:31 ` 回复:[PATCH " juzhe.zhong
2024-01-10 7:28 ` Re:Re:[PATCH " joshua
2024-01-11 11:03 ` [PATCH " Jun Sha (Joshua)
2024-01-08 23:08 ` [PATCH v4] " 钟居哲
2024-01-09 2:12 ` Re:[PATCH " joshua
2024-01-09 3:23 ` joshua
2023-12-29 4:21 ` [PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-04 2:34 ` [PATCH v4] " Jun Sha (Joshua)
2024-01-10 9:27 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10 9:35 ` juzhe.zhong
2024-01-10 9:55 ` Re:[PATCH " joshua
2024-01-10 10:03 ` juzhe.zhong
2024-01-10 10:57 ` Re:Re:[PATCH " joshua
2024-01-10 9:31 ` [PATCH " Jun Sha (Joshua)
2024-01-11 8:46 ` Jun Sha (Joshua)
2024-01-11 9:07 ` juzhe.zhong
2024-01-11 9:11 ` Re:[PATCH " joshua
2024-01-11 9:14 ` joshua
2024-01-11 9:17 ` juzhe.zhong
2024-01-11 9:21 ` Re:Re:[PATCH " joshua
2024-01-11 9:24 ` Re:[PATCH " juzhe.zhong
2024-01-11 9:29 ` Re:Re:[PATCH " joshua
2024-01-11 9:32 ` Re:[PATCH " juzhe.zhong
2024-01-11 9:38 ` Re:Re:[PATCH " joshua
2024-01-11 12:05 ` joshua
2024-01-11 12:13 ` Re:[PATCH " juzhe.zhong
2024-01-11 12:18 ` Re:Re:[PATCH " joshua
2024-01-11 12:28 ` Re:[PATCH " juzhe.zhong
2024-01-11 12:31 ` Re:Re:[PATCH " joshua
2024-01-11 12:33 ` Re:[PATCH " juzhe.zhong
2024-01-11 12:36 ` Re:Re:[PATCH " joshua
2024-01-11 9:26 ` joshua
2024-01-11 9:28 ` Re:[PATCH " juzhe.zhong
2024-01-11 9:35 ` Re:Re:[PATCH " joshua
2024-01-11 9:54 ` Re:[PATCH " joshua
2024-01-11 9:52 ` [PATCH " Jun Sha (Joshua)
2024-01-11 9:57 ` juzhe.zhong
2024-01-11 10:54 ` Re:[PATCH " joshua
2024-01-11 10:55 ` juzhe.zhong
2024-01-11 14:11 ` Re:Re:[PATCH " joshua
2024-01-11 22:59 ` Re:[PATCH " 钟居哲
2024-01-11 23:22 ` 钟居哲
2024-01-12 0:49 ` 回复:Re:[PATCH " joshua
2024-01-12 1:08 ` 回复:[PATCH " juzhe.zhong
2024-01-12 1:14 ` juzhe.zhong
2024-01-12 3:26 ` Re:Re:[PATCH " joshua
2024-01-03 2:37 ` [PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-03 7:54 ` Jun Sha (Joshua)
2024-01-10 6:02 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10 6:37 ` juzhe.zhong
2024-01-10 6:51 ` Jun Sha (Joshua)
2024-01-10 6:53 ` juzhe.zhong
2024-01-10 13:36 ` Robin Dapp
2024-01-10 13:43 ` 钟居哲
2024-01-11 2:40 ` joshua [this message]
2024-01-11 2:39 ` Jun Sha (Joshua)
2024-01-11 2:46 ` juzhe.zhong
2024-01-11 8:12 ` Robin Dapp
2024-01-03 2:39 ` [PATCH v4] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-03 3:05 ` Kito Cheng
2024-01-03 7:55 ` Jun Sha (Joshua)
2024-01-12 3:18 ` [PATCH v5] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2024-01-12 3:20 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-18 9:50 ` Kito Cheng
2024-01-12 3:21 ` [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-12 3:22 ` [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-12 3:22 ` [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-12 7:32 ` juzhe.zhong
2024-01-12 3:23 ` [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-12 7:32 ` juzhe.zhong
2024-01-12 3:24 ` [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-12 7:32 ` juzhe.zhong
2024-01-18 14:43 ` [PATCH v5] RISC-V: Support XTheadVector extension Christoph Müllner
2024-01-19 20:03 ` Jeff Law
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