From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com,
christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai,
"Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>,
Jin Ma <jinma@linux.alibaba.com>,
Xianmiao Qu <cooper.qu@linux.alibaba.com>
Subject: [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions
Date: Fri, 12 Jan 2024 11:23:21 +0800 [thread overview]
Message-ID: <20240112032321.1821-1-cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <20240112031840.1556-1-cooper.joshua@linux.alibaba.com>
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we add an attribute "spec_restriction" to disable
some alternatives for xtheadvector.
gcc/ChangeLog:
* config/riscv/riscv.md (none,thv,rvv):
(no,yes): Add an attribute to disable alternative
for xtheadvector or RVV1.0.
* config/riscv/vector.md:
Disable alternatives that destination register overlaps
source register group for xtheadvector.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/riscv.md | 22 +++
gcc/config/riscv/vector.md | 314 +++++++++++++++++++++----------------
2 files changed, 202 insertions(+), 134 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..23fc32d5cb2 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,25 @@
]
(const_string "yes")))
+;; This attribute marks the alternatives not matching the constraints
+;; described in spec as disabled.
+(define_attr "spec_restriction" "none,thv,rvv"
+ (const_string "none"))
+
+(define_attr "spec_restriction_disabled" "no,yes"
+ (cond [(eq_attr "spec_restriction" "none")
+ (const_string "no")
+
+ (and (eq_attr "spec_restriction" "thv")
+ (match_test "TARGET_XTHEADVECTOR"))
+ (const_string "yes")
+
+ (and (eq_attr "spec_restriction" "rvv")
+ (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
;; Attribute to control enable or disable instructions.
(define_attr "enabled" "no,yes"
(cond [
@@ -590,6 +609,9 @@
(eq_attr "group_overlap_valid" "no")
(const_string "no")
+
+ (eq_attr "spec_restriction_disabled" "yes")
+ (const_string "no")
]
(const_string "yes")))
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3eb6daafbc2..c79416cf0d3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3260,7 +3260,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none,none")])
(define_insn "@pred_msbc<mode>"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
@@ -3279,7 +3280,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,thv,none")])
(define_insn "@pred_madc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3299,7 +3301,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "@pred_msbc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3319,7 +3322,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_expand "@pred_madc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3368,7 +3372,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "*pred_madc<mode>_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3389,7 +3394,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_expand "@pred_msbc<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3438,7 +3444,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "*pred_msbc<mode>_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3459,7 +3466,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "4")
- (set (attr "avl_type_idx") (const_int 5))])
+ (set (attr "avl_type_idx") (const_int 5))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "@pred_madc<mode>_overflow"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
@@ -3477,7 +3485,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none,none")])
(define_insn "@pred_msbc<mode>_overflow"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
@@ -3495,7 +3504,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,thv,none,none")])
(define_insn "@pred_madc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3514,7 +3524,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "@pred_msbc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3533,7 +3544,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
(define_expand "@pred_madc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3580,7 +3592,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "*pred_madc<mode>_overflow_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3600,7 +3613,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
(define_expand "@pred_msbc<mode>_overflow_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -3647,7 +3661,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
(define_insn "*pred_msbc<mode>_overflow_extended_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
@@ -3667,7 +3682,8 @@
[(set_attr "type" "vicalu")
(set_attr "mode" "<MODE>")
(set_attr "vl_op_idx" "3")
- (set (attr "avl_type_idx") (const_int 4))])
+ (set (attr "avl_type_idx") (const_int 4))
+ (set_attr "spec_restriction" "thv,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer unary operations
@@ -3987,7 +4003,8 @@
"TARGET_VECTOR"
"vn<insn>.w%o4\t%0,%3,%v4%p1"
[(set_attr "type" "vnshift")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "spec_restriction" "none,none,thv,thv,none,thv,none,none,none,thv,none,none")])
(define_insn "@pred_narrow_<optab><mode>_scalar"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -4008,7 +4025,8 @@
"TARGET_VECTOR"
"vn<insn>.w%o4\t%0,%3,%4%p1"
[(set_attr "type" "vnshift")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
;; vncvt.x.x.w
(define_insn "@pred_trunc<mode>"
@@ -4032,7 +4050,8 @@
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
+ (set (attr "avl_type_idx") (const_int 7))
+ (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated fixed-point operations
@@ -4438,7 +4457,8 @@
"TARGET_VECTOR"
"vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
[(set_attr "type" "vnclip")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "spec_restriction" "thv,thv,thv,thv,thv,thv,none,none,thv,thv,none,none")])
(define_insn "@pred_narrow_clip<v_su><mode>_scalar"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -4460,7 +4480,8 @@
"TARGET_VECTOR"
"vnclip<v_su>.w%o4\t%0,%3,%4%p1"
[(set_attr "type" "vnclip")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "spec_restriction" "thv,thv,thv,thv,none,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer comparison operations
@@ -4511,23 +4532,24 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "comparison_except_ltge_operator"
- [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
- (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
+ (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.v%o5\t%0,%4,%v5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_cmp<mode>_narrow"
@@ -4547,7 +4569,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.v%o5\t%0,%4,%v5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
(define_expand "@pred_ltge<mode>"
[(set (match_operand:<VM> 0 "register_operand")
@@ -4591,23 +4614,24 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_ltge<mode>"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "ltge_operator"
- [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
- (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
+ (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj, vr, vr, vj, vj")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.v%o5\t%0,%4,%v5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_ltge<mode>_narrow"
@@ -4627,7 +4651,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.v%o5\t%0,%4,%v5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
(define_expand "@pred_cmp<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -4673,24 +4698,25 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "comparison_except_eqge_operator"
- [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")
+ [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r"))])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_cmp<mode>_scalar_narrow"
@@ -4711,7 +4737,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
(define_expand "@pred_eqne<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -4757,24 +4784,25 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "equality_operator"
[(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r"))
- (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
+ (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_eqne<mode>_scalar_narrow"
@@ -4795,7 +4823,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
;; we need to deal with SEW = 64 in RV32 system.
@@ -4922,24 +4951,25 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "comparison_except_eqge_operator"
- [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
+ [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r"))])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_cmp<mode>_scalar_narrow"
@@ -4960,28 +4990,30 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "equality_operator"
[(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r"))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
+ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_eqne<mode>_scalar_narrow"
@@ -5002,7 +5034,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
(define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
@@ -5031,25 +5064,26 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_extended_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "comparison_except_eqge_operator"
- [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
+ [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r")))])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
(define_insn "*pred_cmp<mode>_extended_scalar_narrow"
[(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
@@ -5070,7 +5104,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
(define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
@@ -5099,25 +5134,26 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_extended_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "equality_operator"
[(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r")))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))
+ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
(define_insn "*pred_eqne<mode>_extended_scalar_narrow"
[(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
@@ -5138,7 +5174,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
"vms%B3.vx\t%0,%4,%5%p1"
[(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
;; GE, vmsge.vx/vmsgeu.vx
;;
@@ -7327,23 +7364,24 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "signed_order_operator"
- [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
- (match_operand:V_VLSF 5 "register_operand" " vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:V_VLSF 5 "register_operand" " vr, vr, vr, vr")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
(define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
@@ -7386,7 +7424,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vmf%B3.vv\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
(define_expand "@pred_cmp<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -7432,24 +7471,25 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "signed_order_operator"
- [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
+ [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f"))])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_cmp<mode>_scalar_narrow"
@@ -7470,7 +7510,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
(define_expand "@pred_eqne<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand")
@@ -7516,24 +7557,25 @@
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
+ [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
(if_then_else:<VM>
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(match_operator:<VM> 3 "equality_operator"
[(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
+ (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
+ (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
;; We use early-clobber for source LMUL > dest LMUL.
(define_insn "*pred_eqne<mode>_scalar_narrow"
@@ -7554,7 +7596,8 @@
"TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
"vmf%B3.vf\t%0,%4,%5%p1"
[(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "spec_restriction" "none,thv,thv,none,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point merge
@@ -7774,7 +7817,8 @@
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
+ (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7816,7 +7860,8 @@
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
+ (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7839,7 +7884,8 @@
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
+ (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
--
2.17.1
next prev parent reply other threads:[~2024-01-12 3:23 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-29 4:03 [PATCH v4] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2023-12-29 4:05 ` [PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-29 4:06 ` [PATCH v4] RISC-V: Change csr_operand into Jun Sha (Joshua)
2023-12-29 4:10 ` [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns Jun Sha (Joshua)
2024-01-02 1:35 ` juzhe.zhong
2024-01-02 19:50 ` Christoph Müllner
2024-01-02 1:35 ` [PATCH v4] RISC-V: Change csr_operand into juzhe.zhong
2023-12-29 4:13 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-04 9:28 ` Jun Sha (Joshua)
2023-12-29 4:19 ` [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-31 17:43 ` Jeff Law
2024-01-01 22:57 ` 钟居哲
2024-01-03 2:54 ` Andrew Pinski
2024-01-03 3:06 ` juzhe.zhong
2024-01-03 3:19 ` Andrew Pinski
2024-01-03 3:25 ` juzhe.zhong
2024-01-03 3:32 ` Andrew Pinski
2024-01-03 3:32 ` Kito Cheng
2024-01-04 9:15 ` Re：Re: " joshua
2024-01-04 9:18 ` juzhe.zhong
2024-01-04 10:04 ` Christoph Müllner
2024-01-08 2:11 ` Re：Re: " joshua
2024-01-08 3:06 ` Kito Cheng
2024-01-08 3:17 ` Re：Re: " joshua
2024-01-08 3:40 ` Kito Cheng
2024-01-10 3:01 ` Re：Re: " joshua
2024-01-03 6:08 ` Jun Sha (Joshua)
2024-01-08 23:04 ` 钟居哲
2024-01-09 17:49 ` Jeff Law
2024-01-09 22:35 ` 钟居哲
2023-12-29 4:21 ` [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-02 2:00 ` juzhe.zhong
2024-01-02 3:03 ` Re：[PATCH " joshua
2024-01-02 3:10 ` juzhe.zhong
2024-01-02 3:40 ` Re：Re：[PATCH " joshua
2024-01-02 3:41 ` Re：[PATCH " juzhe.zhong
2024-01-02 9:48 ` joshua
2024-01-02 9:52 ` juzhe.zhong
2024-01-02 12:39 ` [PATCH " Jun Sha (Joshua)
2024-01-03 3:11 ` Kito Cheng
2024-01-03 6:15 ` Jun Sha (Joshua)
2024-01-04 2:29 ` Jun Sha (Joshua)
2024-01-09 3:18 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-09 22:33 ` 钟居哲
2024-01-10 2:22 ` Jun Sha (Joshua)
2024-01-10 2:34 ` juzhe.zhong
2024-01-10 2:57 ` Re：[PATCH " joshua
2024-01-10 3:02 ` juzhe.zhong
2024-01-10 6:54 ` juzhe.zhong
2024-01-10 7:01 ` juzhe.zhong
2024-01-10 7:16 ` Re：Re：[PATCH " joshua
2024-01-10 7:17 ` Re：[PATCH " juzhe.zhong
2024-01-10 7:26 ` 回复：Re：[PATCH " joshua
2024-01-10 7:31 ` 回复：[PATCH " juzhe.zhong
2024-01-10 7:28 ` Re：Re：[PATCH " joshua
2024-01-11 11:03 ` [PATCH " Jun Sha (Joshua)
2024-01-08 23:08 ` [PATCH v4] " 钟居哲
2024-01-09 2:12 ` Re：[PATCH " joshua
2024-01-09 3:23 ` joshua
2023-12-29 4:21 ` [PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-04 2:34 ` [PATCH v4] " Jun Sha (Joshua)
2024-01-10 9:27 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10 9:35 ` juzhe.zhong
2024-01-10 9:55 ` Re：[PATCH " joshua
2024-01-10 10:03 ` juzhe.zhong
2024-01-10 10:57 ` Re：Re：[PATCH " joshua
2024-01-10 9:31 ` [PATCH " Jun Sha (Joshua)
2024-01-11 8:46 ` Jun Sha (Joshua)
2024-01-11 9:07 ` juzhe.zhong
2024-01-11 9:11 ` Re：[PATCH " joshua
2024-01-11 9:14 ` joshua
2024-01-11 9:17 ` juzhe.zhong
2024-01-11 9:21 ` Re：Re：[PATCH " joshua
2024-01-11 9:24 ` Re：[PATCH " juzhe.zhong
2024-01-11 9:29 ` Re：Re：[PATCH " joshua
2024-01-11 9:32 ` Re：[PATCH " juzhe.zhong
2024-01-11 9:38 ` Re：Re：[PATCH " joshua
2024-01-11 12:05 ` joshua
2024-01-11 12:13 ` Re：[PATCH " juzhe.zhong
2024-01-11 12:18 ` Re：Re：[PATCH " joshua
2024-01-11 12:28 ` Re：[PATCH " juzhe.zhong
2024-01-11 12:31 ` Re：Re：[PATCH " joshua
2024-01-11 12:33 ` Re：[PATCH " juzhe.zhong
2024-01-11 12:36 ` Re：Re：[PATCH " joshua
2024-01-11 9:26 ` joshua
2024-01-11 9:28 ` Re：[PATCH " juzhe.zhong
2024-01-11 9:35 ` Re：Re：[PATCH " joshua
2024-01-11 9:54 ` Re：[PATCH " joshua
2024-01-11 9:52 ` [PATCH " Jun Sha (Joshua)
2024-01-11 9:57 ` juzhe.zhong
2024-01-11 10:54 ` Re：[PATCH " joshua
2024-01-11 10:55 ` juzhe.zhong
2024-01-11 14:11 ` Re：Re：[PATCH " joshua
2024-01-11 22:59 ` Re：[PATCH " 钟居哲
2024-01-11 23:22 ` 钟居哲
2024-01-12 0:49 ` 回复：Re：[PATCH " joshua
2024-01-12 1:08 ` 回复：[PATCH " juzhe.zhong
2024-01-12 1:14 ` juzhe.zhong
2024-01-12 3:26 ` Re：Re：[PATCH " joshua
2024-01-03 2:37 ` [PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-03 7:54 ` Jun Sha (Joshua)
2024-01-10 6:02 ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10 6:37 ` juzhe.zhong
2024-01-10 6:51 ` Jun Sha (Joshua)
2024-01-10 6:53 ` juzhe.zhong
2024-01-10 13:36 ` Robin Dapp
2024-01-10 13:43 ` 钟居哲
2024-01-11 2:40 ` Re：Re: " joshua
2024-01-11 2:39 ` Jun Sha (Joshua)
2024-01-11 2:46 ` juzhe.zhong
2024-01-11 8:12 ` Robin Dapp
2024-01-03 2:39 ` [PATCH v4] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-03 3:05 ` Kito Cheng
2024-01-03 7:55 ` Jun Sha (Joshua)
2024-01-12 3:18 ` [PATCH v5] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2024-01-12 3:20 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-18 9:50 ` Kito Cheng
2024-01-12 3:21 ` [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-12 3:22 ` [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-12 7:31 ` juzhe.zhong
2024-01-12 3:22 ` [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-12 7:32 ` juzhe.zhong
2024-01-12 3:23 ` Jun Sha (Joshua) [this message]
2024-01-12 7:32 ` [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions juzhe.zhong
2024-01-12 3:24 ` [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-12 7:32 ` juzhe.zhong
2024-01-18 14:43 ` [PATCH v5] RISC-V: Support XTheadVector extension Christoph Müllner
2024-01-19 20:03 ` Jeff Law
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