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From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
	philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com,
	christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai,
	kito.cheng@gmail.com,
	"Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>,
	Jin Ma <jinma@linux.alibaba.com>,
	Xianmiao Qu <cooper.qu@linux.alibaba.com>
Subject: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
Date: Fri, 12 Jan 2024 11:20:29 +0800	[thread overview]
Message-ID: <20240112032029.1609-1-cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <20240112031840.1556-1-cooper.joshua@linux.alibaba.com>

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc
	(riscv_subset_list::parse): Add new vendor extension.
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Add test marco.
	* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
	* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/common/config/riscv/riscv-common.cc       | 23 +++++++++++++++++++
 gcc/config/riscv/riscv-c.cc                   |  8 +++++--
 gcc/config/riscv/riscv.opt                    |  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c     | 11 +++++++++
 .../gcc.target/riscv/rvv/xtheadvector.c       | 13 +++++++++++
 5 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..449722070d4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -368,6 +368,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
       if (lookup ("zcmp"))
 	error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
     }
+
+  if ((lookup ("v") || lookup ("zve32x")
+	 || lookup ("zve64x") || lookup ("zve32f")
+	 || lookup ("zve64f") || lookup ("zve64d")
+	 || lookup ("zvl32b") || lookup ("zvl64b")
+	 || lookup ("zvl128b") || lookup ("zvfh"))
+	 && lookup ("xtheadvector"))
+    error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+		   "extension or its sub-extensions", m_arch);
 }
 
 /* Parsing function for multi-letter extensions.
@@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
+  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
+  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
+  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
+  {"xtheadvector",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16},
+  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
+  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
+  {"xtheadvector",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B},
+  {"xtheadvector",  &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"xtheadvector",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
+  {"xtheadvector",  &gcc_options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  &gcc_options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ba60cd8b555..422ddc2c308 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 				     riscv_ext_version_value (0, 11));
     }
 
+   if (TARGET_XTHEADVECTOR)
+     builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+				     riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
@@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *)
     {
       if (!TARGET_VECTOR)
 	{
-	  error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-		 "enabled",
+	  error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+		 "'XTHEADVECTOR' extension enabled",
 		 name);
 	  return;
 	}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..bb18a22b693 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)    Var(riscv_xthead_subext)
 
+Mask(XTHEADVECTOR)  Var(riscv_xthead_subext)
+
 TargetVariable
 int riscv_xventana_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
new file mode 100644
index 00000000000..550b9039a06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_th_v_intrinsic != 11000
+#error "__riscv_th_v_intrinsic"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
new file mode 100644
index 00000000000..8ad370172e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadvector
+#error "Feature macro not defined"
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
-- 
2.17.1


  reply	other threads:[~2024-01-12  3:20 UTC|newest]

Thread overview: 130+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-29  4:03 [PATCH v4] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2023-12-29  4:05 ` [PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-29  4:06 ` [PATCH v4] RISC-V: Change csr_operand into Jun Sha (Joshua)
2023-12-29  4:10   ` [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns Jun Sha (Joshua)
2024-01-02  1:35     ` juzhe.zhong
2024-01-02 19:50       ` Christoph Müllner
2024-01-02  1:35   ` [PATCH v4] RISC-V: Change csr_operand into juzhe.zhong
2023-12-29  4:13 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-04  9:28   ` Jun Sha (Joshua)
2023-12-29  4:19 ` [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-31 17:43   ` Jeff Law
2024-01-01 22:57     ` 钟居哲
2024-01-03  2:54       ` Andrew Pinski
2024-01-03  3:06         ` juzhe.zhong
2024-01-03  3:19           ` Andrew Pinski
2024-01-03  3:25             ` juzhe.zhong
2024-01-03  3:32               ` Andrew Pinski
2024-01-03  3:32               ` Kito Cheng
2024-01-04  9:15       ` Re:Re: " joshua
2024-01-04  9:18         ` juzhe.zhong
2024-01-04 10:04           ` Christoph Müllner
2024-01-08  2:11           ` Re:Re: " joshua
2024-01-08  3:06             ` Kito Cheng
2024-01-08  3:17               ` Re:Re: " joshua
2024-01-08  3:40                 ` Kito Cheng
2024-01-10  3:01                   ` Re:Re: " joshua
2024-01-03  6:08   ` Jun Sha (Joshua)
2024-01-08 23:04     ` 钟居哲
2024-01-09 17:49       ` Jeff Law
2024-01-09 22:35         ` 钟居哲
2023-12-29  4:21 ` [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-02  2:00   ` juzhe.zhong
2024-01-02  3:03     ` Re:[PATCH " joshua
2024-01-02  3:10       ` juzhe.zhong
2024-01-02  3:40         ` Re:Re:[PATCH " joshua
2024-01-02  3:41           ` Re:[PATCH " juzhe.zhong
2024-01-02  9:48     ` joshua
2024-01-02  9:52       ` juzhe.zhong
2024-01-02 12:39   ` [PATCH " Jun Sha (Joshua)
2024-01-03  3:11     ` Kito Cheng
2024-01-03  6:15     ` Jun Sha (Joshua)
2024-01-04  2:29       ` Jun Sha (Joshua)
2024-01-09  3:18         ` [PATCH v5] " Jun Sha (Joshua)
2024-01-09 22:33           ` 钟居哲
2024-01-10  2:22           ` Jun Sha (Joshua)
2024-01-10  2:34             ` juzhe.zhong
2024-01-10  2:57               ` Re:[PATCH " joshua
2024-01-10  3:02                 ` juzhe.zhong
2024-01-10  6:54                 ` juzhe.zhong
2024-01-10  7:01                 ` juzhe.zhong
2024-01-10  7:16                   ` Re:Re:[PATCH " joshua
2024-01-10  7:17                     ` Re:[PATCH " juzhe.zhong
2024-01-10  7:26                       ` 回复:Re:[PATCH " joshua
2024-01-10  7:31                         ` 回复:[PATCH " juzhe.zhong
2024-01-10  7:28                       ` Re:Re:[PATCH " joshua
2024-01-11 11:03             ` [PATCH " Jun Sha (Joshua)
2024-01-08 23:08       ` [PATCH v4] " 钟居哲
2024-01-09  2:12         ` Re:[PATCH " joshua
2024-01-09  3:23         ` joshua
2023-12-29  4:21 ` [PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-04  2:34   ` [PATCH v4] " Jun Sha (Joshua)
2024-01-10  9:27     ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10  9:35       ` juzhe.zhong
2024-01-10  9:55         ` Re:[PATCH " joshua
2024-01-10 10:03           ` juzhe.zhong
2024-01-10 10:57             ` Re:Re:[PATCH " joshua
2024-01-10  9:31     ` [PATCH " Jun Sha (Joshua)
2024-01-11  8:46       ` Jun Sha (Joshua)
2024-01-11  9:07         ` juzhe.zhong
2024-01-11  9:11           ` Re:[PATCH " joshua
2024-01-11  9:14             ` joshua
2024-01-11  9:17               ` juzhe.zhong
2024-01-11  9:21                 ` Re:Re:[PATCH " joshua
2024-01-11  9:24                   ` Re:[PATCH " juzhe.zhong
2024-01-11  9:29                     ` Re:Re:[PATCH " joshua
2024-01-11  9:32                       ` Re:[PATCH " juzhe.zhong
2024-01-11  9:38                         ` Re:Re:[PATCH " joshua
2024-01-11 12:05                         ` joshua
2024-01-11 12:13                           ` Re:[PATCH " juzhe.zhong
2024-01-11 12:18                             ` Re:Re:[PATCH " joshua
2024-01-11 12:28                               ` Re:[PATCH " juzhe.zhong
2024-01-11 12:31                                 ` Re:Re:[PATCH " joshua
2024-01-11 12:33                                   ` Re:[PATCH " juzhe.zhong
2024-01-11 12:36                                     ` Re:Re:[PATCH " joshua
2024-01-11  9:26                 ` joshua
2024-01-11  9:28                   ` Re:[PATCH " juzhe.zhong
2024-01-11  9:35                     ` Re:Re:[PATCH " joshua
2024-01-11  9:54           ` Re:[PATCH " joshua
2024-01-11  9:52       ` [PATCH " Jun Sha (Joshua)
2024-01-11  9:57         ` juzhe.zhong
2024-01-11 10:54           ` Re:[PATCH " joshua
2024-01-11 10:55             ` juzhe.zhong
2024-01-11 14:11               ` Re:Re:[PATCH " joshua
2024-01-11 22:59                 ` Re:[PATCH " 钟居哲
2024-01-11 23:22                 ` 钟居哲
2024-01-12  0:49                   ` 回复:Re:[PATCH " joshua
2024-01-12  1:08                     ` 回复:[PATCH " juzhe.zhong
2024-01-12  1:14                     ` juzhe.zhong
2024-01-12  3:26                       ` Re:Re:[PATCH " joshua
2024-01-03  2:37 ` [PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-03  7:54   ` Jun Sha (Joshua)
2024-01-10  6:02     ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10  6:37       ` juzhe.zhong
2024-01-10  6:51     ` Jun Sha (Joshua)
2024-01-10  6:53       ` juzhe.zhong
2024-01-10 13:36       ` Robin Dapp
2024-01-10 13:43         ` 钟居哲
2024-01-11  2:40           ` Re:Re: " joshua
2024-01-11  2:39       ` Jun Sha (Joshua)
2024-01-11  2:46         ` juzhe.zhong
2024-01-11  8:12           ` Robin Dapp
2024-01-03  2:39 ` [PATCH v4] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-03  3:05   ` Kito Cheng
2024-01-03  7:55   ` Jun Sha (Joshua)
2024-01-12  3:18 ` [PATCH v5] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2024-01-12  3:20   ` Jun Sha (Joshua) [this message]
2024-01-12  7:31     ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 juzhe.zhong
2024-01-18  9:50       ` Kito Cheng
2024-01-12  3:21   ` [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2024-01-12  7:31     ` juzhe.zhong
2024-01-12  3:22   ` [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-12  7:31     ` juzhe.zhong
2024-01-12  3:22   ` [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-12  7:32     ` juzhe.zhong
2024-01-12  3:23   ` [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-12  7:32     ` juzhe.zhong
2024-01-12  3:24   ` [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-12  7:32     ` juzhe.zhong
2024-01-18 14:43   ` [PATCH v5] RISC-V: Support XTheadVector extension Christoph Müllner
2024-01-19 20:03     ` Jeff Law

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