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From: "Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com,
	philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com,
	christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai,
	"Jun Sha (Joshua)" <cooper.joshua@linux.alibaba.com>,
	Jin Ma <jinma@linux.alibaba.com>,
	Xianmiao Qu <cooper.qu@linux.alibaba.com>
Subject: [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook
Date: Fri, 12 Jan 2024 11:24:04 +0800	[thread overview]
Message-ID: <20240112032404.1874-1-cooper.joshua@linux.alibaba.com> (raw)
In-Reply-To: <20240112031840.1556-1-cooper.joshua@linux.alibaba.com>

There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.

gcc/ChangeLog:

	* config/riscv/thead.cc
	(th_asm_output_opcode): Rewrite some instructions.

Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/thead.cc | 215 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 213 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index dc3aed3904d..fb088ebff02 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -27,6 +27,7 @@
 #include "backend.h"
 #include "tree.h"
 #include "rtl.h"
+#include "insn-attr.h"
 #include "explow.h"
 #include "memmodel.h"
 #include "emit-rtl.h"
@@ -890,8 +891,218 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
 {
   /* We need to add th. prefix to all the xtheadvector
      instructions here.*/
-  if (current_output_insn != NULL && p[0] == 'v')
-    fputs ("th.", asm_out_file);
+  if (current_output_insn != NULL)
+    {
+      if (get_attr_type (current_output_insn) == TYPE_VLDE ||
+	  get_attr_type (current_output_insn) == TYPE_VSTE ||
+	  get_attr_type (current_output_insn) == TYPE_VLDFF)
+	{
+	  if (strstr (p, "e8") || strstr (p, "e16") ||
+	      strstr (p, "e32") || strstr (p, "e64"))
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VSTE
+				  ? fputs ("th.vse", asm_out_file)
+				  : fputs ("th.vle", asm_out_file);
+	      if (strstr (p, "e8"))
+		return p+4;
+	      else
+		return p+5;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VLDS ||
+	  get_attr_type (current_output_insn) == TYPE_VSTS)
+	{
+	  if (strstr (p, "vle8") || strstr (p, "vse8") ||
+	      strstr (p, "vle16") || strstr (p, "vse16") ||
+	      strstr (p, "vle32") || strstr (p, "vse32") ||
+	      strstr (p, "vle64") || strstr (p, "vse64"))
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VSTS
+				  ? fputs ("th.vse", asm_out_file)
+				  : fputs ("th.vle", asm_out_file);
+	      if (strstr (p, "e8"))
+		return p+4;
+	      else
+		return p+5;
+	    }
+	  else if (strstr (p, "vlse8") || strstr (p, "vsse8") ||
+		   strstr (p, "vlse16") || strstr (p, "vsse16") ||
+		   strstr (p, "vlse32") || strstr (p, "vsse32") ||
+		   strstr (p, "vlse64") || strstr (p, "vsse64"))
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VSTS
+				  ? fputs ("th.vsse", asm_out_file)
+				  : fputs ("th.vlse", asm_out_file);
+	      if (strstr (p, "e8"))
+		return p+5;
+	      else
+		return p+6;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VLDUX ||
+	  get_attr_type (current_output_insn) == TYPE_VLDOX)
+	{
+	  if (strstr (p, "ei"))
+	    {
+	      fputs ("th.vlxe", asm_out_file);
+	      if (strstr (p, "ei8"))
+		return p+7;
+	      else
+		return p+8;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VSTUX ||
+	  get_attr_type (current_output_insn) == TYPE_VSTOX)
+	{
+	  if (strstr (p, "ei"))
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VSTUX
+				? fputs ("th.vsuxe", asm_out_file)
+				: fputs ("th.vsxe", asm_out_file);
+	      if (strstr (p, "ei8"))
+		return p+7;
+	      else
+		return p+8;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VLSEGDE ||
+	  get_attr_type (current_output_insn) == TYPE_VSSEGTE ||
+	  get_attr_type (current_output_insn) == TYPE_VLSEGDFF)
+	{
+	  get_attr_type (current_output_insn) == TYPE_VSSEGTE
+				? fputs ("th.vsseg", asm_out_file)
+				: fputs ("th.vlseg", asm_out_file);
+	  asm_fprintf (asm_out_file, "%c", p[5]);
+	  fputs ("e", asm_out_file);
+	  if (strstr (p, "e8"))
+	    return p+8;
+	  else
+	    return p+9;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VLSEGDS ||
+	  get_attr_type (current_output_insn) == TYPE_VSSEGTS)
+	{
+	  get_attr_type (current_output_insn) == TYPE_VSSEGTS
+				? fputs ("th.vssseg", asm_out_file)
+				: fputs ("th.vlsseg", asm_out_file);
+	  asm_fprintf (asm_out_file, "%c", p[6]);
+	  fputs ("e", asm_out_file);
+	  if (strstr (p, "e8"))
+	    return p+9;
+	  else
+	    return p+10;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VLSEGDUX ||
+	  get_attr_type (current_output_insn) == TYPE_VLSEGDOX)
+	{
+	  fputs ("th.vlxseg", asm_out_file);
+	  asm_fprintf (asm_out_file, "%c", p[7]);
+	  fputs ("e", asm_out_file);
+	  if (strstr (p, "ei8"))
+	    return p+11;
+	  else
+	    return p+12;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VSSEGTUX ||
+	  get_attr_type (current_output_insn) == TYPE_VSSEGTOX)
+	{
+	  fputs ("th.vsxseg", asm_out_file);
+	  asm_fprintf (asm_out_file, "%c", p[7]);
+	  fputs ("e", asm_out_file);
+	  if (strstr (p, "ei8"))
+	    return p+11;
+	  else
+	    return p+12;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VNSHIFT)
+	{
+	  if (strstr (p, "vncvt"))
+	    {
+	      fputs ("th.vncvt.x.x.v", asm_out_file);
+	      return p+11;
+	    }
+
+	  strstr (p, "vnsrl") ? fputs ("th.vnsrl.v", asm_out_file)
+			      : fputs ("th.vnsra.v", asm_out_file);
+	  return p+7;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VNCLIP)
+	{
+	  if (strstr (p, "vnclipu"))
+	    {
+	      fputs ("th.vnclipu.v", asm_out_file);
+	      return p+9;
+	    }
+	  else
+	    {
+	      fputs ("th.vnclip.v", asm_out_file);
+	      return p+8;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VMPOP)
+	{
+	  fputs ("th.vmpopc", asm_out_file);
+	  return p+5;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VMFFS)
+	{
+	  fputs ("th.vmfirst", asm_out_file);
+	  return p+6;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VFNCVTFTOI ||
+	  get_attr_type (current_output_insn) == TYPE_VFNCVTITOF)
+	{
+	  if (strstr (p, "xu"))
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VFNCVTFTOI
+			   ? fputs ("th.vfncvt.xu.f.v", asm_out_file)
+			   : fputs ("th.vfncvt.f.xu.v", asm_out_file);
+	      return p+13;
+	}
+	  else
+	    {
+	      get_attr_type (current_output_insn) == TYPE_VFNCVTFTOI
+			   ? fputs ("th.vfncvt.x.f.v", asm_out_file)
+			   : fputs ("th.vfncvt.f.x.v", asm_out_file);
+	      return p+12;
+	    }
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VFNCVTFTOF)
+	{
+	  fputs ("th.vfncvt.f.f.v", asm_out_file);
+	  return p+12;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VFREDU
+	  && strstr (p, "sum"))
+	{
+	  fputs ("th.vfredsum", asm_out_file);
+	  return p+9;
+	}
+
+      if (get_attr_type (current_output_insn) == TYPE_VFWREDU
+	  && strstr (p, "sum"))
+	{
+	  fputs ("th.vfwredsum", asm_out_file);
+	  return p+10;
+	}
+
+      if (p[0] == 'v')
+	fputs ("th.", asm_out_file);
+    }
 
   return p;
 }
-- 
2.17.1


  parent reply	other threads:[~2024-01-12  3:24 UTC|newest]

Thread overview: 130+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-29  4:03 [PATCH v4] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2023-12-29  4:05 ` [PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc Jun Sha (Joshua)
2023-12-29  4:06 ` [PATCH v4] RISC-V: Change csr_operand into Jun Sha (Joshua)
2023-12-29  4:10   ` [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns Jun Sha (Joshua)
2024-01-02  1:35     ` juzhe.zhong
2024-01-02 19:50       ` Christoph Müllner
2024-01-02  1:35   ` [PATCH v4] RISC-V: Change csr_operand into juzhe.zhong
2023-12-29  4:13 ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-04  9:28   ` Jun Sha (Joshua)
2023-12-29  4:19 ` [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2023-12-31 17:43   ` Jeff Law
2024-01-01 22:57     ` 钟居哲
2024-01-03  2:54       ` Andrew Pinski
2024-01-03  3:06         ` juzhe.zhong
2024-01-03  3:19           ` Andrew Pinski
2024-01-03  3:25             ` juzhe.zhong
2024-01-03  3:32               ` Andrew Pinski
2024-01-03  3:32               ` Kito Cheng
2024-01-04  9:15       ` Re:Re: " joshua
2024-01-04  9:18         ` juzhe.zhong
2024-01-04 10:04           ` Christoph Müllner
2024-01-08  2:11           ` Re:Re: " joshua
2024-01-08  3:06             ` Kito Cheng
2024-01-08  3:17               ` Re:Re: " joshua
2024-01-08  3:40                 ` Kito Cheng
2024-01-10  3:01                   ` Re:Re: " joshua
2024-01-03  6:08   ` Jun Sha (Joshua)
2024-01-08 23:04     ` 钟居哲
2024-01-09 17:49       ` Jeff Law
2024-01-09 22:35         ` 钟居哲
2023-12-29  4:21 ` [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-02  2:00   ` juzhe.zhong
2024-01-02  3:03     ` Re:[PATCH " joshua
2024-01-02  3:10       ` juzhe.zhong
2024-01-02  3:40         ` Re:Re:[PATCH " joshua
2024-01-02  3:41           ` Re:[PATCH " juzhe.zhong
2024-01-02  9:48     ` joshua
2024-01-02  9:52       ` juzhe.zhong
2024-01-02 12:39   ` [PATCH " Jun Sha (Joshua)
2024-01-03  3:11     ` Kito Cheng
2024-01-03  6:15     ` Jun Sha (Joshua)
2024-01-04  2:29       ` Jun Sha (Joshua)
2024-01-09  3:18         ` [PATCH v5] " Jun Sha (Joshua)
2024-01-09 22:33           ` 钟居哲
2024-01-10  2:22           ` Jun Sha (Joshua)
2024-01-10  2:34             ` juzhe.zhong
2024-01-10  2:57               ` Re:[PATCH " joshua
2024-01-10  3:02                 ` juzhe.zhong
2024-01-10  6:54                 ` juzhe.zhong
2024-01-10  7:01                 ` juzhe.zhong
2024-01-10  7:16                   ` Re:Re:[PATCH " joshua
2024-01-10  7:17                     ` Re:[PATCH " juzhe.zhong
2024-01-10  7:26                       ` 回复:Re:[PATCH " joshua
2024-01-10  7:31                         ` 回复:[PATCH " juzhe.zhong
2024-01-10  7:28                       ` Re:Re:[PATCH " joshua
2024-01-11 11:03             ` [PATCH " Jun Sha (Joshua)
2024-01-08 23:08       ` [PATCH v4] " 钟居哲
2024-01-09  2:12         ` Re:[PATCH " joshua
2024-01-09  3:23         ` joshua
2023-12-29  4:21 ` [PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-04  2:34   ` [PATCH v4] " Jun Sha (Joshua)
2024-01-10  9:27     ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10  9:35       ` juzhe.zhong
2024-01-10  9:55         ` Re:[PATCH " joshua
2024-01-10 10:03           ` juzhe.zhong
2024-01-10 10:57             ` Re:Re:[PATCH " joshua
2024-01-10  9:31     ` [PATCH " Jun Sha (Joshua)
2024-01-11  8:46       ` Jun Sha (Joshua)
2024-01-11  9:07         ` juzhe.zhong
2024-01-11  9:11           ` Re:[PATCH " joshua
2024-01-11  9:14             ` joshua
2024-01-11  9:17               ` juzhe.zhong
2024-01-11  9:21                 ` Re:Re:[PATCH " joshua
2024-01-11  9:24                   ` Re:[PATCH " juzhe.zhong
2024-01-11  9:29                     ` Re:Re:[PATCH " joshua
2024-01-11  9:32                       ` Re:[PATCH " juzhe.zhong
2024-01-11  9:38                         ` Re:Re:[PATCH " joshua
2024-01-11 12:05                         ` joshua
2024-01-11 12:13                           ` Re:[PATCH " juzhe.zhong
2024-01-11 12:18                             ` Re:Re:[PATCH " joshua
2024-01-11 12:28                               ` Re:[PATCH " juzhe.zhong
2024-01-11 12:31                                 ` Re:Re:[PATCH " joshua
2024-01-11 12:33                                   ` Re:[PATCH " juzhe.zhong
2024-01-11 12:36                                     ` Re:Re:[PATCH " joshua
2024-01-11  9:26                 ` joshua
2024-01-11  9:28                   ` Re:[PATCH " juzhe.zhong
2024-01-11  9:35                     ` Re:Re:[PATCH " joshua
2024-01-11  9:54           ` Re:[PATCH " joshua
2024-01-11  9:52       ` [PATCH " Jun Sha (Joshua)
2024-01-11  9:57         ` juzhe.zhong
2024-01-11 10:54           ` Re:[PATCH " joshua
2024-01-11 10:55             ` juzhe.zhong
2024-01-11 14:11               ` Re:Re:[PATCH " joshua
2024-01-11 22:59                 ` Re:[PATCH " 钟居哲
2024-01-11 23:22                 ` 钟居哲
2024-01-12  0:49                   ` 回复:Re:[PATCH " joshua
2024-01-12  1:08                     ` 回复:[PATCH " juzhe.zhong
2024-01-12  1:14                     ` juzhe.zhong
2024-01-12  3:26                       ` Re:Re:[PATCH " joshua
2024-01-03  2:37 ` [PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-03  7:54   ` Jun Sha (Joshua)
2024-01-10  6:02     ` [PATCH v5] " Jun Sha (Joshua)
2024-01-10  6:37       ` juzhe.zhong
2024-01-10  6:51     ` Jun Sha (Joshua)
2024-01-10  6:53       ` juzhe.zhong
2024-01-10 13:36       ` Robin Dapp
2024-01-10 13:43         ` 钟居哲
2024-01-11  2:40           ` Re:Re: " joshua
2024-01-11  2:39       ` Jun Sha (Joshua)
2024-01-11  2:46         ` juzhe.zhong
2024-01-11  8:12           ` Robin Dapp
2024-01-03  2:39 ` [PATCH v4] RISC-V: Rewrite some instructions using ASM targethook Jun Sha (Joshua)
2024-01-03  3:05   ` Kito Cheng
2024-01-03  7:55   ` Jun Sha (Joshua)
2024-01-12  3:18 ` [PATCH v5] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
2024-01-12  3:20   ` [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 Jun Sha (Joshua)
2024-01-12  7:31     ` juzhe.zhong
2024-01-18  9:50       ` Kito Cheng
2024-01-12  3:21   ` [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector Jun Sha (Joshua)
2024-01-12  7:31     ` juzhe.zhong
2024-01-12  3:22   ` [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector Jun Sha (Joshua)
2024-01-12  7:31     ` juzhe.zhong
2024-01-12  3:22   ` [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics Jun Sha (Joshua)
2024-01-12  7:32     ` juzhe.zhong
2024-01-12  3:23   ` [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions Jun Sha (Joshua)
2024-01-12  7:32     ` juzhe.zhong
2024-01-12  3:24   ` Jun Sha (Joshua) [this message]
2024-01-12  7:32     ` [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook juzhe.zhong
2024-01-18 14:43   ` [PATCH v5] RISC-V: Support XTheadVector extension Christoph Müllner
2024-01-19 20:03     ` Jeff Law

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