* [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension @ 2023-11-09 11:57 Mary Bennett 2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 0 siblings, 2 replies; 12+ messages in thread From: Mary Bennett @ 2023-11-09 11:57 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> RISC-V: Add support for XCVsimd extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 9 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../riscv/cv-simd-abs-b-compile-1.c | 11 + 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mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c 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gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P 2023-11-09 11:57 [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett @ 2023-11-09 11:57 ` Mary Bennett 2023-12-05 16:12 ` Kito Cheng 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 1 sibling, 1 reply; 12+ messages in thread From: Mary Bennett @ 2023-11-09 11:57 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 9 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + .../riscv/cv-simd-add-div4-compile-1.c | 11 + .../riscv/cv-simd-add-div8-compile-1.c | 11 + .../riscv/cv-simd-add-h-compile-1.c | 11 + .../riscv/cv-simd-add-sc-b-compile-1.c | 30 + .../riscv/cv-simd-add-sc-h-compile-1.c | 30 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11 + .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpgt-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpgt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgtu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmple-b-compile-1.c | 11 + .../riscv/cv-simd-cmple-h-compile-1.c | 11 + .../riscv/cv-simd-cmple-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmple-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpleu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpleu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmplt-b-compile-1.c | 11 + .../riscv/cv-simd-cmplt-h-compile-1.c | 11 + .../riscv/cv-simd-cmplt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmplt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpltu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpltu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpne-b-compile-1.c | 11 + .../riscv/cv-simd-cmpne-h-compile-1.c | 11 + .../riscv/cv-simd-cmpne-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpne-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cplxconj-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div8-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div8-compile-1.c | 11 + .../riscv/cv-simd-dotsp-b-compile-1.c | 11 + .../riscv/cv-simd-dotsp-h-compile-1.c | 11 + .../riscv/cv-simd-dotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-dotup-b-compile-1.c | 11 + .../riscv/cv-simd-dotup-h-compile-1.c | 11 + .../riscv/cv-simd-dotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-dotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-dotusp-b-compile-1.c | 11 + .../riscv/cv-simd-dotusp-h-compile-1.c | 11 + .../riscv/cv-simd-dotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-extract-b-compile-1.c | 23 + .../riscv/cv-simd-extract-h-compile-1.c | 23 + .../riscv/cv-simd-extractu-b-compile-1.c | 23 + .../riscv/cv-simd-extractu-h-compile-1.c | 23 + .../riscv/cv-simd-insert-b-compile-1.c | 23 + .../riscv/cv-simd-insert-h-compile-1.c | 23 + .../riscv/cv-simd-march-compile-1.c | 1765 +++++++++++++++ .../riscv/cv-simd-max-b-compile-1.c | 11 + .../riscv/cv-simd-max-h-compile-1.c | 11 + .../riscv/cv-simd-max-sc-b-compile-1.c | 30 + .../riscv/cv-simd-max-sc-h-compile-1.c | 30 + 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.../riscv/cv-simd-packlo-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-sdotup-b-compile-1.c | 11 + .../riscv/cv-simd-sdotup-h-compile-1.c | 11 + .../riscv/cv-simd-sdotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sdotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sdotusp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-shuffle-sci-h-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-b-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-h-compile-1.c | 11 + .../riscv/cv-simd-shufflei0-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei1-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei2-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei3-sci-b-compile-1.c | 19 + .../riscv/cv-simd-sll-b-compile-1.c | 11 + .../riscv/cv-simd-sll-h-compile-1.c | 11 + .../riscv/cv-simd-sll-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sll-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sra-b-compile-1.c | 11 + .../riscv/cv-simd-sra-h-compile-1.c | 11 + .../riscv/cv-simd-sra-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sra-sc-h-compile-1.c | 24 + .../riscv/cv-simd-srl-b-compile-1.c | 11 + .../riscv/cv-simd-srl-h-compile-1.c | 11 + .../riscv/cv-simd-srl-sc-b-compile-1.c | 24 + .../riscv/cv-simd-srl-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sub-b-compile-1.c | 11 + .../riscv/cv-simd-sub-div2-compile-1.c | 11 + .../riscv/cv-simd-sub-div4-compile-1.c | 11 + .../riscv/cv-simd-sub-div8-compile-1.c | 11 + .../riscv/cv-simd-sub-h-compile-1.c | 11 + .../riscv/cv-simd-sub-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sub-sc-h-compile-1.c | 30 + .../riscv/cv-simd-subrotmj-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div2-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div4-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div8-compile-1.c | 11 + .../riscv/cv-simd-xor-b-compile-1.c | 11 + .../riscv/cv-simd-xor-h-compile-1.c | 11 + .../riscv/cv-simd-xor-sc-b-compile-1.c | 30 + .../riscv/cv-simd-xor-sc-h-compile-1.c | 30 + gcc/testsuite/lib/target-supports.exp | 13 + 173 files changed, 7663 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c create 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gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 04631e007f0..45bf44c0b49 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -314,6 +314,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1671,6 +1672,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI}, + {"xcvsimd", &gcc_options::x_riscv_xcv_subext, MASK_XCVSIMD}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 718b4bd77df..f253dc995a5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -55,6 +55,11 @@ (and (match_code "const_int") (match_test "ival == 2"))) +(define_constraint "c03" + "Constant value 3" + (and (match_code "const_int") + (match_test "ival == 3"))) + (define_constraint "c04" "Constant value 4" (and (match_code "const_int") @@ -253,3 +258,28 @@ A 5-bit signed immediate for CORE-V Immediate Branch." (and (match_code "const_int") (match_test "IN_RANGE (ival, -16, 15)"))) + +(define_constraint "CV_simd_si6" + "A 6-bit signed immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -32, 31)"))) + +(define_constraint "CV_simd_un6" + "A 6-bit unsigned immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 0, 63)"))) + +(define_constraint "CV_simd_i01" + "Shifting immediate for SIMD shufflei1." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 64, 127)"))) + +(define_constraint "CV_simd_i02" + "Shifting immediate for SIMD shufflei2." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -128, -65)"))) + +(define_constraint "CV_simd_i03" + "Shifting immediate for SIMD shufflei3." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -64, -1)"))) diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def index 3b9ec029d06..9157529fd4c 100644 --- a/gcc/config/riscv/corev.def +++ b/gcc/config/riscv/corev.def @@ -44,3 +44,159 @@ RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_ // XCVELW RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw), + +// XCVSIMD +//ALU Operations +RISCV_BUILTIN (cv_simd_add_h_si, "cv_simd_add_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_add_b_si, "cv_simd_add_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_h_si, "cv_simd_add_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_b_si, "cv_simd_add_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_h_si, "cv_simd_sub_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_b_si, "cv_simd_sub_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_h_si, "cv_simd_sub_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_b_si, "cv_simd_sub_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_h_si, "cv_simd_avg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_b_si, "cv_simd_avg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_h_si, "cv_simd_avg_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_b_si, "cv_simd_avg_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_h_si, "cv_simd_avgu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_b_si, "cv_simd_avgu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_h_si, "cv_simd_avgu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_b_si, "cv_simd_avgu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_min_h_si, "cv_simd_min_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_b_si, "cv_simd_min_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_h_si, "cv_simd_min_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_b_si, "cv_simd_min_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_h_si, "cv_simd_minu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_b_si, "cv_simd_minu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_h_si, "cv_simd_minu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_b_si, "cv_simd_minu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_max_h_si, "cv_simd_max_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_b_si, "cv_simd_max_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_h_si, "cv_simd_max_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_b_si, "cv_simd_max_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_h_si, "cv_simd_maxu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_b_si, "cv_simd_maxu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_h_si, "cv_simd_maxu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_b_si, "cv_simd_maxu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_h_si, "cv_simd_srl_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_b_si, "cv_simd_srl_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_h_si, "cv_simd_srl_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_b_si, "cv_simd_srl_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_h_si, "cv_simd_sra_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_b_si, "cv_simd_sra_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_h_si, "cv_simd_sra_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_b_si, "cv_simd_sra_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_h_si, "cv_simd_sll_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_b_si, "cv_simd_sll_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_h_si, "cv_simd_sll_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_b_si, "cv_simd_sll_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_or_h_si, "cv_simd_or_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_b_si, "cv_simd_or_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_h_si, "cv_simd_or_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_b_si, "cv_simd_or_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_h_si, "cv_simd_xor_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_b_si, "cv_simd_xor_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_h_si, "cv_simd_xor_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_b_si, "cv_simd_xor_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_and_h_si, "cv_simd_and_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_b_si, "cv_simd_and_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_h_si, "cv_simd_and_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_b_si, "cv_simd_and_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_h_si, "cv_simd_abs_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_b_si, "cv_simd_abs_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_h_si, "cv_simd_neg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_b_si, "cv_simd_neg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +//BIT MANIPULATION +RISCV_BUILTIN (cv_simd_extract_h_si, "cv_simd_extract_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extract_b_si, "cv_simd_extract_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_h_si, "cv_simd_extractu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_b_si, "cv_simd_extractu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_h_si, "cv_simd_insert_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_b_si, "cv_simd_insert_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +//DOT PRODUCT +RISCV_BUILTIN (cv_simd_dotup_h_si, "cv_simd_dotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_b_si, "cv_simd_dotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_h_si, "cv_simd_dotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_b_si, "cv_simd_dotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_h_si, "cv_simd_dotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_b_si, "cv_simd_dotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_h_si, "cv_simd_dotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_b_si, "cv_simd_dotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_h_si, "cv_simd_dotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_b_si, "cv_simd_dotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_h_si, "cv_simd_dotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_b_si, "cv_simd_dotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_h_si, "cv_simd_sdotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_b_si, "cv_simd_sdotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_h_si, "cv_simd_sdotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_b_si, "cv_simd_sdotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_h_si, "cv_simd_sdotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_b_si, "cv_simd_sdotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_h_si, "cv_simd_sdotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_b_si, "cv_simd_sdotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_h_si, "cv_simd_sdotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_b_si, "cv_simd_sdotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_h_si, "cv_simd_sdotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_b_si, "cv_simd_sdotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +//SHUFFLE AND PACK +RISCV_BUILTIN (cv_simd_shuffle_h_si, "cv_simd_shuffle_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_h_si, "cv_simd_shuffle_sci_h",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_b_si, "cv_simd_shuffle_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_b_si, "cv_simd_shuffle_sci_b",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_h_si, "cv_simd_shuffle2_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_b_si, "cv_simd_shuffle2_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_h_si, "cv_simd_packhi_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_h_si, "cv_simd_packlo_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_si, "cv_simd_pack", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_h_si, "cv_simd_pack_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//COMPARISON OPERATIONS +RISCV_BUILTIN (cv_simd_cmpeq_h_si, "cv_simd_cmpeq_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_b_si, "cv_simd_cmpeq_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_h_si, "cv_simd_cmpeq_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_b_si, "cv_simd_cmpeq_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_h_si, "cv_simd_cmpne_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_b_si, "cv_simd_cmpne_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_h_si, "cv_simd_cmpne_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_b_si, "cv_simd_cmpne_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_h_si, "cv_simd_cmpgt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_b_si, "cv_simd_cmpgt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_h_si, "cv_simd_cmpgt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_b_si, "cv_simd_cmpgt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_h_si, "cv_simd_cmpge_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_b_si, "cv_simd_cmpge_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_h_si, "cv_simd_cmpge_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_b_si, "cv_simd_cmpge_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_h_si, "cv_simd_cmplt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_b_si, "cv_simd_cmplt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_h_si, "cv_simd_cmplt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_b_si, "cv_simd_cmplt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_h_si, "cv_simd_cmple_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_b_si, "cv_simd_cmple_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_h_si, "cv_simd_cmple_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_b_si, "cv_simd_cmple_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_h_si, "cv_simd_cmpgtu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_b_si, "cv_simd_cmpgtu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_h_si, "cv_simd_cmpgtu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_b_si, "cv_simd_cmpgtu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_h_si, "cv_simd_cmpgeu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_b_si, "cv_simd_cmpgeu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_h_si, "cv_simd_cmpgeu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_b_si, "cv_simd_cmpgeu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_h_si, "cv_simd_cmpltu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_b_si, "cv_simd_cmpltu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_h_si, "cv_simd_cmpltu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_b_si, "cv_simd_cmpltu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_h_si, "cv_simd_cmpleu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_b_si, "cv_simd_cmpleu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_h_si, "cv_simd_cmpleu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_b_si, "cv_simd_cmpleu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +//COMPLEX NUMBER +RISCV_BUILTIN (cv_simd_cplxmul_r_si, "cv_simd_cplxmul_r", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxmul_i_si, "cv_simd_cplxmul_i", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxconj_si, "cv_simd_cplxconj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_subrotmj_si, "cv_simd_subrotmj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index 7d7b952d817..86c5a14502c 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -27,6 +27,164 @@ ;;CORE-V EVENT LOAD UNSPECV_CV_ELW + + ;;CORE-V SIMD + ;;CORE-V SIMD ALU + UNSPEC_CV_ADD_H + UNSPEC_CV_ADD_B + UNSPEC_CV_ADD_SC_H + UNSPEC_CV_ADD_SC_B + UNSPEC_CV_SUB_H + UNSPEC_CV_SUB_B + UNSPEC_CV_SUB_SC_H + UNSPEC_CV_SUB_SC_B + UNSPEC_CV_AVG_H + UNSPEC_CV_AVG_B + UNSPEC_CV_AVG_SC_H + UNSPEC_CV_AVG_SC_B + UNSPEC_CV_AVGU_H + UNSPEC_CV_AVGU_B + UNSPEC_CV_AVGU_SC_H + UNSPEC_CV_AVGU_SC_B + UNSPEC_CV_MIN_H + UNSPEC_CV_MIN_B + UNSPEC_CV_MIN_SC_H + UNSPEC_CV_MIN_SC_B + UNSPEC_CV_MINU_H + UNSPEC_CV_MINU_B + UNSPEC_CV_MINU_SC_H + UNSPEC_CV_MINU_SC_B + UNSPEC_CV_MAX_H + UNSPEC_CV_MAX_B + UNSPEC_CV_MAX_SC_H + UNSPEC_CV_MAX_SC_B + UNSPEC_CV_MAXU_H + UNSPEC_CV_MAXU_B + UNSPEC_CV_MAXU_SC_H + UNSPEC_CV_MAXU_SC_B + UNSPEC_CV_SRL_H + UNSPEC_CV_SRL_B + UNSPEC_CV_SRL_SC_H + UNSPEC_CV_SRL_SC_B + UNSPEC_CV_SRA_H + UNSPEC_CV_SRA_B + UNSPEC_CV_SRA_SC_H + UNSPEC_CV_SRA_SC_B + UNSPEC_CV_SLL_H + UNSPEC_CV_SLL_B + UNSPEC_CV_SLL_SC_H + UNSPEC_CV_SLL_SC_B + UNSPEC_CV_OR_H + UNSPEC_CV_OR_B + UNSPEC_CV_OR_SC_H + UNSPEC_CV_OR_SC_B + UNSPEC_CV_XOR_H + UNSPEC_CV_XOR_B + UNSPEC_CV_XOR_SC_H + UNSPEC_CV_XOR_SC_B + UNSPEC_CV_AND_H + UNSPEC_CV_AND_B + UNSPEC_CV_AND_SC_H + UNSPEC_CV_AND_SC_B + UNSPEC_CV_ABS_H + UNSPEC_CV_ABS_B + UNSPEC_CV_NEG_H + UNSPEC_CV_NEG_B + + ;;CORE-V SIMD BIT MANIPULATION + UNSPEC_CV_EXTRACT_H + UNSPEC_CV_EXTRACT_B + UNSPEC_CV_EXTRACTU_H + UNSPEC_CV_EXTRACTU_B + UNSPEC_CV_INSERT_H + UNSPEC_CV_INSERT_B + + ;;CORE-V SIMD DOT PRODUCT + UNSPEC_CV_DOTUP_H + UNSPEC_CV_DOTUP_B + UNSPEC_CV_DOTUP_SC_H + UNSPEC_CV_DOTUP_SC_B + UNSPEC_CV_DOTUSP_H + UNSPEC_CV_DOTUSP_B + UNSPEC_CV_DOTUSP_SC_H + UNSPEC_CV_DOTUSP_SC_B + UNSPEC_CV_DOTSP_H + UNSPEC_CV_DOTSP_B + UNSPEC_CV_DOTSP_SC_H + UNSPEC_CV_DOTSP_SC_B + UNSPEC_CV_SDOTUP_H + UNSPEC_CV_SDOTUP_B + UNSPEC_CV_SDOTUP_SC_H + UNSPEC_CV_SDOTUP_SC_B + UNSPEC_CV_SDOTUSP_H + UNSPEC_CV_SDOTUSP_B + UNSPEC_CV_SDOTUSP_SC_H + UNSPEC_CV_SDOTUSP_SC_B + UNSPEC_CV_SDOTSP_H + UNSPEC_CV_SDOTSP_B + UNSPEC_CV_SDOTSP_SC_H + UNSPEC_CV_SDOTSP_SC_B + + ;;CORE-V SIMD SHUFFLE AND PACK + UNSPEC_CV_SHUFFLE_H + UNSPEC_CV_SHUFFLE_SCI_H + UNSPEC_CV_SHUFFLE_B + UNSPEC_CV_SHUFFLE_SCI_B + UNSPEC_CV_SHUFFLE2_H + UNSPEC_CV_SHUFFLE2_B + UNSPEC_CV_PACKHI_H + UNSPEC_CV_PACKLO_H + UNSPEC_CV_PACKHI_B + UNSPEC_CV_PACKLO_B + + ;;CORE-V SIMD COMPARISON + UNSPEC_CV_CMPEQ_H + UNSPEC_CV_CMPEQ_B + UNSPEC_CV_CMPEQ_SC_H + UNSPEC_CV_CMPEQ_SC_B + UNSPEC_CV_CMPNE_H + UNSPEC_CV_CMPNE_B + UNSPEC_CV_CMPNE_SC_H + UNSPEC_CV_CMPNE_SC_B + UNSPEC_CV_CMPGT_H + UNSPEC_CV_CMPGT_B + UNSPEC_CV_CMPGT_SC_H + UNSPEC_CV_CMPGT_SC_B + UNSPEC_CV_CMPGE_H + UNSPEC_CV_CMPGE_B + UNSPEC_CV_CMPGE_SC_H + UNSPEC_CV_CMPGE_SC_B + UNSPEC_CV_CMPLT_H + UNSPEC_CV_CMPLT_B + UNSPEC_CV_CMPLT_SC_H + UNSPEC_CV_CMPLT_SC_B + UNSPEC_CV_CMPLE_H + UNSPEC_CV_CMPLE_B + UNSPEC_CV_CMPLE_SC_H + UNSPEC_CV_CMPLE_SC_B + UNSPEC_CV_CMPGTU_H + UNSPEC_CV_CMPGTU_B + UNSPEC_CV_CMPGTU_SC_H + UNSPEC_CV_CMPGTU_SC_B + UNSPEC_CV_CMPGEU_H + UNSPEC_CV_CMPGEU_B + UNSPEC_CV_CMPGEU_SC_H + UNSPEC_CV_CMPGEU_SC_B + UNSPEC_CV_CMPLTU_H + UNSPEC_CV_CMPLTU_B + UNSPEC_CV_CMPLTU_SC_H + UNSPEC_CV_CMPLTU_SC_B + UNSPEC_CV_CMPLEU_H + UNSPEC_CV_CMPLEU_B + UNSPEC_CV_CMPLEU_SC_H + UNSPEC_CV_CMPLEU_SC_B + + ;;CORE-V SIMD COMPLEX + UNSPEC_CV_CPLXMUL_R + UNSPEC_CV_CPLXMUL_I + UNSPEC_CV_CPLXCONJ + UNSPEC_CV_SUBROTMJ + ]) ;; XCVMAC extension. @@ -720,3 +878,1753 @@ "cv.b%C1imm\t%2,%3,%0" [(set_attr "type" "branch") (set_attr "mode" "none")]) + +;;CORE-V SIMD +;;CORE-V SIMD ALU +(define_insn "riscv_cv_simd_add_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_ADD_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.h\\t%0,%1,%2 + cv.add.div2\\t%0,%1,%2 + cv.add.div4\\t%0,%1,%2 + cv.add.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_ADD_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.add.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.h\\t%0,%1,%2 + cv.add.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.b\\t%0,%1,%2 + cv.add.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUB_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.h\\t%0,%1,%2 + cv.sub.div2\\t%0,%1,%2 + cv.sub.div4\\t%0,%1,%2 + cv.sub.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SUB_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.h\\t%0,%1,%2 + cv.sub.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.b\\t%0,%1,%2 + cv.sub.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.h\\t%0,%1,%2 + cv.avg.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.b\\t%0,%1,%2 + cv.avg.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.h\\t%0,%1,%2 + cv.avgu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.b\\t%0,%1,%2 + cv.avgu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.h\\t%0,%1,%2 + cv.min.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.b\\t%0,%1,%2 + cv.min.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.h\\t%0,%1,%2 + cv.minu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.b\\t%0,%1,%2 + cv.minu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.h\\t%0,%1,%2 + cv.max.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.b\\t%0,%1,%2 + cv.max.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.h\\t%0,%1,%2 + cv.maxu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.b\\t%0,%1,%2 + cv.maxu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.h\\t%0,%1,%2 + cv.srl.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.b\\t%0,%1,%2 + cv.srl.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.h\\t%0,%1,%2 + cv.sra.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.b\\t%0,%1,%2 + cv.sra.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.h\\t%0,%1,%2 + cv.sll.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.b\\t%0,%1,%2 + cv.sll.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.h\\t%0,%1,%2 + cv.or.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.b\\t%0,%1,%2 + cv.or.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.h\\t%0,%1,%2 + cv.xor.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.b\\t%0,%1,%2 + cv.xor.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.h\\t%0,%1,%2 + cv.and.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.b\\t%0,%1,%2 + cv.and.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.h\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.b\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.h\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD BIT MANIPULATION +(define_insn "riscv_cv_simd_extract_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extract_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.h\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.b\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD DOT PRODUCT +(define_insn "riscv_cv_simd_dotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.h\\t%0,%1,%2 + cv.dotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.b\\t%0,%1,%2 + cv.dotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.h\\t%0,%1,%2 + cv.dotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.b\\t%0,%1,%2 + cv.dotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.h\\t%0,%1,%2 + cv.dotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.b\\t%0,%1,%2 + cv.dotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.h\\t%0,%1,%2 + cv.sdotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.b\\t%0,%1,%2 + cv.sdotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.h\\t%0,%1,%2 + cv.sdotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.b\\t%0,%1,%2 + cv.sdotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.h\\t%0,%1,%2 + cv.sdotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.b\\t%0,%1,%2 + cv.sdotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD SHUFFLE AND PACK +(define_insn "riscv_cv_simd_shuffle_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "const_int6_operand" "CV_simd_un6")] + UNSPEC_CV_SHUFFLE_SCI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.sci.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:QI 2 "const_int_operand" "CV_simd_un6,CV_simd_i01,CV_simd_i02,CV_simd_i03")] + UNSPEC_CV_SHUFFLE_SCI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.shufflei0.sci.b\\t%0,%1,%Y2 + cv.shufflei1.sci.b\\t%0,%1,%Y2 + cv.shufflei2.sci.b\\t%0,%1,%Y2 + cv.shufflei3.sci.b\\t%0,%1,%Y2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKHI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKLO_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKHI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packhi.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKLO_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packlo.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPARISON +(define_insn "riscv_cv_simd_cmpeq_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.h\\t%0,%1,%2 + cv.cmpeq.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.b\\t%0,%1,%2 + cv.cmpeq.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.h\\t%0,%1,%2 + cv.cmpne.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.b\\t%0,%1,%2 + cv.cmpne.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.h\\t%0,%1,%2 + cv.cmpgt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.b\\t%0,%1,%2 + cv.cmpgt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.h\\t%0,%1,%2 + cv.cmpge.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.b\\t%0,%1,%2 + cv.cmpge.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.h\\t%0,%1,%2 + cv.cmplt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.b\\t%0,%1,%2 + cv.cmplt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.h\\t%0,%1,%2 + cv.cmple.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.b\\t%0,%1,%2 + cv.cmple.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.h\\t%0,%1,%2 + cv.cmpgtu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.b\\t%0,%1,%2 + cv.cmpgtu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.h\\t%0,%1,%2 + cv.cmpgeu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.b\\t%0,%1,%2 + cv.cmpgeu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.h\\t%0,%1,%2 + cv.cmpltu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.b\\t%0,%1,%2 + cv.cmpltu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.h\\t%0,%1,%2 + cv.cmpleu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.b\\t%0,%1,%2 + cv.cmpleu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPLEX +(define_insn "riscv_cv_simd_cplxmul_r_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_R))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.r\\t%0,%1,%2 + cv.cplxmul.r.div2\\t%0,%1,%2 + cv.cplxmul.r.div4\\t%0,%1,%2 + cv.cplxmul.r.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxmul_i_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_I))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.i\\t%0,%1,%2 + cv.cplxmul.i.div2\\t%0,%1,%2 + cv.cplxmul.i.div4\\t%0,%1,%2 + cv.cplxmul.i.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxconj_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CV_CPLXCONJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cplxconj\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_subrotmj_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUBROTMJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.subrotmj\\t%0,%1,%2 + cv.subrotmj.div2\\t%0,%1,%2 + cv.subrotmj.div4\\t%0,%1,%2 + cv.subrotmj.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 69a6319c2c8..dd448c925a7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -404,6 +404,26 @@ (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), -16, 15)"))) +(define_predicate "const_int6s_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -32, 31)"))) + +(define_predicate "int6s_operand" + (ior (match_operand 0 "const_int6s_operand") + (match_operand 0 "register_operand"))) + +(define_predicate "const_int2_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + +(define_predicate "const_int6_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) + +(define_predicate "int6_operand" + (ior (match_operand 0 "const_int6_operand") + (match_operand 0 "register_operand"))) + ;; Predicates for the V extension. (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 5ee11ebe3bc..be823f4f450 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -129,6 +129,7 @@ AVAIL (hint_pause, (!0)) AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) +AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 3e7d5c69503..90ab28c31d9 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -38,6 +38,10 @@ DEF_RISCV_FTYPE (1, (USI, UHI)) DEF_RISCV_FTYPE (1, (SI, QI)) DEF_RISCV_FTYPE (1, (SI, HI)) DEF_RISCV_FTYPE (2, (USI, UQI, UQI)) +DEF_RISCV_FTYPE (2, (USI, USI, UQI)) +DEF_RISCV_FTYPE (2, (USI, USI, UHI)) +DEF_RISCV_FTYPE (2, (USI, USI, QI)) +DEF_RISCV_FTYPE (2, (USI, USI, HI)) DEF_RISCV_FTYPE (2, (USI, UHI, UHI)) DEF_RISCV_FTYPE (2, (USI, USI, USI)) DEF_RISCV_FTYPE (2, (UDI, UQI, UQI)) @@ -48,6 +52,11 @@ DEF_RISCV_FTYPE (2, (UDI, UDI, UDI)) DEF_RISCV_FTYPE (2, (SI, USI, USI)) DEF_RISCV_FTYPE (2, (SI, SI, SI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI)) +DEF_RISCV_FTYPE (3, (USI, USI, USI, QI)) +DEF_RISCV_FTYPE (3, (USI, USI, UQI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, QI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, UHI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, HI, USI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, USI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, SI)) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 08ff05dcc3f..9fd1914ae70 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5534,6 +5534,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) output_addr_const (file, newop); break; } + case 'Y': + { + unsigned int imm = (UINTVAL (op) & 63); + gcc_assert (imm <= 63); + rtx newop = GEN_INT (imm); + output_addr_const (file, newop); + break; + } default: switch (code) { diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index d06c0f8f416..8e55d332346 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -415,6 +415,8 @@ Mask(XCVELW) Var(riscv_xcv_subext) Mask(XCVBI) Var(riscv_xcv_subext) +Mask(XCVSIMD) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b890acccac1..9d77d3f53cc 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21799,6 +21799,8 @@ All of these functions are declared in the include file @file{riscv_vector.h}. @node CORE-V Built-in Functions @subsection CORE-V Built-in Functions +For more information on all CORE-V built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md} These built-in functions are available for the CORE-V MAC machine architecture. For more information on CORE-V built-ins, please see @@ -21978,6 +21980,890 @@ architecture. For more information on CORE-V ELW builtins, please see Generated assembler @code{cv.elw} @end deftypefn +These built-in functions are available for the CORE-V SIMD machine +architecture. For more information on CORE-V SIMD built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-816-bit-simd-builtins-xcvsimd} + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_b (uint32_t, uint32_t) +Generated assembler @code{cv.add.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.add.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.add.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_b (uint32_t, uint32_t) +Generated assembler @code{cv.sub.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sub.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sub.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_h (uint32_t, uint32_t) +Generated assembler @code{cv.avg.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_b (uint32_t, uint32_t) +Generated assembler @code{cv.avg.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.avg.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.avg.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_h (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_b (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.avgu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.avgu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_h (uint32_t, uint32_t) +Generated assembler @code{cv.min.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_b (uint32_t, uint32_t) +Generated assembler @code{cv.min.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.min.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.min.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_h (uint32_t, uint32_t) +Generated assembler @code{cv.minu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_b (uint32_t, uint32_t) +Generated assembler @code{cv.minu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.minu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.minu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_h (uint32_t, uint32_t) +Generated assembler @code{cv.max.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_b (uint32_t, uint32_t) +Generated assembler @code{cv.max.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.max.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.max.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_h (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_b (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.maxu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.maxu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_h (uint32_t, uint32_t) +Generated assembler @code{cv.srl.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_b (uint32_t, uint32_t) +Generated assembler @code{cv.srl.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.srl.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.srl.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_h (uint32_t, uint32_t) +Generated assembler @code{cv.sra.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_b (uint32_t, uint32_t) +Generated assembler @code{cv.sra.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sra.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sra.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_h (uint32_t, uint32_t) +Generated assembler @code{cv.sll.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_b (uint32_t, uint32_t) +Generated assembler @code{cv.sll.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sll.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sll.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_h (uint32_t, uint32_t) +Generated assembler @code{cv.or.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_b (uint32_t, uint32_t) +Generated assembler @code{cv.or.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.or.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.or.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_h (uint32_t, uint32_t) +Generated assembler @code{cv.xor.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_b (uint32_t, uint32_t) +Generated assembler @code{cv.xor.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.xor.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.xor.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_h (uint32_t, uint32_t) +Generated assembler @code{cv.and.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_b (uint32_t, uint32_t) +Generated assembler @code{cv.and.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.and.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.and.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_h (uint32_t) +Generated assembler @code{cv.abs.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_b (uint32_t) +Generated assembler @code{cv.abs.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.dotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.dotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint16_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint8_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_h (uint32_t, uint6_t) +Generated assembler @code{cv.extract.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_b (uint32_t, uint6_t) +Generated assembler @code{cv.extract.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_h (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_b (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_h (uint32_t, uint32_t) +Generated assembler @code{cv.insert.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_b (uint32_t, uint32_t) +Generated assembler @code{cv.insert.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_h (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_b (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_sci_h (uint32_t, uint4_t) +Generated assembler @code{cv.shuffle.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei0_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei0.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei1_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei1.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei2_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei2.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei3_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei3.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packhi.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packlo.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpeq.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpeq.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpne.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpne.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpgt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpgt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpge.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpge.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmplt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmplt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmple.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmple.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgtu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgtu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgeu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgeu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpltu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpltu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpleu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpleu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxconj (uint32_t) +Generated assembler @code{cv.cplxconj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div8} +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 6fee1144238..031cdfd8a70 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2487,6 +2487,9 @@ Test system has support for the CORE-V ELW extension. @item cv_bi Test system has support for the CORE-V BI extension. +@item cv_simd +Test system has support for the CORE-V SIMD extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c new file mode 100644 index 00000000000..c8d58724786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c new file mode 100644 index 00000000000..9ebb9053e35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c new file mode 100644 index 00000000000..b362e904407 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c new file mode 100644 index 00000000000..8e885a1062b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c new file mode 100644 index 00000000000..3edea7bb990 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c new file mode 100644 index 00000000000..df43c202b9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c new file mode 100644 index 00000000000..27b2cc38f4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c new file mode 100644 index 00000000000..43f37a88cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c new file mode 100644 index 00000000000..99cd7b40731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c new file mode 100644 index 00000000000..6be001d4c11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c new file mode 100644 index 00000000000..770c3e59e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c new file mode 100644 index 00000000000..616a9235a67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c new file mode 100644 index 00000000000..73ceba6cbed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c new file mode 100644 index 00000000000..21ae43aeb5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c new file mode 100644 index 00000000000..f2582d4e3ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c new file mode 100644 index 00000000000..a72a9effcd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c new file mode 100644 index 00000000000..41cd20f2536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c new file mode 100644 index 00000000000..a17a9233120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c new file mode 100644 index 00000000000..8f7c62c8b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c new file mode 100644 index 00000000000..7e00a5b2b7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c new file mode 100644 index 00000000000..f024d0e5d7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c new file mode 100644 index 00000000000..7ac9cb2704a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c new file mode 100644 index 00000000000..8fc1eb03417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c new file mode 100644 index 00000000000..5a0adcd68a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c new file mode 100644 index 00000000000..c1aeb7e6874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c new file mode 100644 index 00000000000..74c5a17588c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c new file mode 100644 index 00000000000..32b509ecd53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c new file mode 100644 index 00000000000..4e4bbeeee04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c new file mode 100644 index 00000000000..4443f65f7c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c new file mode 100644 index 00000000000..0207c3210e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c new file mode 100644 index 00000000000..b8da488a814 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c new file mode 100644 index 00000000000..e8e2e62e9cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c new file mode 100644 index 00000000000..b669ea19ca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c new file mode 100644 index 00000000000..fb5f4317cd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c new file mode 100644 index 00000000000..5d5a5a96be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c new file mode 100644 index 00000000000..ab32a39091c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c new file mode 100644 index 00000000000..6f55da30358 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c new file mode 100644 index 00000000000..760cd48d991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c new file mode 100644 index 00000000000..9453079ee5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c new file mode 100644 index 00000000000..8f339103572 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c new file mode 100644 index 00000000000..3f2d2a9ccfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c new file mode 100644 index 00000000000..b19e437ddc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c new file mode 100644 index 00000000000..adb26c1c66b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c new file mode 100644 index 00000000000..d14ca9a7837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c new file mode 100644 index 00000000000..22c2218a911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c new file mode 100644 index 00000000000..1d7f671eb42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c new file mode 100644 index 00000000000..18bee44f90d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c new file mode 100644 index 00000000000..a1adf919610 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c new file mode 100644 index 00000000000..f3823ff950b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c new file mode 100644 index 00000000000..ee3a5b2ac3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c new file mode 100644 index 00000000000..7ae45ff94dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c new file mode 100644 index 00000000000..ce6f280ae4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c new file mode 100644 index 00000000000..acd0c2c13aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c new file mode 100644 index 00000000000..e3260f986ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c new file mode 100644 index 00000000000..37f1f8b81f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c new file mode 100644 index 00000000000..34e4e980868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c new file mode 100644 index 00000000000..973b11e663a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c new file mode 100644 index 00000000000..532aabbd683 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c new file mode 100644 index 00000000000..cfa0abcd545 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c new file mode 100644 index 00000000000..9554172ab2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c new file mode 100644 index 00000000000..f2d9e659b89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c new file mode 100644 index 00000000000..194a70480f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c new file mode 100644 index 00000000000..dab59c6e95b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c new file mode 100644 index 00000000000..27da60ac96f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c new file mode 100644 index 00000000000..f9fd78e12be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c new file mode 100644 index 00000000000..0cacf8dc2ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c new file mode 100644 index 00000000000..60c378a5c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c new file mode 100644 index 00000000000..a2bb0dffe53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c new file mode 100644 index 00000000000..0f9d986f8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c new file mode 100644 index 00000000000..7c025c7aba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c new file mode 100644 index 00000000000..4b522da48dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c new file mode 100644 index 00000000000..12fa58be89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..1ba74ff8ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..19684717e95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c new file mode 100644 index 00000000000..a65464e348d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c new file mode 100644 index 00000000000..42145083ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c new file mode 100644 index 00000000000..51e9154ff60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c new file mode 100644 index 00000000000..28b423f5731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c new file mode 100644 index 00000000000..b5281bd7230 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c new file mode 100644 index 00000000000..5545b5e6037 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..7db3f1c94f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..1af83c57070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c new file mode 100644 index 00000000000..10133fe4907 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c new file mode 100644 index 00000000000..a507e016496 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c new file mode 100644 index 00000000000..1ea67024cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c new file mode 100644 index 00000000000..499e5780381 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c new file mode 100644 index 00000000000..d7c9d4ed212 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 3); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c new file mode 100644 index 00000000000..e10389e6995 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 1); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c new file mode 100644 index 00000000000..3fe01498356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c @@ -0,0 +1,1765 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 20); +} + + +int +foo5 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + + +int +foo6 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 20); +} + + +int +foo7 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + + +int +foo8 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + + +int +foo9 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + + +int +foo10 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 20); +} + + +int +foo11 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + + +int +foo12 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 20); +} + + +int +foo13 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + + +int +foo14 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + + +int +foo15 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + + +int +foo16 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 20); +} + + +int +foo17 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + + +int +foo18 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 20); +} + + +int +foo19 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + + +int +foo20 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + + +int +foo21 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + + +int +foo22 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 20); +} + + +int +foo23 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + + +int +foo24 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 20); +} + + +int +foo25 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + + +int +foo26 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + + +int +foo27 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + + +int +foo28 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 20); +} + + +int +foo29 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + + +int +foo30 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 20); +} + + +int +foo31 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + + +int +foo32 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + + +int +foo33 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + + +int +foo34 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 20); +} + + +int +foo35 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + + +int +foo36 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 20); +} + + +int +foo37 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + + +int +foo38 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + + +int +foo39 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + + +int +foo40 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 20); +} + + +int +foo41 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + + +int +foo42 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 20); +} + + +int +foo43 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + + +int +foo44 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + + +int +foo45 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + + +int +foo46 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 20); +} + + +int +foo47 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + + +int +foo48 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 20); +} + + +int +foo49 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + + +int +foo50 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + + +int +foo51 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, b); +} + + +int +foo52 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, 20); +} + + +int +foo53 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, b); +} + + +int +foo54 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, 20); +} + + +int +foo55 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + + +int +foo56 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + + +int +foo57 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, b); +} + + +int +foo58 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, 20); +} + + +int +foo59 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, b); +} + + +int +foo60 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, 20); +} + + +int +foo61 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + + +int +foo62 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + + +int +foo63 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, b); +} + + +int +foo64 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, 20); +} + + +int +foo65 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, b); +} + + +int +foo66 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, 20); +} + + +int +foo67 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + + +int +foo68 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + + +int +foo69 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + + +int +foo70 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 20); +} + + +int +foo71 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + + +int +foo72 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 20); +} + + +int +foo73 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + + +int +foo74 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + + +int +foo75 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + + +int +foo76 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 20); +} + + +int +foo77 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + + +int +foo78 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 20); +} + + +int +foo79 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + + +int +foo80 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + + +int +foo81 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + + +int +foo82 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 20); +} + + +int +foo83 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + + +int +foo84 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 20); +} + + +int +foo85 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + + +int +foo86 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + + +int +foo87 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + + +int +foo88 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + + +int +foo89 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + + +int +foo90 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 20); +} + + +int +foo91 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + + +int +foo92 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 20); +} + + +int +foo93 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + + +int +foo94 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + + +int +foo95 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + + +int +foo96 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 20); +} + + +int +foo97 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + + +int +foo98 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 20); +} + + +int +foo99 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + + +int +foo100 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + + +int +foo101 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + + +int +foo102 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 20); +} + + +int +foo103 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + + +int +foo104 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 20); +} + + +int +foo105 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + + +int +foo106 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + + +int +foo107 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + + +int +foo108 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 20, b); +} + + +int +foo109 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + + +int +foo110 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 20, b); +} + + +int +foo111 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + + +int +foo112 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + + +int +foo113 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + + +int +foo114 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 20, b); +} + + +int +foo115 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + + +int +foo116 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 20, b); +} + + +int +foo117 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + + +int +foo118 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + + +int +foo119 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + + +int +foo120 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 20, b); +} + + +int +foo121 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + + +int +foo122 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 20, b); +} + + +int +foo123 (int a) +{ + return __builtin_riscv_cv_simd_extract_h(a, 20); +} + + +int +foo124 (int a) +{ + return __builtin_riscv_cv_simd_extract_b(a, 20); +} + + +int +foo125 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h(a, 20); +} + + +int +foo126 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b(a, 20); +} + + +int +foo127 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h(a, b, 20); +} + + +int +foo128 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b(a, b, 20); +} + + +int +foo129 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_h(a, b); +} + + +int +foo130 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_b(a, b); +} + + +int +foo131 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 20); +} + + +int +foo132 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 0); +} + + +int +foo133 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 64); +} + + +int +foo134 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 128); +} + + +int +foo135 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 192); +} + + +int +foo136 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + + +int +foo137 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + + +int +foo138 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + + +int +foo139 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + + +int +foo140 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + + +int +foo141 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + + +int +foo142 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + + +int +foo143 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + + +int +foo144 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + + +int +foo145 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 20); +} + + +int +foo146 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + + +int +foo147 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 20); +} + + +int +foo148 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + + +int +foo149 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + + +int +foo150 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + + +int +foo151 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 20); +} + + +int +foo152 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + + +int +foo153 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 20); +} + + +int +foo154 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + + +int +foo155 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + + +int +foo156 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + + +int +foo157 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 20); +} + + +int +foo158 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + + +int +foo159 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 20); +} + + +int +foo160 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + + +int +foo161 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + + +int +foo162 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + + +int +foo163 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 20); +} + + +int +foo164 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + + +int +foo165 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 20); +} + + +int +foo166 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + + +int +foo167 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + + +int +foo168 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + + +int +foo169 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 20); +} + + +int +foo170 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + + +int +foo171 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 20); +} + + +int +foo172 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + + +int +foo173 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + + +int +foo174 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + + +int +foo175 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 20); +} + + +int +foo176 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + + +int +foo177 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 20); +} + + +int +foo178 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + + +int +foo179 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + + +int +foo180 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + + +int +foo181 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 20); +} + + +int +foo182 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + + +int +foo183 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 20); +} + + +int +foo184 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + + +int +foo185 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + + +int +foo186 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + + +int +foo187 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 20); +} + + +int +foo188 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + + +int +foo189 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 20); +} + + +int +foo190 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + + +int +foo191 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + + +int +foo192 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + + +int +foo193 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 20); +} + + +int +foo194 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + + +int +foo195 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 20); +} + + +int +foo196 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + + +int +foo197 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + + +int +foo198 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + + +int +foo199 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 20); +} + + +int +foo200 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + + +int +foo201 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 20); +} + + +int +foo202 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + + +int +foo203 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + + +int +foo204 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + + +int +foo205 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + + +int +foo206 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + + +int +foo207 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + + +int +foo208 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + + +int +foo209 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + + +int +foo210 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + + +int +foo211 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + + +int +foo212 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + + +int +foo213 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + + +int +foo214 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + + +int +foo215 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + + +int +foo216 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + + +int +foo217 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + + +int +foo218 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + + +int +foo219 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + + +int +foo220 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c new file mode 100644 index 00000000000..05c5b078129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c new file mode 100644 index 00000000000..a24308b38bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c new file mode 100644 index 00000000000..a82ceba459a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c new file mode 100644 index 00000000000..baa52d52f62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c new file mode 100644 index 00000000000..e6a96958f02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c new file mode 100644 index 00000000000..ee95b139c58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c new file mode 100644 index 00000000000..48a3c6f7922 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c new file mode 100644 index 00000000000..0a776774596 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c new file mode 100644 index 00000000000..474d96ddf4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c new file mode 100644 index 00000000000..493bbdcd92d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c new file mode 100644 index 00000000000..30ede85c2e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c new file mode 100644 index 00000000000..a99b012c425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c new file mode 100644 index 00000000000..43582b28f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c new file mode 100644 index 00000000000..e44113bbae4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c new file mode 100644 index 00000000000..eec0a56f959 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c new file mode 100644 index 00000000000..6fc29abc3fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c new file mode 100644 index 00000000000..3f8bb7ceced --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c new file mode 100644 index 00000000000..2b6ecb0fb18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c new file mode 100644 index 00000000000..d6bd54f97e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c new file mode 100644 index 00000000000..cff54f344f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c new file mode 100644 index 00000000000..cd8b2dcb0dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c new file mode 100644 index 00000000000..95352fe9b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c new file mode 100644 index 00000000000..286d36640aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c new file mode 100644 index 00000000000..2d7f1b0bcf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c new file mode 100644 index 00000000000..deb25d022a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c new file mode 100644 index 00000000000..23489301e30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c new file mode 100644 index 00000000000..14e5baa27f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c new file mode 100644 index 00000000000..e0d7f587816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..2f314142e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..03481e24c9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c new file mode 100644 index 00000000000..63017c87c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c new file mode 100644 index 00000000000..70f12643c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c new file mode 100644 index 00000000000..812faab72c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c new file mode 100644 index 00000000000..546a13b2812 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c new file mode 100644 index 00000000000..f0b522160f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c new file mode 100644 index 00000000000..8078c96702b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..d1ce8fe62de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..55410209450 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c new file mode 100644 index 00000000000..08c7a819b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c new file mode 100644 index 00000000000..7475a844ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c new file mode 100644 index 00000000000..fe4fcc613d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c new file mode 100644 index 00000000000..024e4e23af2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c new file mode 100644 index 00000000000..7b971c1dcf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 64); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 127); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c new file mode 100644 index 00000000000..63995981141 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +unsigned int +foo1 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 128); +} + +unsigned int +foo2 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 191); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c new file mode 100644 index 00000000000..6f02cb5dd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 192); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c new file mode 100644 index 00000000000..1392e7bfb1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c new file mode 100644 index 00000000000..84eba7515e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c new file mode 100644 index 00000000000..fa56156185a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c new file mode 100644 index 00000000000..12a1ffd3c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c new file mode 100644 index 00000000000..c5693023c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c new file mode 100644 index 00000000000..033aabb633f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c new file mode 100644 index 00000000000..133d9199374 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c new file mode 100644 index 00000000000..2830f44c3f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c new file mode 100644 index 00000000000..ae848b1860e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c new file mode 100644 index 00000000000..797524ee783 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c new file mode 100644 index 00000000000..e62f8fa561c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c new file mode 100644 index 00000000000..6f7592a83b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c new file mode 100644 index 00000000000..45120bcafda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c new file mode 100644 index 00000000000..e79a001508c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c new file mode 100644 index 00000000000..d8630f7ac63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c new file mode 100644 index 00000000000..efad60017b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c new file mode 100644 index 00000000000..a80e441f488 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c new file mode 100644 index 00000000000..30ce64689bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c new file mode 100644 index 00000000000..ac6d27d0eda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c new file mode 100644 index 00000000000..8ecac97a9e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c new file mode 100644 index 00000000000..c77395d31c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c new file mode 100644 index 00000000000..e53c6d1bbab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c new file mode 100644 index 00000000000..ebd431efda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c new file mode 100644 index 00000000000..56ba1cd4d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c new file mode 100644 index 00000000000..d07bceabe52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c new file mode 100644 index 00000000000..7fe0f79d8a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c new file mode 100644 index 00000000000..5227a2bf862 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 0eae746e848..fcd077eed47 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13111,6 +13111,19 @@ proc check_effective_target_cv_bi { } { } "-march=rv32i_xcvbi" ] } +# Return 1 if the CORE-V SIMD extension is available. +proc check_effective_target_cv_simd { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_simd object { + void foo (void) + { + asm ("cv.add.sc.b x0, x0, x0"); + } + } "-march=rv32i_xcvsimd" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx) -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P 2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett @ 2023-12-05 16:12 ` Kito Cheng 0 siblings, 0 replies; 12+ messages in thread From: Kito Cheng @ 2023-12-05 16:12 UTC (permalink / raw) To: Mary Bennett; +Cc: gcc-patches There are few formatting issues, but I think this is generally OK for intrinsic support only, but one question before I formally say LGTM for this patch: are you interested in making it able to code gen with GNU vector and also for auto vectorization stuff? If so, I can spend more time on reviewing that and give mooooore comments. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension 2023-11-09 11:57 [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett @ 2024-01-16 16:35 ` Mary Bennett 2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett ` (2 more replies) 1 sibling, 3 replies; 12+ messages in thread From: Mary Bennett @ 2024-01-16 16:35 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 9 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + 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* [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett @ 2024-01-16 16:35 ` Mary Bennett 2024-01-16 16:35 ` [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2 siblings, 0 replies; 12+ messages in thread From: Mary Bennett @ 2024-01-16 16:35 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 9 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + .../riscv/cv-simd-add-div4-compile-1.c | 11 + .../riscv/cv-simd-add-div8-compile-1.c | 11 + .../riscv/cv-simd-add-h-compile-1.c | 11 + .../riscv/cv-simd-add-sc-b-compile-1.c | 30 + .../riscv/cv-simd-add-sc-h-compile-1.c | 30 + .../riscv/cv-simd-and-b-compile-1.c | 11 + .../riscv/cv-simd-and-h-compile-1.c | 11 + .../riscv/cv-simd-and-sc-b-compile-1.c | 30 + .../riscv/cv-simd-and-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avg-b-compile-1.c | 11 + .../riscv/cv-simd-avg-h-compile-1.c | 11 + .../riscv/cv-simd-avg-sc-b-compile-1.c | 30 + .../riscv/cv-simd-avg-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avgu-b-compile-1.c | 11 + .../riscv/cv-simd-avgu-h-compile-1.c | 11 + .../riscv/cv-simd-avgu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-avgu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpeq-b-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-h-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpeq-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpge-b-compile-1.c | 11 + .../riscv/cv-simd-cmpge-h-compile-1.c | 11 + .../riscv/cv-simd-cmpge-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpge-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgeu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpgt-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpgt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgtu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmple-b-compile-1.c | 11 + .../riscv/cv-simd-cmple-h-compile-1.c | 11 + .../riscv/cv-simd-cmple-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmple-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpleu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpleu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmplt-b-compile-1.c | 11 + .../riscv/cv-simd-cmplt-h-compile-1.c | 11 + .../riscv/cv-simd-cmplt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmplt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpltu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpltu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpne-b-compile-1.c | 11 + .../riscv/cv-simd-cmpne-h-compile-1.c | 11 + .../riscv/cv-simd-cmpne-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpne-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cplxconj-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div8-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div8-compile-1.c | 11 + .../riscv/cv-simd-dotsp-b-compile-1.c | 11 + .../riscv/cv-simd-dotsp-h-compile-1.c | 11 + .../riscv/cv-simd-dotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-dotup-b-compile-1.c | 11 + .../riscv/cv-simd-dotup-h-compile-1.c | 11 + .../riscv/cv-simd-dotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-dotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-dotusp-b-compile-1.c | 11 + .../riscv/cv-simd-dotusp-h-compile-1.c | 11 + .../riscv/cv-simd-dotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-extract-b-compile-1.c | 23 + .../riscv/cv-simd-extract-h-compile-1.c | 23 + .../riscv/cv-simd-extractu-b-compile-1.c | 23 + .../riscv/cv-simd-extractu-h-compile-1.c | 23 + .../riscv/cv-simd-insert-b-compile-1.c | 23 + .../riscv/cv-simd-insert-h-compile-1.c | 23 + .../riscv/cv-simd-march-compile-1.c | 1765 +++++++++++++++ .../riscv/cv-simd-max-b-compile-1.c | 11 + .../riscv/cv-simd-max-h-compile-1.c | 11 + .../riscv/cv-simd-max-sc-b-compile-1.c | 30 + .../riscv/cv-simd-max-sc-h-compile-1.c | 30 + .../riscv/cv-simd-maxu-b-compile-1.c | 11 + .../riscv/cv-simd-maxu-h-compile-1.c | 11 + .../riscv/cv-simd-maxu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-maxu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-min-b-compile-1.c | 11 + .../riscv/cv-simd-min-h-compile-1.c | 11 + .../riscv/cv-simd-min-sc-b-compile-1.c | 30 + .../riscv/cv-simd-min-sc-h-compile-1.c | 30 + .../riscv/cv-simd-minu-b-compile-1.c | 11 + .../riscv/cv-simd-minu-h-compile-1.c | 11 + .../riscv/cv-simd-minu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-minu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-neg-b-compile-1.c | 11 + .../riscv/cv-simd-neg-h-compile-1.c | 11 + .../gcc.target/riscv/cv-simd-or-b-compile-1.c | 11 + .../gcc.target/riscv/cv-simd-or-h-compile-1.c | 11 + .../riscv/cv-simd-or-sc-b-compile-1.c | 30 + .../riscv/cv-simd-or-sc-h-compile-1.c | 30 + .../gcc.target/riscv/cv-simd-pack-compile-1.c | 11 + .../riscv/cv-simd-pack-h-compile-1.c | 11 + .../riscv/cv-simd-packhi-b-compile-1.c | 11 + .../riscv/cv-simd-packlo-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-sdotup-b-compile-1.c | 11 + .../riscv/cv-simd-sdotup-h-compile-1.c | 11 + .../riscv/cv-simd-sdotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sdotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sdotusp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-shuffle-sci-h-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-b-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-h-compile-1.c | 11 + .../riscv/cv-simd-shufflei0-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei1-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei2-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei3-sci-b-compile-1.c | 19 + .../riscv/cv-simd-sll-b-compile-1.c | 11 + .../riscv/cv-simd-sll-h-compile-1.c | 11 + .../riscv/cv-simd-sll-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sll-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sra-b-compile-1.c | 11 + .../riscv/cv-simd-sra-h-compile-1.c | 11 + .../riscv/cv-simd-sra-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sra-sc-h-compile-1.c | 24 + .../riscv/cv-simd-srl-b-compile-1.c | 11 + .../riscv/cv-simd-srl-h-compile-1.c | 11 + .../riscv/cv-simd-srl-sc-b-compile-1.c | 24 + .../riscv/cv-simd-srl-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sub-b-compile-1.c | 11 + .../riscv/cv-simd-sub-div2-compile-1.c | 11 + .../riscv/cv-simd-sub-div4-compile-1.c | 11 + .../riscv/cv-simd-sub-div8-compile-1.c | 11 + .../riscv/cv-simd-sub-h-compile-1.c | 11 + .../riscv/cv-simd-sub-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sub-sc-h-compile-1.c | 30 + .../riscv/cv-simd-subrotmj-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div2-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div4-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div8-compile-1.c | 11 + .../riscv/cv-simd-xor-b-compile-1.c | 11 + .../riscv/cv-simd-xor-h-compile-1.c | 11 + .../riscv/cv-simd-xor-sc-b-compile-1.c | 30 + .../riscv/cv-simd-xor-sc-h-compile-1.c | 30 + gcc/testsuite/lib/target-supports.exp | 13 + 173 files changed, 7663 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0301d170a41..eaba54172c0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -355,6 +355,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1730,6 +1731,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, + {"xcvsimd", &gcc_options::x_riscv_xcv_subext, MASK_XCVSIMD}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index ee1c12b2e51..41acaea04eb 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -55,6 +55,11 @@ (and (match_code "const_int") (match_test "ival == 2"))) +(define_constraint "c03" + "Constant value 3" + (and (match_code "const_int") + (match_test "ival == 3"))) + (define_constraint "c04" "Constant value 4" (and (match_code "const_int") @@ -262,3 +267,28 @@ (and (match_code "const_int") (and (match_test "IN_RANGE (ival, 0, 1073741823)") (match_test "exact_log2 (ival + 1) != -1")))) + +(define_constraint "CV_simd_si6" + "A 6-bit signed immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -32, 31)"))) + +(define_constraint "CV_simd_un6" + "A 6-bit unsigned immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 0, 63)"))) + +(define_constraint "CV_simd_i01" + "Shifting immediate for SIMD shufflei1." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 64, 127)"))) + +(define_constraint "CV_simd_i02" + "Shifting immediate for SIMD shufflei2." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -128, -65)"))) + +(define_constraint "CV_simd_i03" + "Shifting immediate for SIMD shufflei3." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -64, -1)"))) diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def index 3b9ec029d06..9157529fd4c 100644 --- a/gcc/config/riscv/corev.def +++ b/gcc/config/riscv/corev.def @@ -44,3 +44,159 @@ RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_ // XCVELW RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw), + +// XCVSIMD +//ALU Operations +RISCV_BUILTIN (cv_simd_add_h_si, "cv_simd_add_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_add_b_si, "cv_simd_add_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_h_si, "cv_simd_add_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_b_si, "cv_simd_add_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_h_si, "cv_simd_sub_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_b_si, "cv_simd_sub_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_h_si, "cv_simd_sub_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_b_si, "cv_simd_sub_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_h_si, "cv_simd_avg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_b_si, "cv_simd_avg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_h_si, "cv_simd_avg_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_b_si, "cv_simd_avg_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_h_si, "cv_simd_avgu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_b_si, "cv_simd_avgu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_h_si, "cv_simd_avgu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_b_si, "cv_simd_avgu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_min_h_si, "cv_simd_min_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_b_si, "cv_simd_min_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_h_si, "cv_simd_min_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_b_si, "cv_simd_min_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_h_si, "cv_simd_minu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_b_si, "cv_simd_minu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_h_si, "cv_simd_minu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_b_si, "cv_simd_minu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_max_h_si, "cv_simd_max_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_b_si, "cv_simd_max_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_h_si, "cv_simd_max_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_b_si, "cv_simd_max_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_h_si, "cv_simd_maxu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_b_si, "cv_simd_maxu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_h_si, "cv_simd_maxu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_b_si, "cv_simd_maxu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_h_si, "cv_simd_srl_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_b_si, "cv_simd_srl_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_h_si, "cv_simd_srl_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_b_si, "cv_simd_srl_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_h_si, "cv_simd_sra_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_b_si, "cv_simd_sra_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_h_si, "cv_simd_sra_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_b_si, "cv_simd_sra_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_h_si, "cv_simd_sll_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_b_si, "cv_simd_sll_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_h_si, "cv_simd_sll_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_b_si, "cv_simd_sll_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_or_h_si, "cv_simd_or_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_b_si, "cv_simd_or_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_h_si, "cv_simd_or_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_b_si, "cv_simd_or_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_h_si, "cv_simd_xor_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_b_si, "cv_simd_xor_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_h_si, "cv_simd_xor_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_b_si, "cv_simd_xor_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_and_h_si, "cv_simd_and_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_b_si, "cv_simd_and_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_h_si, "cv_simd_and_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_b_si, "cv_simd_and_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_h_si, "cv_simd_abs_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_b_si, "cv_simd_abs_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_h_si, "cv_simd_neg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_b_si, "cv_simd_neg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +//BIT MANIPULATION +RISCV_BUILTIN (cv_simd_extract_h_si, "cv_simd_extract_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extract_b_si, "cv_simd_extract_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_h_si, "cv_simd_extractu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_b_si, "cv_simd_extractu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_h_si, "cv_simd_insert_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_b_si, "cv_simd_insert_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +//DOT PRODUCT +RISCV_BUILTIN (cv_simd_dotup_h_si, "cv_simd_dotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_b_si, "cv_simd_dotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_h_si, "cv_simd_dotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_b_si, "cv_simd_dotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_h_si, "cv_simd_dotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_b_si, "cv_simd_dotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_h_si, "cv_simd_dotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_b_si, "cv_simd_dotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_h_si, "cv_simd_dotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_b_si, "cv_simd_dotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_h_si, "cv_simd_dotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_b_si, "cv_simd_dotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_h_si, "cv_simd_sdotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_b_si, "cv_simd_sdotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_h_si, "cv_simd_sdotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_b_si, "cv_simd_sdotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_h_si, "cv_simd_sdotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_b_si, "cv_simd_sdotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_h_si, "cv_simd_sdotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_b_si, "cv_simd_sdotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_h_si, "cv_simd_sdotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_b_si, "cv_simd_sdotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_h_si, "cv_simd_sdotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_b_si, "cv_simd_sdotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +//SHUFFLE AND PACK +RISCV_BUILTIN (cv_simd_shuffle_h_si, "cv_simd_shuffle_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_h_si, "cv_simd_shuffle_sci_h",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_b_si, "cv_simd_shuffle_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_b_si, "cv_simd_shuffle_sci_b",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_h_si, "cv_simd_shuffle2_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_b_si, "cv_simd_shuffle2_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_h_si, "cv_simd_packhi_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_h_si, "cv_simd_packlo_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_si, "cv_simd_pack", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_h_si, "cv_simd_pack_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//COMPARISON OPERATIONS +RISCV_BUILTIN (cv_simd_cmpeq_h_si, "cv_simd_cmpeq_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_b_si, "cv_simd_cmpeq_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_h_si, "cv_simd_cmpeq_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_b_si, "cv_simd_cmpeq_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_h_si, "cv_simd_cmpne_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_b_si, "cv_simd_cmpne_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_h_si, "cv_simd_cmpne_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_b_si, "cv_simd_cmpne_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_h_si, "cv_simd_cmpgt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_b_si, "cv_simd_cmpgt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_h_si, "cv_simd_cmpgt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_b_si, "cv_simd_cmpgt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_h_si, "cv_simd_cmpge_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_b_si, "cv_simd_cmpge_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_h_si, "cv_simd_cmpge_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_b_si, "cv_simd_cmpge_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_h_si, "cv_simd_cmplt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_b_si, "cv_simd_cmplt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_h_si, "cv_simd_cmplt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_b_si, "cv_simd_cmplt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_h_si, "cv_simd_cmple_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_b_si, "cv_simd_cmple_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_h_si, "cv_simd_cmple_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_b_si, "cv_simd_cmple_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_h_si, "cv_simd_cmpgtu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_b_si, "cv_simd_cmpgtu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_h_si, "cv_simd_cmpgtu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_b_si, "cv_simd_cmpgtu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_h_si, "cv_simd_cmpgeu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_b_si, "cv_simd_cmpgeu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_h_si, "cv_simd_cmpgeu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_b_si, "cv_simd_cmpgeu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_h_si, "cv_simd_cmpltu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_b_si, "cv_simd_cmpltu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_h_si, "cv_simd_cmpltu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_b_si, "cv_simd_cmpltu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_h_si, "cv_simd_cmpleu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_b_si, "cv_simd_cmpleu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_h_si, "cv_simd_cmpleu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_b_si, "cv_simd_cmpleu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +//COMPLEX NUMBER +RISCV_BUILTIN (cv_simd_cplxmul_r_si, "cv_simd_cplxmul_r", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxmul_i_si, "cv_simd_cplxmul_i", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxconj_si, "cv_simd_cplxconj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_subrotmj_si, "cv_simd_subrotmj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index adad2409fb6..32a14d03936 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -27,6 +27,164 @@ ;;CORE-V EVENT LOAD UNSPECV_CV_ELW + + ;;CORE-V SIMD + ;;CORE-V SIMD ALU + UNSPEC_CV_ADD_H + UNSPEC_CV_ADD_B + UNSPEC_CV_ADD_SC_H + UNSPEC_CV_ADD_SC_B + UNSPEC_CV_SUB_H + UNSPEC_CV_SUB_B + UNSPEC_CV_SUB_SC_H + UNSPEC_CV_SUB_SC_B + UNSPEC_CV_AVG_H + UNSPEC_CV_AVG_B + UNSPEC_CV_AVG_SC_H + UNSPEC_CV_AVG_SC_B + UNSPEC_CV_AVGU_H + UNSPEC_CV_AVGU_B + UNSPEC_CV_AVGU_SC_H + UNSPEC_CV_AVGU_SC_B + UNSPEC_CV_MIN_H + UNSPEC_CV_MIN_B + UNSPEC_CV_MIN_SC_H + UNSPEC_CV_MIN_SC_B + UNSPEC_CV_MINU_H + UNSPEC_CV_MINU_B + UNSPEC_CV_MINU_SC_H + UNSPEC_CV_MINU_SC_B + UNSPEC_CV_MAX_H + UNSPEC_CV_MAX_B + UNSPEC_CV_MAX_SC_H + UNSPEC_CV_MAX_SC_B + UNSPEC_CV_MAXU_H + UNSPEC_CV_MAXU_B + UNSPEC_CV_MAXU_SC_H + UNSPEC_CV_MAXU_SC_B + UNSPEC_CV_SRL_H + UNSPEC_CV_SRL_B + UNSPEC_CV_SRL_SC_H + UNSPEC_CV_SRL_SC_B + UNSPEC_CV_SRA_H + UNSPEC_CV_SRA_B + UNSPEC_CV_SRA_SC_H + UNSPEC_CV_SRA_SC_B + UNSPEC_CV_SLL_H + UNSPEC_CV_SLL_B + UNSPEC_CV_SLL_SC_H + UNSPEC_CV_SLL_SC_B + UNSPEC_CV_OR_H + UNSPEC_CV_OR_B + UNSPEC_CV_OR_SC_H + UNSPEC_CV_OR_SC_B + UNSPEC_CV_XOR_H + UNSPEC_CV_XOR_B + UNSPEC_CV_XOR_SC_H + UNSPEC_CV_XOR_SC_B + UNSPEC_CV_AND_H + UNSPEC_CV_AND_B + UNSPEC_CV_AND_SC_H + UNSPEC_CV_AND_SC_B + UNSPEC_CV_ABS_H + UNSPEC_CV_ABS_B + UNSPEC_CV_NEG_H + UNSPEC_CV_NEG_B + + ;;CORE-V SIMD BIT MANIPULATION + UNSPEC_CV_EXTRACT_H + UNSPEC_CV_EXTRACT_B + UNSPEC_CV_EXTRACTU_H + UNSPEC_CV_EXTRACTU_B + UNSPEC_CV_INSERT_H + UNSPEC_CV_INSERT_B + + ;;CORE-V SIMD DOT PRODUCT + UNSPEC_CV_DOTUP_H + UNSPEC_CV_DOTUP_B + UNSPEC_CV_DOTUP_SC_H + UNSPEC_CV_DOTUP_SC_B + UNSPEC_CV_DOTUSP_H + UNSPEC_CV_DOTUSP_B + UNSPEC_CV_DOTUSP_SC_H + UNSPEC_CV_DOTUSP_SC_B + UNSPEC_CV_DOTSP_H + UNSPEC_CV_DOTSP_B + UNSPEC_CV_DOTSP_SC_H + UNSPEC_CV_DOTSP_SC_B + UNSPEC_CV_SDOTUP_H + UNSPEC_CV_SDOTUP_B + UNSPEC_CV_SDOTUP_SC_H + UNSPEC_CV_SDOTUP_SC_B + UNSPEC_CV_SDOTUSP_H + UNSPEC_CV_SDOTUSP_B + UNSPEC_CV_SDOTUSP_SC_H + UNSPEC_CV_SDOTUSP_SC_B + UNSPEC_CV_SDOTSP_H + UNSPEC_CV_SDOTSP_B + UNSPEC_CV_SDOTSP_SC_H + UNSPEC_CV_SDOTSP_SC_B + + ;;CORE-V SIMD SHUFFLE AND PACK + UNSPEC_CV_SHUFFLE_H + UNSPEC_CV_SHUFFLE_SCI_H + UNSPEC_CV_SHUFFLE_B + UNSPEC_CV_SHUFFLE_SCI_B + UNSPEC_CV_SHUFFLE2_H + UNSPEC_CV_SHUFFLE2_B + UNSPEC_CV_PACKHI_H + UNSPEC_CV_PACKLO_H + UNSPEC_CV_PACKHI_B + UNSPEC_CV_PACKLO_B + + ;;CORE-V SIMD COMPARISON + UNSPEC_CV_CMPEQ_H + UNSPEC_CV_CMPEQ_B + UNSPEC_CV_CMPEQ_SC_H + UNSPEC_CV_CMPEQ_SC_B + UNSPEC_CV_CMPNE_H + UNSPEC_CV_CMPNE_B + UNSPEC_CV_CMPNE_SC_H + UNSPEC_CV_CMPNE_SC_B + UNSPEC_CV_CMPGT_H + UNSPEC_CV_CMPGT_B + UNSPEC_CV_CMPGT_SC_H + UNSPEC_CV_CMPGT_SC_B + UNSPEC_CV_CMPGE_H + UNSPEC_CV_CMPGE_B + UNSPEC_CV_CMPGE_SC_H + UNSPEC_CV_CMPGE_SC_B + UNSPEC_CV_CMPLT_H + UNSPEC_CV_CMPLT_B + UNSPEC_CV_CMPLT_SC_H + UNSPEC_CV_CMPLT_SC_B + UNSPEC_CV_CMPLE_H + UNSPEC_CV_CMPLE_B + UNSPEC_CV_CMPLE_SC_H + UNSPEC_CV_CMPLE_SC_B + UNSPEC_CV_CMPGTU_H + UNSPEC_CV_CMPGTU_B + UNSPEC_CV_CMPGTU_SC_H + UNSPEC_CV_CMPGTU_SC_B + UNSPEC_CV_CMPGEU_H + UNSPEC_CV_CMPGEU_B + UNSPEC_CV_CMPGEU_SC_H + UNSPEC_CV_CMPGEU_SC_B + UNSPEC_CV_CMPLTU_H + UNSPEC_CV_CMPLTU_B + UNSPEC_CV_CMPLTU_SC_H + UNSPEC_CV_CMPLTU_SC_B + UNSPEC_CV_CMPLEU_H + UNSPEC_CV_CMPLEU_B + UNSPEC_CV_CMPLEU_SC_H + UNSPEC_CV_CMPLEU_SC_B + + ;;CORE-V SIMD COMPLEX + UNSPEC_CV_CPLXMUL_R + UNSPEC_CV_CPLXMUL_I + UNSPEC_CV_CPLXCONJ + UNSPEC_CV_SUBROTMJ + ]) ;; XCVMAC extension. @@ -706,3 +864,1753 @@ [(set_attr "type" "load") (set_attr "mode" "SI")]) + +;;CORE-V SIMD +;;CORE-V SIMD ALU +(define_insn "riscv_cv_simd_add_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_ADD_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.h\\t%0,%1,%2 + cv.add.div2\\t%0,%1,%2 + cv.add.div4\\t%0,%1,%2 + cv.add.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_ADD_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.add.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.h\\t%0,%1,%2 + cv.add.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.b\\t%0,%1,%2 + cv.add.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUB_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.h\\t%0,%1,%2 + cv.sub.div2\\t%0,%1,%2 + cv.sub.div4\\t%0,%1,%2 + cv.sub.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SUB_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.h\\t%0,%1,%2 + cv.sub.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.b\\t%0,%1,%2 + cv.sub.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.h\\t%0,%1,%2 + cv.avg.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.b\\t%0,%1,%2 + cv.avg.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.h\\t%0,%1,%2 + cv.avgu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.b\\t%0,%1,%2 + cv.avgu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.h\\t%0,%1,%2 + cv.min.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.b\\t%0,%1,%2 + cv.min.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.h\\t%0,%1,%2 + cv.minu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.b\\t%0,%1,%2 + cv.minu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.h\\t%0,%1,%2 + cv.max.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.b\\t%0,%1,%2 + cv.max.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.h\\t%0,%1,%2 + cv.maxu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.b\\t%0,%1,%2 + cv.maxu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.h\\t%0,%1,%2 + cv.srl.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.b\\t%0,%1,%2 + cv.srl.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.h\\t%0,%1,%2 + cv.sra.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.b\\t%0,%1,%2 + cv.sra.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.h\\t%0,%1,%2 + cv.sll.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.b\\t%0,%1,%2 + cv.sll.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.h\\t%0,%1,%2 + cv.or.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.b\\t%0,%1,%2 + cv.or.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.h\\t%0,%1,%2 + cv.xor.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.b\\t%0,%1,%2 + cv.xor.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.h\\t%0,%1,%2 + cv.and.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.b\\t%0,%1,%2 + cv.and.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.h\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.b\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.h\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD BIT MANIPULATION +(define_insn "riscv_cv_simd_extract_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extract_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.h\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.b\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD DOT PRODUCT +(define_insn "riscv_cv_simd_dotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.h\\t%0,%1,%2 + cv.dotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.b\\t%0,%1,%2 + cv.dotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.h\\t%0,%1,%2 + cv.dotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.b\\t%0,%1,%2 + cv.dotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.h\\t%0,%1,%2 + cv.dotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.b\\t%0,%1,%2 + cv.dotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.h\\t%0,%1,%2 + cv.sdotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.b\\t%0,%1,%2 + cv.sdotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.h\\t%0,%1,%2 + cv.sdotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.b\\t%0,%1,%2 + cv.sdotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.h\\t%0,%1,%2 + cv.sdotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.b\\t%0,%1,%2 + cv.sdotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD SHUFFLE AND PACK +(define_insn "riscv_cv_simd_shuffle_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "const_int6_operand" "CV_simd_un6")] + UNSPEC_CV_SHUFFLE_SCI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.sci.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:QI 2 "const_int_operand" "CV_simd_un6,CV_simd_i01,CV_simd_i02,CV_simd_i03")] + UNSPEC_CV_SHUFFLE_SCI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.shufflei0.sci.b\\t%0,%1,%Y2 + cv.shufflei1.sci.b\\t%0,%1,%Y2 + cv.shufflei2.sci.b\\t%0,%1,%Y2 + cv.shufflei3.sci.b\\t%0,%1,%Y2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKHI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKLO_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKHI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packhi.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKLO_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packlo.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPARISON +(define_insn "riscv_cv_simd_cmpeq_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.h\\t%0,%1,%2 + cv.cmpeq.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.b\\t%0,%1,%2 + cv.cmpeq.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.h\\t%0,%1,%2 + cv.cmpne.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.b\\t%0,%1,%2 + cv.cmpne.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.h\\t%0,%1,%2 + cv.cmpgt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.b\\t%0,%1,%2 + cv.cmpgt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.h\\t%0,%1,%2 + cv.cmpge.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.b\\t%0,%1,%2 + cv.cmpge.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.h\\t%0,%1,%2 + cv.cmplt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.b\\t%0,%1,%2 + cv.cmplt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.h\\t%0,%1,%2 + cv.cmple.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.b\\t%0,%1,%2 + cv.cmple.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.h\\t%0,%1,%2 + cv.cmpgtu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.b\\t%0,%1,%2 + cv.cmpgtu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.h\\t%0,%1,%2 + cv.cmpgeu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.b\\t%0,%1,%2 + cv.cmpgeu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.h\\t%0,%1,%2 + cv.cmpltu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.b\\t%0,%1,%2 + cv.cmpltu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.h\\t%0,%1,%2 + cv.cmpleu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.b\\t%0,%1,%2 + cv.cmpleu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPLEX +(define_insn "riscv_cv_simd_cplxmul_r_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_R))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.r\\t%0,%1,%2 + cv.cplxmul.r.div2\\t%0,%1,%2 + cv.cplxmul.r.div4\\t%0,%1,%2 + cv.cplxmul.r.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxmul_i_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_I))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.i\\t%0,%1,%2 + cv.cplxmul.i.div2\\t%0,%1,%2 + cv.cplxmul.i.div4\\t%0,%1,%2 + cv.cplxmul.i.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxconj_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CV_CPLXCONJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cplxconj\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_subrotmj_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUBROTMJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.subrotmj\\t%0,%1,%2 + cv.subrotmj.div2\\t%0,%1,%2 + cv.subrotmj.div4\\t%0,%1,%2 + cv.subrotmj.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b1a79cae50a..c7f5291ca21 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -425,6 +425,26 @@ (ior (match_operand 0 "register_operand") (match_code "const_int"))) +(define_predicate "const_int6s_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -32, 31)"))) + +(define_predicate "int6s_operand" + (ior (match_operand 0 "const_int6s_operand") + (match_operand 0 "register_operand"))) + +(define_predicate "const_int2_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + +(define_predicate "const_int6_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) + +(define_predicate "int6_operand" + (ior (match_operand 0 "const_int6_operand") + (match_operand 0 "register_operand"))) + ;; Predicates for the V extension. (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 1932ff069c6..d457e306dd1 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -135,6 +135,7 @@ AVAIL (hint_pause, (!0)) AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) +AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 5f051df2277..449525b08f4 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -38,6 +38,10 @@ DEF_RISCV_FTYPE (1, (USI, UHI)) DEF_RISCV_FTYPE (1, (SI, QI)) DEF_RISCV_FTYPE (1, (SI, HI)) DEF_RISCV_FTYPE (2, (USI, UQI, UQI)) +DEF_RISCV_FTYPE (2, (USI, USI, UQI)) +DEF_RISCV_FTYPE (2, (USI, USI, UHI)) +DEF_RISCV_FTYPE (2, (USI, USI, QI)) +DEF_RISCV_FTYPE (2, (USI, USI, HI)) DEF_RISCV_FTYPE (2, (USI, UHI, UHI)) DEF_RISCV_FTYPE (2, (USI, USI, USI)) DEF_RISCV_FTYPE (2, (USI, USI, UQI)) @@ -50,6 +54,11 @@ DEF_RISCV_FTYPE (2, (UDI, UDI, UDI)) DEF_RISCV_FTYPE (2, (SI, USI, USI)) DEF_RISCV_FTYPE (2, (SI, SI, SI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI)) +DEF_RISCV_FTYPE (3, (USI, USI, USI, QI)) +DEF_RISCV_FTYPE (3, (USI, USI, UQI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, QI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, UHI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, HI, USI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, USI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, SI)) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 41626fa34e4..21e8385874d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5842,6 +5842,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) output_addr_const (file, newop); break; } + case 'Y': + { + unsigned int imm = (UINTVAL (op) & 63); + gcc_assert (imm <= 63); + rtx newop = GEN_INT (imm); + output_addr_const (file, newop); + break; + } default: switch (code) { diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 44ed6d69da2..f92cfb9a69a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -425,6 +425,8 @@ Mask(XCVALU) Var(riscv_xcv_subext) Mask(XCVELW) Var(riscv_xcv_subext) +Mask(XCVSIMD) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b9129d1b464..51841e49ca0 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -24228,6 +24228,8 @@ All of these functions are declared in the include file @file{riscv_vector.h}. @node CORE-V Built-in Functions @subsection CORE-V Built-in Functions +For more information on all CORE-V built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md} These built-in functions are available for the CORE-V MAC machine architecture. For more information on CORE-V built-ins, please see @@ -24407,6 +24409,890 @@ architecture. For more information on CORE-V ELW builtins, please see Generated assembler @code{cv.elw} @end deftypefn +These built-in functions are available for the CORE-V SIMD machine +architecture. For more information on CORE-V SIMD built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-816-bit-simd-builtins-xcvsimd} + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_b (uint32_t, uint32_t) +Generated assembler @code{cv.add.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.add.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.add.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_b (uint32_t, uint32_t) +Generated assembler @code{cv.sub.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sub.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sub.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_h (uint32_t, uint32_t) +Generated assembler @code{cv.avg.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_b (uint32_t, uint32_t) +Generated assembler @code{cv.avg.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.avg.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.avg.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_h (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_b (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.avgu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.avgu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_h (uint32_t, uint32_t) +Generated assembler @code{cv.min.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_b (uint32_t, uint32_t) +Generated assembler @code{cv.min.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.min.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.min.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_h (uint32_t, uint32_t) +Generated assembler @code{cv.minu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_b (uint32_t, uint32_t) +Generated assembler @code{cv.minu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.minu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.minu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_h (uint32_t, uint32_t) +Generated assembler @code{cv.max.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_b (uint32_t, uint32_t) +Generated assembler @code{cv.max.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.max.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.max.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_h (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_b (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.maxu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.maxu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_h (uint32_t, uint32_t) +Generated assembler @code{cv.srl.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_b (uint32_t, uint32_t) +Generated assembler @code{cv.srl.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.srl.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.srl.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_h (uint32_t, uint32_t) +Generated assembler @code{cv.sra.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_b (uint32_t, uint32_t) +Generated assembler @code{cv.sra.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sra.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sra.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_h (uint32_t, uint32_t) +Generated assembler @code{cv.sll.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_b (uint32_t, uint32_t) +Generated assembler @code{cv.sll.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sll.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sll.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_h (uint32_t, uint32_t) +Generated assembler @code{cv.or.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_b (uint32_t, uint32_t) +Generated assembler @code{cv.or.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.or.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.or.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_h (uint32_t, uint32_t) +Generated assembler @code{cv.xor.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_b (uint32_t, uint32_t) +Generated assembler @code{cv.xor.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.xor.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.xor.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_h (uint32_t, uint32_t) +Generated assembler @code{cv.and.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_b (uint32_t, uint32_t) +Generated assembler @code{cv.and.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.and.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.and.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_h (uint32_t) +Generated assembler @code{cv.abs.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_b (uint32_t) +Generated assembler @code{cv.abs.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.dotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.dotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint16_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint8_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_h (uint32_t, uint6_t) +Generated assembler @code{cv.extract.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_b (uint32_t, uint6_t) +Generated assembler @code{cv.extract.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_h (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_b (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_h (uint32_t, uint32_t) +Generated assembler @code{cv.insert.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_b (uint32_t, uint32_t) +Generated assembler @code{cv.insert.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_h (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_b (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_sci_h (uint32_t, uint4_t) +Generated assembler @code{cv.shuffle.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei0_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei0.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei1_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei1.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei2_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei2.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei3_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei3.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packhi.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packlo.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpeq.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpeq.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpne.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpne.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpgt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpgt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpge.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpge.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmplt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmplt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmple.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmple.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgtu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgtu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgeu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgeu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpltu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpltu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpleu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpleu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxconj (uint32_t) +Generated assembler @code{cv.cplxconj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div8} +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 8082100a3c9..798dabee6bb 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2505,6 +2505,9 @@ Test system has support for the CORE-V ALU extension. @item cv_elw Test system has support for the CORE-V ELW extension. +@item cv_simd +Test system has support for the CORE-V SIMD extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c new file mode 100644 index 00000000000..c8d58724786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c new file mode 100644 index 00000000000..9ebb9053e35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c new file mode 100644 index 00000000000..b362e904407 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c new file mode 100644 index 00000000000..8e885a1062b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c new file mode 100644 index 00000000000..3edea7bb990 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c new file mode 100644 index 00000000000..df43c202b9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c new file mode 100644 index 00000000000..27b2cc38f4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c new file mode 100644 index 00000000000..43f37a88cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c new file mode 100644 index 00000000000..99cd7b40731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c new file mode 100644 index 00000000000..6be001d4c11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c new file mode 100644 index 00000000000..770c3e59e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c new file mode 100644 index 00000000000..616a9235a67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c new file mode 100644 index 00000000000..73ceba6cbed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c new file mode 100644 index 00000000000..21ae43aeb5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c new file mode 100644 index 00000000000..f2582d4e3ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c new file mode 100644 index 00000000000..a72a9effcd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c new file mode 100644 index 00000000000..41cd20f2536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c new file mode 100644 index 00000000000..a17a9233120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c new file mode 100644 index 00000000000..8f7c62c8b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c new file mode 100644 index 00000000000..7e00a5b2b7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c new file mode 100644 index 00000000000..f024d0e5d7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c new file mode 100644 index 00000000000..7ac9cb2704a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c new file mode 100644 index 00000000000..8fc1eb03417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c new file mode 100644 index 00000000000..5a0adcd68a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c new file mode 100644 index 00000000000..c1aeb7e6874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c new file mode 100644 index 00000000000..74c5a17588c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c new file mode 100644 index 00000000000..32b509ecd53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c new file mode 100644 index 00000000000..4e4bbeeee04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c new file mode 100644 index 00000000000..4443f65f7c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c new file mode 100644 index 00000000000..0207c3210e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c new file mode 100644 index 00000000000..b8da488a814 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c new file mode 100644 index 00000000000..e8e2e62e9cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c new file mode 100644 index 00000000000..b669ea19ca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c new file mode 100644 index 00000000000..fb5f4317cd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c new file mode 100644 index 00000000000..5d5a5a96be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c new file mode 100644 index 00000000000..ab32a39091c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c new file mode 100644 index 00000000000..6f55da30358 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c new file mode 100644 index 00000000000..760cd48d991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c new file mode 100644 index 00000000000..9453079ee5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c new file mode 100644 index 00000000000..8f339103572 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c new file mode 100644 index 00000000000..3f2d2a9ccfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c new file mode 100644 index 00000000000..b19e437ddc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c new file mode 100644 index 00000000000..adb26c1c66b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c new file mode 100644 index 00000000000..d14ca9a7837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c new file mode 100644 index 00000000000..22c2218a911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c new file mode 100644 index 00000000000..1d7f671eb42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c new file mode 100644 index 00000000000..18bee44f90d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c new file mode 100644 index 00000000000..a1adf919610 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c new file mode 100644 index 00000000000..f3823ff950b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c new file mode 100644 index 00000000000..ee3a5b2ac3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c new file mode 100644 index 00000000000..7ae45ff94dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c new file mode 100644 index 00000000000..ce6f280ae4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c new file mode 100644 index 00000000000..acd0c2c13aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c new file mode 100644 index 00000000000..e3260f986ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c new file mode 100644 index 00000000000..37f1f8b81f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c new file mode 100644 index 00000000000..34e4e980868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c new file mode 100644 index 00000000000..973b11e663a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c new file mode 100644 index 00000000000..532aabbd683 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c new file mode 100644 index 00000000000..cfa0abcd545 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c new file mode 100644 index 00000000000..9554172ab2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c new file mode 100644 index 00000000000..f2d9e659b89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c new file mode 100644 index 00000000000..194a70480f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c new file mode 100644 index 00000000000..dab59c6e95b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c new file mode 100644 index 00000000000..27da60ac96f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c new file mode 100644 index 00000000000..f9fd78e12be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c new file mode 100644 index 00000000000..0cacf8dc2ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c new file mode 100644 index 00000000000..60c378a5c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c new file mode 100644 index 00000000000..a2bb0dffe53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c new file mode 100644 index 00000000000..0f9d986f8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c new file mode 100644 index 00000000000..7c025c7aba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c new file mode 100644 index 00000000000..4b522da48dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c new file mode 100644 index 00000000000..12fa58be89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..1ba74ff8ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..19684717e95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c new file mode 100644 index 00000000000..a65464e348d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c new file mode 100644 index 00000000000..42145083ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c new file mode 100644 index 00000000000..51e9154ff60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c new file mode 100644 index 00000000000..28b423f5731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c new file mode 100644 index 00000000000..b5281bd7230 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c new file mode 100644 index 00000000000..5545b5e6037 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..7db3f1c94f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..1af83c57070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c new file mode 100644 index 00000000000..10133fe4907 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c new file mode 100644 index 00000000000..a507e016496 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c new file mode 100644 index 00000000000..1ea67024cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c new file mode 100644 index 00000000000..499e5780381 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c new file mode 100644 index 00000000000..d7c9d4ed212 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 3); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c new file mode 100644 index 00000000000..e10389e6995 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 1); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c new file mode 100644 index 00000000000..3fe01498356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c @@ -0,0 +1,1765 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 20); +} + + +int +foo5 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + + +int +foo6 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 20); +} + + +int +foo7 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + + +int +foo8 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + + +int +foo9 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + + +int +foo10 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 20); +} + + +int +foo11 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + + +int +foo12 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 20); +} + + +int +foo13 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + + +int +foo14 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + + +int +foo15 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + + +int +foo16 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 20); +} + + +int +foo17 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + + +int +foo18 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 20); +} + + +int +foo19 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + + +int +foo20 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + + +int +foo21 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + + +int +foo22 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 20); +} + + +int +foo23 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + + +int +foo24 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 20); +} + + +int +foo25 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + + +int +foo26 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + + +int +foo27 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + + +int +foo28 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 20); +} + + +int +foo29 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + + +int +foo30 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 20); +} + + +int +foo31 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + + +int +foo32 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + + +int +foo33 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + + +int +foo34 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 20); +} + + +int +foo35 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + + +int +foo36 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 20); +} + + +int +foo37 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + + +int +foo38 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + + +int +foo39 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + + +int +foo40 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 20); +} + + +int +foo41 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + + +int +foo42 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 20); +} + + +int +foo43 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + + +int +foo44 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + + +int +foo45 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + + +int +foo46 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 20); +} + + +int +foo47 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + + +int +foo48 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 20); +} + + +int +foo49 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + + +int +foo50 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + + +int +foo51 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, b); +} + + +int +foo52 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, 20); +} + + +int +foo53 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, b); +} + + +int +foo54 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, 20); +} + + +int +foo55 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + + +int +foo56 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + + +int +foo57 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, b); +} + + +int +foo58 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, 20); +} + + +int +foo59 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, b); +} + + +int +foo60 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, 20); +} + + +int +foo61 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + + +int +foo62 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + + +int +foo63 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, b); +} + + +int +foo64 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, 20); +} + + +int +foo65 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, b); +} + + +int +foo66 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, 20); +} + + +int +foo67 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + + +int +foo68 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + + +int +foo69 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + + +int +foo70 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 20); +} + + +int +foo71 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + + +int +foo72 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 20); +} + + +int +foo73 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + + +int +foo74 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + + +int +foo75 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + + +int +foo76 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 20); +} + + +int +foo77 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + + +int +foo78 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 20); +} + + +int +foo79 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + + +int +foo80 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + + +int +foo81 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + + +int +foo82 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 20); +} + + +int +foo83 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + + +int +foo84 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 20); +} + + +int +foo85 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + + +int +foo86 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + + +int +foo87 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + + +int +foo88 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + + +int +foo89 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + + +int +foo90 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 20); +} + + +int +foo91 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + + +int +foo92 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 20); +} + + +int +foo93 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + + +int +foo94 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + + +int +foo95 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + + +int +foo96 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 20); +} + + +int +foo97 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + + +int +foo98 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 20); +} + + +int +foo99 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + + +int +foo100 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + + +int +foo101 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + + +int +foo102 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 20); +} + + +int +foo103 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + + +int +foo104 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 20); +} + + +int +foo105 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + + +int +foo106 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + + +int +foo107 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + + +int +foo108 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 20, b); +} + + +int +foo109 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + + +int +foo110 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 20, b); +} + + +int +foo111 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + + +int +foo112 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + + +int +foo113 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + + +int +foo114 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 20, b); +} + + +int +foo115 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + + +int +foo116 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 20, b); +} + + +int +foo117 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + + +int +foo118 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + + +int +foo119 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + + +int +foo120 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 20, b); +} + + +int +foo121 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + + +int +foo122 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 20, b); +} + + +int +foo123 (int a) +{ + return __builtin_riscv_cv_simd_extract_h(a, 20); +} + + +int +foo124 (int a) +{ + return __builtin_riscv_cv_simd_extract_b(a, 20); +} + + +int +foo125 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h(a, 20); +} + + +int +foo126 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b(a, 20); +} + + +int +foo127 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h(a, b, 20); +} + + +int +foo128 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b(a, b, 20); +} + + +int +foo129 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_h(a, b); +} + + +int +foo130 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_b(a, b); +} + + +int +foo131 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 20); +} + + +int +foo132 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 0); +} + + +int +foo133 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 64); +} + + +int +foo134 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 128); +} + + +int +foo135 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 192); +} + + +int +foo136 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + + +int +foo137 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + + +int +foo138 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + + +int +foo139 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + + +int +foo140 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + + +int +foo141 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + + +int +foo142 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + + +int +foo143 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + + +int +foo144 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + + +int +foo145 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 20); +} + + +int +foo146 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + + +int +foo147 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 20); +} + + +int +foo148 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + + +int +foo149 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + + +int +foo150 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + + +int +foo151 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 20); +} + + +int +foo152 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + + +int +foo153 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 20); +} + + +int +foo154 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + + +int +foo155 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + + +int +foo156 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + + +int +foo157 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 20); +} + + +int +foo158 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + + +int +foo159 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 20); +} + + +int +foo160 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + + +int +foo161 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + + +int +foo162 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + + +int +foo163 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 20); +} + + +int +foo164 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + + +int +foo165 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 20); +} + + +int +foo166 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + + +int +foo167 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + + +int +foo168 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + + +int +foo169 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 20); +} + + +int +foo170 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + + +int +foo171 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 20); +} + + +int +foo172 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + + +int +foo173 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + + +int +foo174 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + + +int +foo175 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 20); +} + + +int +foo176 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + + +int +foo177 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 20); +} + + +int +foo178 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + + +int +foo179 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + + +int +foo180 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + + +int +foo181 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 20); +} + + +int +foo182 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + + +int +foo183 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 20); +} + + +int +foo184 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + + +int +foo185 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + + +int +foo186 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + + +int +foo187 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 20); +} + + +int +foo188 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + + +int +foo189 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 20); +} + + +int +foo190 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + + +int +foo191 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + + +int +foo192 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + + +int +foo193 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 20); +} + + +int +foo194 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + + +int +foo195 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 20); +} + + +int +foo196 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + + +int +foo197 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + + +int +foo198 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + + +int +foo199 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 20); +} + + +int +foo200 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + + +int +foo201 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 20); +} + + +int +foo202 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + + +int +foo203 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + + +int +foo204 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + + +int +foo205 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + + +int +foo206 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + + +int +foo207 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + + +int +foo208 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + + +int +foo209 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + + +int +foo210 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + + +int +foo211 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + + +int +foo212 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + + +int +foo213 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + + +int +foo214 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + + +int +foo215 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + + +int +foo216 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + + +int +foo217 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + + +int +foo218 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + + +int +foo219 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + + +int +foo220 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c new file mode 100644 index 00000000000..05c5b078129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c new file mode 100644 index 00000000000..a24308b38bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c new file mode 100644 index 00000000000..a82ceba459a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c new file mode 100644 index 00000000000..baa52d52f62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c new file mode 100644 index 00000000000..e6a96958f02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c new file mode 100644 index 00000000000..ee95b139c58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c new file mode 100644 index 00000000000..48a3c6f7922 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c new file mode 100644 index 00000000000..0a776774596 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c new file mode 100644 index 00000000000..474d96ddf4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c new file mode 100644 index 00000000000..493bbdcd92d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c new file mode 100644 index 00000000000..30ede85c2e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c new file mode 100644 index 00000000000..a99b012c425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c new file mode 100644 index 00000000000..43582b28f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c new file mode 100644 index 00000000000..e44113bbae4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c new file mode 100644 index 00000000000..eec0a56f959 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c new file mode 100644 index 00000000000..6fc29abc3fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c new file mode 100644 index 00000000000..3f8bb7ceced --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c new file mode 100644 index 00000000000..2b6ecb0fb18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c new file mode 100644 index 00000000000..d6bd54f97e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c new file mode 100644 index 00000000000..cff54f344f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c new file mode 100644 index 00000000000..cd8b2dcb0dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c new file mode 100644 index 00000000000..95352fe9b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c new file mode 100644 index 00000000000..286d36640aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c new file mode 100644 index 00000000000..2d7f1b0bcf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c new file mode 100644 index 00000000000..deb25d022a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c new file mode 100644 index 00000000000..23489301e30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c new file mode 100644 index 00000000000..14e5baa27f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c new file mode 100644 index 00000000000..e0d7f587816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..2f314142e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..03481e24c9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c new file mode 100644 index 00000000000..63017c87c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c new file mode 100644 index 00000000000..70f12643c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c new file mode 100644 index 00000000000..812faab72c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c new file mode 100644 index 00000000000..546a13b2812 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c new file mode 100644 index 00000000000..f0b522160f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c new file mode 100644 index 00000000000..8078c96702b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..d1ce8fe62de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..55410209450 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c new file mode 100644 index 00000000000..08c7a819b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c new file mode 100644 index 00000000000..7475a844ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c new file mode 100644 index 00000000000..fe4fcc613d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c new file mode 100644 index 00000000000..024e4e23af2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c new file mode 100644 index 00000000000..7b971c1dcf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 64); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 127); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c new file mode 100644 index 00000000000..63995981141 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +unsigned int +foo1 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 128); +} + +unsigned int +foo2 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 191); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c new file mode 100644 index 00000000000..6f02cb5dd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 192); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c new file mode 100644 index 00000000000..1392e7bfb1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c new file mode 100644 index 00000000000..84eba7515e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c new file mode 100644 index 00000000000..fa56156185a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c new file mode 100644 index 00000000000..12a1ffd3c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c new file mode 100644 index 00000000000..c5693023c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c new file mode 100644 index 00000000000..033aabb633f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c new file mode 100644 index 00000000000..133d9199374 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c new file mode 100644 index 00000000000..2830f44c3f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c new file mode 100644 index 00000000000..ae848b1860e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c new file mode 100644 index 00000000000..797524ee783 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c new file mode 100644 index 00000000000..e62f8fa561c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c new file mode 100644 index 00000000000..6f7592a83b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c new file mode 100644 index 00000000000..45120bcafda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c new file mode 100644 index 00000000000..e79a001508c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c new file mode 100644 index 00000000000..d8630f7ac63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c new file mode 100644 index 00000000000..efad60017b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c new file mode 100644 index 00000000000..a80e441f488 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c new file mode 100644 index 00000000000..30ce64689bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c new file mode 100644 index 00000000000..ac6d27d0eda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c new file mode 100644 index 00000000000..8ecac97a9e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c new file mode 100644 index 00000000000..c77395d31c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c new file mode 100644 index 00000000000..e53c6d1bbab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c new file mode 100644 index 00000000000..ebd431efda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c new file mode 100644 index 00000000000..56ba1cd4d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c new file mode 100644 index 00000000000..d07bceabe52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c new file mode 100644 index 00000000000..7fe0f79d8a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c new file mode 100644 index 00000000000..5227a2bf862 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fac32fb3d0e..6829978e330 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13345,6 +13345,19 @@ proc check_effective_target_cv_elw { } { } "-march=rv32i_xcvelw" ] } +# Return 1 if the CORE-V SIMD extension is available. +proc check_effective_target_cv_simd { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_simd object { + void foo (void) + { + asm ("cv.add.sc.b x0, x0, x0"); + } + } "-march=rv32i_xcvsimd" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx) -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/2] RISC-V: Fix XCValu test 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett @ 2024-01-16 16:35 ` Mary Bennett 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2 siblings, 0 replies; 12+ messages in thread From: Mary Bennett @ 2024-01-16 16:35 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-alu-fail-compile.c: Change warning to error. --- .../gcc.target/riscv/cv-alu-fail-compile.c | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c index bbdb2d58c3f..89c7f6f2f5a 100644 --- a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c +++ b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c @@ -7,26 +7,26 @@ extern int d; int foo(int a, int b, int c) { - d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_sletu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_addN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_extbs (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_extbz (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_exths (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_exthz (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_min (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_max (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_sletu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_addN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_extbs (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_extbz (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_exths (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_exthz (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_min (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_max (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ return d; } -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2024-01-16 16:35 ` [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett @ 2024-01-16 17:13 ` Mary Bennett 2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett ` (2 more replies) 2 siblings, 3 replies; 12+ messages in thread From: Mary Bennett @ 2024-01-16 17:13 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett v2 -> v3: * Removed duplicate ftype. This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 8 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + 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gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett @ 2024-01-16 17:13 ` Mary Bennett 2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett 2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng 2 siblings, 0 replies; 12+ messages in thread From: Mary Bennett @ 2024-01-16 17:13 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVbitmanip. * config/riscv/constraints.md: Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/predicates.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'. * doc/extend.texi: Add XCVbitmanip builtin documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-simd-abs-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-abs-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-add-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-and-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxconj-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extract-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-extractu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-insert-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-march-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-max-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-min-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-neg-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-or-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-compile-1.c: New test. * gcc.target/riscv/cv-simd-pack-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-packhi-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-packlo-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c: New test. * gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-h-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c: New test. * gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c: New test. * lib/target-supports.exp: Add proc for XCVsimd extension. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 8 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + .../riscv/cv-simd-add-div4-compile-1.c | 11 + .../riscv/cv-simd-add-div8-compile-1.c | 11 + .../riscv/cv-simd-add-h-compile-1.c | 11 + .../riscv/cv-simd-add-sc-b-compile-1.c | 30 + .../riscv/cv-simd-add-sc-h-compile-1.c | 30 + .../riscv/cv-simd-and-b-compile-1.c | 11 + .../riscv/cv-simd-and-h-compile-1.c | 11 + .../riscv/cv-simd-and-sc-b-compile-1.c | 30 + .../riscv/cv-simd-and-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avg-b-compile-1.c | 11 + .../riscv/cv-simd-avg-h-compile-1.c | 11 + .../riscv/cv-simd-avg-sc-b-compile-1.c | 30 + .../riscv/cv-simd-avg-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avgu-b-compile-1.c | 11 + .../riscv/cv-simd-avgu-h-compile-1.c | 11 + .../riscv/cv-simd-avgu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-avgu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpeq-b-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-h-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpeq-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpge-b-compile-1.c | 11 + .../riscv/cv-simd-cmpge-h-compile-1.c | 11 + .../riscv/cv-simd-cmpge-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpge-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgeu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpgt-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpgt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgtu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmple-b-compile-1.c | 11 + .../riscv/cv-simd-cmple-h-compile-1.c | 11 + .../riscv/cv-simd-cmple-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmple-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpleu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpleu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmplt-b-compile-1.c | 11 + .../riscv/cv-simd-cmplt-h-compile-1.c | 11 + .../riscv/cv-simd-cmplt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmplt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpltu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpltu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpne-b-compile-1.c | 11 + .../riscv/cv-simd-cmpne-h-compile-1.c | 11 + .../riscv/cv-simd-cmpne-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpne-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cplxconj-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-div8-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div2-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div4-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-r-div8-compile-1.c | 11 + .../riscv/cv-simd-dotsp-b-compile-1.c | 11 + .../riscv/cv-simd-dotsp-h-compile-1.c | 11 + .../riscv/cv-simd-dotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-dotup-b-compile-1.c | 11 + .../riscv/cv-simd-dotup-h-compile-1.c | 11 + .../riscv/cv-simd-dotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-dotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-dotusp-b-compile-1.c | 11 + .../riscv/cv-simd-dotusp-h-compile-1.c | 11 + .../riscv/cv-simd-dotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-dotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-extract-b-compile-1.c | 23 + .../riscv/cv-simd-extract-h-compile-1.c | 23 + .../riscv/cv-simd-extractu-b-compile-1.c | 23 + .../riscv/cv-simd-extractu-h-compile-1.c | 23 + .../riscv/cv-simd-insert-b-compile-1.c | 23 + .../riscv/cv-simd-insert-h-compile-1.c | 23 + .../riscv/cv-simd-march-compile-1.c | 1765 +++++++++++++++ .../riscv/cv-simd-max-b-compile-1.c | 11 + .../riscv/cv-simd-max-h-compile-1.c | 11 + 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.../riscv/cv-simd-pack-h-compile-1.c | 11 + .../riscv/cv-simd-packhi-b-compile-1.c | 11 + .../riscv/cv-simd-packlo-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotsp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotsp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-sdotup-b-compile-1.c | 11 + .../riscv/cv-simd-sdotup-h-compile-1.c | 11 + .../riscv/cv-simd-sdotup-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sdotup-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sdotusp-b-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-h-compile-1.c | 11 + .../riscv/cv-simd-sdotusp-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sdotusp-sc-h-compile-1.c | 30 + .../riscv/cv-simd-shuffle-sci-h-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-b-compile-1.c | 11 + .../riscv/cv-simd-shuffle2-h-compile-1.c | 11 + .../riscv/cv-simd-shufflei0-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei1-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei2-sci-b-compile-1.c | 19 + .../riscv/cv-simd-shufflei3-sci-b-compile-1.c | 19 + .../riscv/cv-simd-sll-b-compile-1.c | 11 + .../riscv/cv-simd-sll-h-compile-1.c | 11 + .../riscv/cv-simd-sll-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sll-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sra-b-compile-1.c | 11 + .../riscv/cv-simd-sra-h-compile-1.c | 11 + .../riscv/cv-simd-sra-sc-b-compile-1.c | 24 + .../riscv/cv-simd-sra-sc-h-compile-1.c | 24 + .../riscv/cv-simd-srl-b-compile-1.c | 11 + .../riscv/cv-simd-srl-h-compile-1.c | 11 + .../riscv/cv-simd-srl-sc-b-compile-1.c | 24 + .../riscv/cv-simd-srl-sc-h-compile-1.c | 24 + .../riscv/cv-simd-sub-b-compile-1.c | 11 + .../riscv/cv-simd-sub-div2-compile-1.c | 11 + .../riscv/cv-simd-sub-div4-compile-1.c | 11 + .../riscv/cv-simd-sub-div8-compile-1.c | 11 + .../riscv/cv-simd-sub-h-compile-1.c | 11 + .../riscv/cv-simd-sub-sc-b-compile-1.c | 30 + .../riscv/cv-simd-sub-sc-h-compile-1.c | 30 + .../riscv/cv-simd-subrotmj-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div2-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div4-compile-1.c | 11 + .../riscv/cv-simd-subrotmj-div8-compile-1.c | 11 + .../riscv/cv-simd-xor-b-compile-1.c | 11 + .../riscv/cv-simd-xor-h-compile-1.c | 11 + .../riscv/cv-simd-xor-sc-b-compile-1.c | 30 + .../riscv/cv-simd-xor-sc-h-compile-1.c | 30 + gcc/testsuite/lib/target-supports.exp | 13 + 173 files changed, 7662 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c create mode 100644 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gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0301d170a41..eaba54172c0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -355,6 +355,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1730,6 +1731,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, + {"xcvsimd", &gcc_options::x_riscv_xcv_subext, MASK_XCVSIMD}, {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index ee1c12b2e51..41acaea04eb 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -55,6 +55,11 @@ (and (match_code "const_int") (match_test "ival == 2"))) +(define_constraint "c03" + "Constant value 3" + (and (match_code "const_int") + (match_test "ival == 3"))) + (define_constraint "c04" "Constant value 4" (and (match_code "const_int") @@ -262,3 +267,28 @@ (and (match_code "const_int") (and (match_test "IN_RANGE (ival, 0, 1073741823)") (match_test "exact_log2 (ival + 1) != -1")))) + +(define_constraint "CV_simd_si6" + "A 6-bit signed immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -32, 31)"))) + +(define_constraint "CV_simd_un6" + "A 6-bit unsigned immediate for SIMD." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 0, 63)"))) + +(define_constraint "CV_simd_i01" + "Shifting immediate for SIMD shufflei1." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 64, 127)"))) + +(define_constraint "CV_simd_i02" + "Shifting immediate for SIMD shufflei2." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -128, -65)"))) + +(define_constraint "CV_simd_i03" + "Shifting immediate for SIMD shufflei3." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -64, -1)"))) diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def index 3b9ec029d06..9157529fd4c 100644 --- a/gcc/config/riscv/corev.def +++ b/gcc/config/riscv/corev.def @@ -44,3 +44,159 @@ RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_ // XCVELW RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw), + +// XCVSIMD +//ALU Operations +RISCV_BUILTIN (cv_simd_add_h_si, "cv_simd_add_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_add_b_si, "cv_simd_add_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_h_si, "cv_simd_add_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_add_sc_b_si, "cv_simd_add_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_h_si, "cv_simd_sub_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_b_si, "cv_simd_sub_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_h_si, "cv_simd_sub_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sub_sc_b_si, "cv_simd_sub_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_h_si, "cv_simd_avg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_b_si, "cv_simd_avg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_h_si, "cv_simd_avg_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_avg_sc_b_si, "cv_simd_avg_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_h_si, "cv_simd_avgu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_b_si, "cv_simd_avgu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_h_si, "cv_simd_avgu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_avgu_sc_b_si, "cv_simd_avgu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_min_h_si, "cv_simd_min_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_b_si, "cv_simd_min_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_h_si, "cv_simd_min_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_min_sc_b_si, "cv_simd_min_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_h_si, "cv_simd_minu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_b_si, "cv_simd_minu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_h_si, "cv_simd_minu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_minu_sc_b_si, "cv_simd_minu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_max_h_si, "cv_simd_max_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_b_si, "cv_simd_max_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_h_si, "cv_simd_max_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_max_sc_b_si, "cv_simd_max_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_h_si, "cv_simd_maxu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_b_si, "cv_simd_maxu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_h_si, "cv_simd_maxu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_maxu_sc_b_si, "cv_simd_maxu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_h_si, "cv_simd_srl_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_b_si, "cv_simd_srl_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_h_si, "cv_simd_srl_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_srl_sc_b_si, "cv_simd_srl_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_h_si, "cv_simd_sra_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_b_si, "cv_simd_sra_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_h_si, "cv_simd_sra_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sra_sc_b_si, "cv_simd_sra_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_h_si, "cv_simd_sll_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_b_si, "cv_simd_sll_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_h_si, "cv_simd_sll_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_sll_sc_b_si, "cv_simd_sll_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_or_h_si, "cv_simd_or_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_b_si, "cv_simd_or_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_h_si, "cv_simd_or_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_or_sc_b_si, "cv_simd_or_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_h_si, "cv_simd_xor_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_b_si, "cv_simd_xor_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_h_si, "cv_simd_xor_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_xor_sc_b_si, "cv_simd_xor_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_and_h_si, "cv_simd_and_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_b_si, "cv_simd_and_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_h_si, "cv_simd_and_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_and_sc_b_si, "cv_simd_and_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_h_si, "cv_simd_abs_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_abs_b_si, "cv_simd_abs_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_h_si, "cv_simd_neg_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_neg_b_si, "cv_simd_neg_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +//BIT MANIPULATION +RISCV_BUILTIN (cv_simd_extract_h_si, "cv_simd_extract_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extract_b_si, "cv_simd_extract_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_h_si, "cv_simd_extractu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_extractu_b_si, "cv_simd_extractu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_h_si, "cv_simd_insert_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_insert_b_si, "cv_simd_insert_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_QI, cvsimd), +//DOT PRODUCT +RISCV_BUILTIN (cv_simd_dotup_h_si, "cv_simd_dotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_b_si, "cv_simd_dotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_h_si, "cv_simd_dotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_dotup_sc_b_si, "cv_simd_dotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_h_si, "cv_simd_dotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_b_si, "cv_simd_dotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_h_si, "cv_simd_dotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotusp_sc_b_si, "cv_simd_dotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_h_si, "cv_simd_dotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_b_si, "cv_simd_dotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_h_si, "cv_simd_dotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_dotsp_sc_b_si, "cv_simd_dotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_h_si, "cv_simd_sdotup_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_b_si, "cv_simd_sdotup_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_h_si, "cv_simd_sdotup_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotup_sc_b_si, "cv_simd_sdotup_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_h_si, "cv_simd_sdotusp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_b_si, "cv_simd_sdotusp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_h_si, "cv_simd_sdotusp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotusp_sc_b_si, "cv_simd_sdotusp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_h_si, "cv_simd_sdotsp_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_b_si, "cv_simd_sdotsp_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_h_si, "cv_simd_sdotsp_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_sdotsp_sc_b_si, "cv_simd_sdotsp_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI_USI, cvsimd), +//SHUFFLE AND PACK +RISCV_BUILTIN (cv_simd_shuffle_h_si, "cv_simd_shuffle_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_h_si, "cv_simd_shuffle_sci_h",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_b_si, "cv_simd_shuffle_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle_sci_b_si, "cv_simd_shuffle_sci_b",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_h_si, "cv_simd_shuffle2_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_shuffle2_b_si, "cv_simd_shuffle2_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_h_si, "cv_simd_packhi_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_h_si, "cv_simd_packlo_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_si, "cv_simd_pack", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_pack_h_si, "cv_simd_pack_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packhi_b_si, "cv_simd_packhi_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//RISCV_BUILTIN (cv_simd_packlo_b_si, "cv_simd_packlo_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI, cvsimd), +//COMPARISON OPERATIONS +RISCV_BUILTIN (cv_simd_cmpeq_h_si, "cv_simd_cmpeq_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_b_si, "cv_simd_cmpeq_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_h_si, "cv_simd_cmpeq_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpeq_sc_b_si, "cv_simd_cmpeq_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_h_si, "cv_simd_cmpne_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_b_si, "cv_simd_cmpne_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_h_si, "cv_simd_cmpne_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpne_sc_b_si, "cv_simd_cmpne_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_h_si, "cv_simd_cmpgt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_b_si, "cv_simd_cmpgt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_h_si, "cv_simd_cmpgt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgt_sc_b_si, "cv_simd_cmpgt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_h_si, "cv_simd_cmpge_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_b_si, "cv_simd_cmpge_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_h_si, "cv_simd_cmpge_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpge_sc_b_si, "cv_simd_cmpge_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_h_si, "cv_simd_cmplt_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_b_si, "cv_simd_cmplt_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_h_si, "cv_simd_cmplt_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmplt_sc_b_si, "cv_simd_cmplt_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_h_si, "cv_simd_cmple_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_b_si, "cv_simd_cmple_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_h_si, "cv_simd_cmple_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_HI, cvsimd), +RISCV_BUILTIN (cv_simd_cmple_sc_b_si, "cv_simd_cmple_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_QI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_h_si, "cv_simd_cmpgtu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_b_si, "cv_simd_cmpgtu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_h_si, "cv_simd_cmpgtu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgtu_sc_b_si, "cv_simd_cmpgtu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_h_si, "cv_simd_cmpgeu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_b_si, "cv_simd_cmpgeu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_h_si, "cv_simd_cmpgeu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpgeu_sc_b_si, "cv_simd_cmpgeu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_h_si, "cv_simd_cmpltu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_b_si, "cv_simd_cmpltu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_h_si, "cv_simd_cmpltu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpltu_sc_b_si, "cv_simd_cmpltu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_h_si, "cv_simd_cmpleu_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_b_si, "cv_simd_cmpleu_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_h_si, "cv_simd_cmpleu_sc_h", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UHI, cvsimd), +RISCV_BUILTIN (cv_simd_cmpleu_sc_b_si, "cv_simd_cmpleu_sc_b", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_UQI, cvsimd), +//COMPLEX NUMBER +RISCV_BUILTIN (cv_simd_cplxmul_r_si, "cv_simd_cplxmul_r", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxmul_i_si, "cv_simd_cplxmul_i", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvsimd), +RISCV_BUILTIN (cv_simd_cplxconj_si, "cv_simd_cplxconj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, cvsimd), +RISCV_BUILTIN (cv_simd_subrotmj_si, "cv_simd_subrotmj", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvsimd), diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index adad2409fb6..32a14d03936 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -27,6 +27,164 @@ ;;CORE-V EVENT LOAD UNSPECV_CV_ELW + + ;;CORE-V SIMD + ;;CORE-V SIMD ALU + UNSPEC_CV_ADD_H + UNSPEC_CV_ADD_B + UNSPEC_CV_ADD_SC_H + UNSPEC_CV_ADD_SC_B + UNSPEC_CV_SUB_H + UNSPEC_CV_SUB_B + UNSPEC_CV_SUB_SC_H + UNSPEC_CV_SUB_SC_B + UNSPEC_CV_AVG_H + UNSPEC_CV_AVG_B + UNSPEC_CV_AVG_SC_H + UNSPEC_CV_AVG_SC_B + UNSPEC_CV_AVGU_H + UNSPEC_CV_AVGU_B + UNSPEC_CV_AVGU_SC_H + UNSPEC_CV_AVGU_SC_B + UNSPEC_CV_MIN_H + UNSPEC_CV_MIN_B + UNSPEC_CV_MIN_SC_H + UNSPEC_CV_MIN_SC_B + UNSPEC_CV_MINU_H + UNSPEC_CV_MINU_B + UNSPEC_CV_MINU_SC_H + UNSPEC_CV_MINU_SC_B + UNSPEC_CV_MAX_H + UNSPEC_CV_MAX_B + UNSPEC_CV_MAX_SC_H + UNSPEC_CV_MAX_SC_B + UNSPEC_CV_MAXU_H + UNSPEC_CV_MAXU_B + UNSPEC_CV_MAXU_SC_H + UNSPEC_CV_MAXU_SC_B + UNSPEC_CV_SRL_H + UNSPEC_CV_SRL_B + UNSPEC_CV_SRL_SC_H + UNSPEC_CV_SRL_SC_B + UNSPEC_CV_SRA_H + UNSPEC_CV_SRA_B + UNSPEC_CV_SRA_SC_H + UNSPEC_CV_SRA_SC_B + UNSPEC_CV_SLL_H + UNSPEC_CV_SLL_B + UNSPEC_CV_SLL_SC_H + UNSPEC_CV_SLL_SC_B + UNSPEC_CV_OR_H + UNSPEC_CV_OR_B + UNSPEC_CV_OR_SC_H + UNSPEC_CV_OR_SC_B + UNSPEC_CV_XOR_H + UNSPEC_CV_XOR_B + UNSPEC_CV_XOR_SC_H + UNSPEC_CV_XOR_SC_B + UNSPEC_CV_AND_H + UNSPEC_CV_AND_B + UNSPEC_CV_AND_SC_H + UNSPEC_CV_AND_SC_B + UNSPEC_CV_ABS_H + UNSPEC_CV_ABS_B + UNSPEC_CV_NEG_H + UNSPEC_CV_NEG_B + + ;;CORE-V SIMD BIT MANIPULATION + UNSPEC_CV_EXTRACT_H + UNSPEC_CV_EXTRACT_B + UNSPEC_CV_EXTRACTU_H + UNSPEC_CV_EXTRACTU_B + UNSPEC_CV_INSERT_H + UNSPEC_CV_INSERT_B + + ;;CORE-V SIMD DOT PRODUCT + UNSPEC_CV_DOTUP_H + UNSPEC_CV_DOTUP_B + UNSPEC_CV_DOTUP_SC_H + UNSPEC_CV_DOTUP_SC_B + UNSPEC_CV_DOTUSP_H + UNSPEC_CV_DOTUSP_B + UNSPEC_CV_DOTUSP_SC_H + UNSPEC_CV_DOTUSP_SC_B + UNSPEC_CV_DOTSP_H + UNSPEC_CV_DOTSP_B + UNSPEC_CV_DOTSP_SC_H + UNSPEC_CV_DOTSP_SC_B + UNSPEC_CV_SDOTUP_H + UNSPEC_CV_SDOTUP_B + UNSPEC_CV_SDOTUP_SC_H + UNSPEC_CV_SDOTUP_SC_B + UNSPEC_CV_SDOTUSP_H + UNSPEC_CV_SDOTUSP_B + UNSPEC_CV_SDOTUSP_SC_H + UNSPEC_CV_SDOTUSP_SC_B + UNSPEC_CV_SDOTSP_H + UNSPEC_CV_SDOTSP_B + UNSPEC_CV_SDOTSP_SC_H + UNSPEC_CV_SDOTSP_SC_B + + ;;CORE-V SIMD SHUFFLE AND PACK + UNSPEC_CV_SHUFFLE_H + UNSPEC_CV_SHUFFLE_SCI_H + UNSPEC_CV_SHUFFLE_B + UNSPEC_CV_SHUFFLE_SCI_B + UNSPEC_CV_SHUFFLE2_H + UNSPEC_CV_SHUFFLE2_B + UNSPEC_CV_PACKHI_H + UNSPEC_CV_PACKLO_H + UNSPEC_CV_PACKHI_B + UNSPEC_CV_PACKLO_B + + ;;CORE-V SIMD COMPARISON + UNSPEC_CV_CMPEQ_H + UNSPEC_CV_CMPEQ_B + UNSPEC_CV_CMPEQ_SC_H + UNSPEC_CV_CMPEQ_SC_B + UNSPEC_CV_CMPNE_H + UNSPEC_CV_CMPNE_B + UNSPEC_CV_CMPNE_SC_H + UNSPEC_CV_CMPNE_SC_B + UNSPEC_CV_CMPGT_H + UNSPEC_CV_CMPGT_B + UNSPEC_CV_CMPGT_SC_H + UNSPEC_CV_CMPGT_SC_B + UNSPEC_CV_CMPGE_H + UNSPEC_CV_CMPGE_B + UNSPEC_CV_CMPGE_SC_H + UNSPEC_CV_CMPGE_SC_B + UNSPEC_CV_CMPLT_H + UNSPEC_CV_CMPLT_B + UNSPEC_CV_CMPLT_SC_H + UNSPEC_CV_CMPLT_SC_B + UNSPEC_CV_CMPLE_H + UNSPEC_CV_CMPLE_B + UNSPEC_CV_CMPLE_SC_H + UNSPEC_CV_CMPLE_SC_B + UNSPEC_CV_CMPGTU_H + UNSPEC_CV_CMPGTU_B + UNSPEC_CV_CMPGTU_SC_H + UNSPEC_CV_CMPGTU_SC_B + UNSPEC_CV_CMPGEU_H + UNSPEC_CV_CMPGEU_B + UNSPEC_CV_CMPGEU_SC_H + UNSPEC_CV_CMPGEU_SC_B + UNSPEC_CV_CMPLTU_H + UNSPEC_CV_CMPLTU_B + UNSPEC_CV_CMPLTU_SC_H + UNSPEC_CV_CMPLTU_SC_B + UNSPEC_CV_CMPLEU_H + UNSPEC_CV_CMPLEU_B + UNSPEC_CV_CMPLEU_SC_H + UNSPEC_CV_CMPLEU_SC_B + + ;;CORE-V SIMD COMPLEX + UNSPEC_CV_CPLXMUL_R + UNSPEC_CV_CPLXMUL_I + UNSPEC_CV_CPLXCONJ + UNSPEC_CV_SUBROTMJ + ]) ;; XCVMAC extension. @@ -706,3 +864,1753 @@ [(set_attr "type" "load") (set_attr "mode" "SI")]) + +;;CORE-V SIMD +;;CORE-V SIMD ALU +(define_insn "riscv_cv_simd_add_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_ADD_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.h\\t%0,%1,%2 + cv.add.div2\\t%0,%1,%2 + cv.add.div4\\t%0,%1,%2 + cv.add.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_ADD_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.add.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.h\\t%0,%1,%2 + cv.add.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_add_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_ADD_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.add.sci.b\\t%0,%1,%2 + cv.add.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUB_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.h\\t%0,%1,%2 + cv.sub.div2\\t%0,%1,%2 + cv.sub.div4\\t%0,%1,%2 + cv.sub.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SUB_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.h\\t%0,%1,%2 + cv.sub.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sub_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_SUB_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sub.sci.b\\t%0,%1,%2 + cv.sub.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avg.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.h\\t%0,%1,%2 + cv.avg.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avg_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AVG_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avg.sci.b\\t%0,%1,%2 + cv.avg.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AVGU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.avgu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.h\\t%0,%1,%2 + cv.avgu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_avgu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_AVGU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.avgu.sci.b\\t%0,%1,%2 + cv.avgu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MIN_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.min.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.h\\t%0,%1,%2 + cv.min.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_min_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MIN_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.min.sci.b\\t%0,%1,%2 + cv.min.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MINU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.minu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.h\\t%0,%1,%2 + cv.minu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_minu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MINU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.minu.sci.b\\t%0,%1,%2 + cv.minu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAX_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.max.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.h\\t%0,%1,%2 + cv.max.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_max_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_MAX_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.max.sci.b\\t%0,%1,%2 + cv.max.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_MAXU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.maxu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.h\\t%0,%1,%2 + cv.maxu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_maxu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_MAXU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.maxu.sci.b\\t%0,%1,%2 + cv.maxu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.srl.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.h\\t%0,%1,%2 + cv.srl.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_srl_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.srl.sci.b\\t%0,%1,%2 + cv.srl.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SRA_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sra.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.h\\t%0,%1,%2 + cv.sra.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sra_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SRA_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sra.sci.b\\t%0,%1,%2 + cv.sra.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SLL_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sll.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.h\\t%0,%1,%2 + cv.sll.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sll_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_SLL_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sll.sci.b\\t%0,%1,%2 + cv.sll.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_OR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.or.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.h\\t%0,%1,%2 + cv.or.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_or_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_OR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.or.sci.b\\t%0,%1,%2 + cv.or.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_XOR_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.xor.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.h\\t%0,%1,%2 + cv.xor.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_xor_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_XOR_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.xor.sci.b\\t%0,%1,%2 + cv.xor.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_AND_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.and.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.h\\t%0,%1,%2 + cv.and.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_and_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_AND_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.and.sci.b\\t%0,%1,%2 + cv.and.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.h\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_abs_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.abs.b\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.h\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_neg_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sub.b\\t%0,zero,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD BIT MANIPULATION +(define_insn "riscv_cv_simd_extract_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extract_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extract.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_extractu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_EXTRACTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.extractu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.h\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_insert_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "0") + (match_operand:QI 3 "immediate_operand" "CV_simd_si6")] + UNSPEC_CV_INSERT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.insert.b\\t%0,%1,%3" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD DOT PRODUCT +(define_insn "riscv_cv_simd_dotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.h\\t%0,%1,%2 + cv.dotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_DOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotup.sci.b\\t%0,%1,%2 + cv.dotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.h\\t%0,%1,%2 + cv.dotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotusp.sci.b\\t%0,%1,%2 + cv.dotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_DOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.dotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.h\\t%0,%1,%2 + cv.dotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_dotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_DOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.dotsp.sci.b\\t%0,%1,%2 + cv.dotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotup.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.h\\t%0,%1,%2 + cv.sdotup.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotup_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotup.sci.b\\t%0,%1,%2 + cv.sdotup.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTUSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotusp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.h\\t%0,%1,%2 + cv.sdotusp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotusp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTUSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotusp.sci.b\\t%0,%1,%2 + cv.sdotusp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SDOTSP_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.sdotsp.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.h\\t%0,%1,%2 + cv.sdotsp.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_sdotsp_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r") + (match_operand:SI 3 "register_operand" "0,0")] + UNSPEC_CV_SDOTSP_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.sdotsp.sci.b\\t%0,%1,%2 + cv.sdotsp.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD SHUFFLE AND PACK +(define_insn "riscv_cv_simd_shuffle_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "const_int6_operand" "CV_simd_un6")] + UNSPEC_CV_SHUFFLE_SCI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.sci.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_SHUFFLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle_sci_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:QI 2 "const_int_operand" "CV_simd_un6,CV_simd_i01,CV_simd_i02,CV_simd_i03")] + UNSPEC_CV_SHUFFLE_SCI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.shufflei0.sci.b\\t%0,%1,%Y2 + cv.shufflei1.sci.b\\t%0,%1,%Y2 + cv.shufflei2.sci.b\\t%0,%1,%Y2 + cv.shufflei3.sci.b\\t%0,%1,%Y2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_shuffle2_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_SHUFFLE2_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.shuffle2.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKHI_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_PACKLO_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.pack\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packhi_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKHI_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packhi.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_packlo_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPEC_CV_PACKLO_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.packlo.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPARISON +(define_insn "riscv_cv_simd_cmpeq_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPEQ_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpeq.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.h\\t%0,%1,%2 + cv.cmpeq.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpeq_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPEQ_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpeq.sci.b\\t%0,%1,%2 + cv.cmpeq.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPNE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpne.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.h\\t%0,%1,%2 + cv.cmpne.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpne_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPNE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpne.sci.b\\t%0,%1,%2 + cv.cmpne.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.h\\t%0,%1,%2 + cv.cmpgt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgt.sci.b\\t%0,%1,%2 + cv.cmpgt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpge.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.h\\t%0,%1,%2 + cv.cmpge.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpge_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPGE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpge.sci.b\\t%0,%1,%2 + cv.cmpge.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLT_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmplt.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.h\\t%0,%1,%2 + cv.cmplt.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmplt_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLT_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmplt.sci.b\\t%0,%1,%2 + cv.cmplt.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLE_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmple.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.h\\t%0,%1,%2 + cv.cmple.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmple_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")] + UNSPEC_CV_CMPLE_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmple.sci.b\\t%0,%1,%2 + cv.cmple.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgtu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.h\\t%0,%1,%2 + cv.cmpgtu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgtu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgtu.sci.b\\t%0,%1,%2 + cv.cmpgtu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPGEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpgeu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.h\\t%0,%1,%2 + cv.cmpgeu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpgeu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPGEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpgeu.sci.b\\t%0,%1,%2 + cv.cmpgeu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLTU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpltu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.h\\t%0,%1,%2 + cv.cmpltu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpltu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLTU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpltu.sci.b\\t%0,%1,%2 + cv.cmpltu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_h_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_b_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_CV_CMPLEU_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cmpleu.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_h_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_H))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.h\\t%0,%1,%2 + cv.cmpleu.sc.h\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cmpleu_sc_b_si" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")] + UNSPEC_CV_CMPLEU_SC_B))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cmpleu.sci.b\\t%0,%1,%2 + cv.cmpleu.sc.b\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +;;CORE-V SIMD COMPLEX +(define_insn "riscv_cv_simd_cplxmul_r_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_R))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.r\\t%0,%1,%2 + cv.cplxmul.r.div2\\t%0,%1,%2 + cv.cplxmul.r.div4\\t%0,%1,%2 + cv.cplxmul.r.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxmul_i_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:SI 3 "register_operand" "0,0,0,0") + (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_CPLXMUL_I))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.cplxmul.i\\t%0,%1,%2 + cv.cplxmul.i.div2\\t%0,%1,%2 + cv.cplxmul.i.div4\\t%0,%1,%2 + cv.cplxmul.i.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_cplxconj_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CV_CPLXCONJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "cv.cplxconj\\t%0,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) + + +(define_insn "riscv_cv_simd_subrotmj_si" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r") + (match_operand:SI 2 "register_operand" "r,r,r,r") + (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")] + UNSPEC_CV_SUBROTMJ))] + "TARGET_XCVSIMD && !TARGET_64BIT" + "@ + cv.subrotmj\\t%0,%1,%2 + cv.subrotmj.div2\\t%0,%1,%2 + cv.subrotmj.div4\\t%0,%1,%2 + cv.subrotmj.div8\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b1a79cae50a..c7f5291ca21 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -425,6 +425,26 @@ (ior (match_operand 0 "register_operand") (match_code "const_int"))) +(define_predicate "const_int6s_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -32, 31)"))) + +(define_predicate "int6s_operand" + (ior (match_operand 0 "const_int6s_operand") + (match_operand 0 "register_operand"))) + +(define_predicate "const_int2_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + +(define_predicate "const_int6_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) + +(define_predicate "int6_operand" + (ior (match_operand 0 "const_int6_operand") + (match_operand 0 "register_operand"))) + ;; Predicates for the V extension. (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 1932ff069c6..d457e306dd1 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -135,6 +135,7 @@ AVAIL (hint_pause, (!0)) AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT) AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT) AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT) +AVAIL (cvsimd, TARGET_XCVSIMD && !TARGET_64BIT) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 5f051df2277..baea490f91c 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -38,6 +38,9 @@ DEF_RISCV_FTYPE (1, (USI, UHI)) DEF_RISCV_FTYPE (1, (SI, QI)) DEF_RISCV_FTYPE (1, (SI, HI)) DEF_RISCV_FTYPE (2, (USI, UQI, UQI)) +DEF_RISCV_FTYPE (2, (USI, USI, UHI)) +DEF_RISCV_FTYPE (2, (USI, USI, QI)) +DEF_RISCV_FTYPE (2, (USI, USI, HI)) DEF_RISCV_FTYPE (2, (USI, UHI, UHI)) DEF_RISCV_FTYPE (2, (USI, USI, USI)) DEF_RISCV_FTYPE (2, (USI, USI, UQI)) @@ -50,6 +53,11 @@ DEF_RISCV_FTYPE (2, (UDI, UDI, UDI)) DEF_RISCV_FTYPE (2, (SI, USI, USI)) DEF_RISCV_FTYPE (2, (SI, SI, SI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI)) +DEF_RISCV_FTYPE (3, (USI, USI, USI, QI)) +DEF_RISCV_FTYPE (3, (USI, USI, UQI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, QI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, UHI, USI)) +DEF_RISCV_FTYPE (3, (USI, USI, HI, USI)) DEF_RISCV_FTYPE (3, (USI, USI, USI, USI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI)) DEF_RISCV_FTYPE (3, (SI, SI, SI, SI)) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 41626fa34e4..21e8385874d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5842,6 +5842,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) output_addr_const (file, newop); break; } + case 'Y': + { + unsigned int imm = (UINTVAL (op) & 63); + gcc_assert (imm <= 63); + rtx newop = GEN_INT (imm); + output_addr_const (file, newop); + break; + } default: switch (code) { diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 44ed6d69da2..f92cfb9a69a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -425,6 +425,8 @@ Mask(XCVALU) Var(riscv_xcv_subext) Mask(XCVELW) Var(riscv_xcv_subext) +Mask(XCVSIMD) Var(riscv_xcv_subext) + TargetVariable int riscv_xthead_subext diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b9129d1b464..51841e49ca0 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -24228,6 +24228,8 @@ All of these functions are declared in the include file @file{riscv_vector.h}. @node CORE-V Built-in Functions @subsection CORE-V Built-in Functions +For more information on all CORE-V built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md} These built-in functions are available for the CORE-V MAC machine architecture. For more information on CORE-V built-ins, please see @@ -24407,6 +24409,890 @@ architecture. For more information on CORE-V ELW builtins, please see Generated assembler @code{cv.elw} @end deftypefn +These built-in functions are available for the CORE-V SIMD machine +architecture. For more information on CORE-V SIMD built-ins, please see +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-816-bit-simd-builtins-xcvsimd} + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_b (uint32_t, uint32_t) +Generated assembler @code{cv.add.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.add.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.add.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.add.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_b (uint32_t, uint32_t) +Generated assembler @code{cv.sub.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sub.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sub.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sub.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_h (uint32_t, uint32_t) +Generated assembler @code{cv.avg.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_b (uint32_t, uint32_t) +Generated assembler @code{cv.avg.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.avg.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.avg.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avg_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.avg.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_h (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_b (uint32_t, uint32_t) +Generated assembler @code{cv.avgu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.avgu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.avgu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_avgu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.avgu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_h (uint32_t, uint32_t) +Generated assembler @code{cv.min.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_b (uint32_t, uint32_t) +Generated assembler @code{cv.min.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.min.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.min.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_min_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.min.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_h (uint32_t, uint32_t) +Generated assembler @code{cv.minu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_b (uint32_t, uint32_t) +Generated assembler @code{cv.minu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.minu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.minu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_minu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.minu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_h (uint32_t, uint32_t) +Generated assembler @code{cv.max.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_b (uint32_t, uint32_t) +Generated assembler @code{cv.max.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.max.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.max.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_max_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.max.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_h (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_b (uint32_t, uint32_t) +Generated assembler @code{cv.maxu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.maxu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.maxu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_maxu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.maxu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_h (uint32_t, uint32_t) +Generated assembler @code{cv.srl.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_b (uint32_t, uint32_t) +Generated assembler @code{cv.srl.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.srl.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.srl.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_srl_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.srl.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_h (uint32_t, uint32_t) +Generated assembler @code{cv.sra.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_b (uint32_t, uint32_t) +Generated assembler @code{cv.sra.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sra.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sra.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sra_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sra.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_h (uint32_t, uint32_t) +Generated assembler @code{cv.sll.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_b (uint32_t, uint32_t) +Generated assembler @code{cv.sll.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.sll.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.sll.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sll_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.sll.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_h (uint32_t, uint32_t) +Generated assembler @code{cv.or.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_b (uint32_t, uint32_t) +Generated assembler @code{cv.or.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.or.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.or.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_or_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.or.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_h (uint32_t, uint32_t) +Generated assembler @code{cv.xor.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_b (uint32_t, uint32_t) +Generated assembler @code{cv.xor.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.xor.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.xor.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_xor_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.xor.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_h (uint32_t, uint32_t) +Generated assembler @code{cv.and.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_b (uint32_t, uint32_t) +Generated assembler @code{cv.and.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.and.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.and.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_and_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.and.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_h (uint32_t) +Generated assembler @code{cv.abs.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_abs_b (uint32_t) +Generated assembler @code{cv.abs.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.dotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.dotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotup_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.dotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotusp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_h (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_b (uint32_t, uint32_t) +Generated assembler @code{cv.dotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.dotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.dotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_dotsp_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.dotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotup.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint16_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_h (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint8_t, uint32_t) +Generated assembler @code{cv.sdotup.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotup_sc_b (uint32_t, uint6_t, uint32_t) +Generated assembler @code{cv.sdotup.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotusp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotusp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotusp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotusp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.sdotsp.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int16_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_h (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int8_t, uint32_t) +Generated assembler @code{cv.sdotsp.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sdotsp_sc_b (uint32_t, int6_t, uint32_t) +Generated assembler @code{cv.sdotsp.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_h (uint32_t, uint6_t) +Generated assembler @code{cv.extract.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extract_b (uint32_t, uint6_t) +Generated assembler @code{cv.extract.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_h (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_extractu_b (uint32_t, uint6_t) +Generated assembler @code{cv.extractu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_h (uint32_t, uint32_t) +Generated assembler @code{cv.insert.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_insert_b (uint32_t, uint32_t) +Generated assembler @code{cv.insert.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_h (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_b (uint32_t, uint32_t) +Generated assembler @code{cv.shuffle.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle_sci_h (uint32_t, uint4_t) +Generated assembler @code{cv.shuffle.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei0_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei0.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei1_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei1.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei2_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei2.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shufflei3_sci_b (uint32_t, uint4_t) +Generated assembler @code{cv.shufflei3.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_h (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_shuffle2_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.shuffle2.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_h (uint32_t, uint32_t) +Generated assembler @code{cv.pack.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packhi_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packhi.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_packlo_b (uint32_t, uint32_t, uint32_t) +Generated assembler @code{cv.packlo.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpeq.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpeq.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpeq.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpeq_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpeq.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpne.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpne.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpne.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpne_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpne.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpgt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpgt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpgt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpge.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmpge.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmpge.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpge_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmpge.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmplt.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmplt.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmplt.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmplt_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmplt.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmple.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int16_t) +Generated assembler @code{cv.cmple.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_h (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int8_t) +Generated assembler @code{cv.cmple.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmple_sc_b (uint32_t, int6_t) +Generated assembler @code{cv.cmple.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgtu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgtu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgtu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgtu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgtu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpgeu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpgeu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpgeu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpgeu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpgeu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpltu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpltu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpltu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpltu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpltu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_h (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_b (uint32_t, uint32_t) +Generated assembler @code{cv.cmpleu.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint16_t) +Generated assembler @code{cv.cmpleu.sc.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_h (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.h} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint8_t) +Generated assembler @code{cv.cmpleu.sc.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cmpleu_sc_b (uint32_t, uint6_t) +Generated assembler @code{cv.cmpleu.sci.b} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_r (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.r.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxmul_i (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.cplxmul.i.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_cplxconj (uint32_t) +Generated assembler @code{cv.cplxconj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_subrotmj (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.subrotmj.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_add_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.add.div8} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div2} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div4} +@end deftypefn + +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_simd_sub_h (uint32_t, uint32_t, uint32_t, uint4_t) +Generated assembler @code{cv.sub.div8} +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 8082100a3c9..798dabee6bb 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2505,6 +2505,9 @@ Test system has support for the CORE-V ALU extension. @item cv_elw Test system has support for the CORE-V ELW extension. +@item cv_simd +Test system has support for the CORE-V SIMD extension. + @end table @subsubsection Other hardware attributes diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c new file mode 100644 index 00000000000..c8d58724786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c new file mode 100644 index 00000000000..9ebb9053e35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-abs-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c new file mode 100644 index 00000000000..b362e904407 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c new file mode 100644 index 00000000000..8e885a1062b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c new file mode 100644 index 00000000000..3edea7bb990 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c new file mode 100644 index 00000000000..df43c202b9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c new file mode 100644 index 00000000000..27b2cc38f4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c new file mode 100644 index 00000000000..43f37a88cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c new file mode 100644 index 00000000000..99cd7b40731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-add-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c new file mode 100644 index 00000000000..6be001d4c11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c new file mode 100644 index 00000000000..770c3e59e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c new file mode 100644 index 00000000000..616a9235a67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c new file mode 100644 index 00000000000..73ceba6cbed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-and-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c new file mode 100644 index 00000000000..21ae43aeb5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c new file mode 100644 index 00000000000..f2582d4e3ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c new file mode 100644 index 00000000000..a72a9effcd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c new file mode 100644 index 00000000000..41cd20f2536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avg-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c new file mode 100644 index 00000000000..a17a9233120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c new file mode 100644 index 00000000000..8f7c62c8b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c new file mode 100644 index 00000000000..7e00a5b2b7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c new file mode 100644 index 00000000000..f024d0e5d7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-avgu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c new file mode 100644 index 00000000000..7ac9cb2704a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c new file mode 100644 index 00000000000..8fc1eb03417 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c new file mode 100644 index 00000000000..5a0adcd68a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c new file mode 100644 index 00000000000..c1aeb7e6874 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpeq-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c new file mode 100644 index 00000000000..74c5a17588c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c new file mode 100644 index 00000000000..32b509ecd53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c new file mode 100644 index 00000000000..4e4bbeeee04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c new file mode 100644 index 00000000000..4443f65f7c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpge-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c new file mode 100644 index 00000000000..0207c3210e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c new file mode 100644 index 00000000000..b8da488a814 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c new file mode 100644 index 00000000000..e8e2e62e9cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c new file mode 100644 index 00000000000..b669ea19ca0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgeu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c new file mode 100644 index 00000000000..fb5f4317cd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c new file mode 100644 index 00000000000..5d5a5a96be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c new file mode 100644 index 00000000000..ab32a39091c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c new file mode 100644 index 00000000000..6f55da30358 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c new file mode 100644 index 00000000000..760cd48d991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c new file mode 100644 index 00000000000..9453079ee5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c new file mode 100644 index 00000000000..8f339103572 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c new file mode 100644 index 00000000000..3f2d2a9ccfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpgtu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c new file mode 100644 index 00000000000..b19e437ddc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c new file mode 100644 index 00000000000..adb26c1c66b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c new file mode 100644 index 00000000000..d14ca9a7837 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c new file mode 100644 index 00000000000..22c2218a911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmple-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c new file mode 100644 index 00000000000..1d7f671eb42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c new file mode 100644 index 00000000000..18bee44f90d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c new file mode 100644 index 00000000000..a1adf919610 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c new file mode 100644 index 00000000000..f3823ff950b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpleu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c new file mode 100644 index 00000000000..ee3a5b2ac3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c new file mode 100644 index 00000000000..7ae45ff94dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c new file mode 100644 index 00000000000..ce6f280ae4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c new file mode 100644 index 00000000000..acd0c2c13aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmplt-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c new file mode 100644 index 00000000000..e3260f986ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c new file mode 100644 index 00000000000..37f1f8b81f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c new file mode 100644 index 00000000000..34e4e980868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c new file mode 100644 index 00000000000..973b11e663a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpltu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c new file mode 100644 index 00000000000..532aabbd683 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c new file mode 100644 index 00000000000..cfa0abcd545 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c new file mode 100644 index 00000000000..9554172ab2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c new file mode 100644 index 00000000000..f2d9e659b89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cmpne-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c new file mode 100644 index 00000000000..194a70480f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxconj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c new file mode 100644 index 00000000000..dab59c6e95b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c new file mode 100644 index 00000000000..27da60ac96f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c new file mode 100644 index 00000000000..f9fd78e12be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c new file mode 100644 index 00000000000..0cacf8dc2ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-i-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c new file mode 100644 index 00000000000..60c378a5c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c new file mode 100644 index 00000000000..a2bb0dffe53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c new file mode 100644 index 00000000000..0f9d986f8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c new file mode 100644 index 00000000000..7c025c7aba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-cplxmul-r-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c new file mode 100644 index 00000000000..4b522da48dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c new file mode 100644 index 00000000000..12fa58be89b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..1ba74ff8ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..19684717e95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c new file mode 100644 index 00000000000..a65464e348d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c new file mode 100644 index 00000000000..42145083ad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c new file mode 100644 index 00000000000..51e9154ff60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c new file mode 100644 index 00000000000..28b423f5731 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c new file mode 100644 index 00000000000..b5281bd7230 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c new file mode 100644 index 00000000000..5545b5e6037 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..7db3f1c94f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..1af83c57070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-dotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c new file mode 100644 index 00000000000..10133fe4907 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c new file mode 100644 index 00000000000..a507e016496 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extract-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extract_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c new file mode 100644 index 00000000000..1ea67024cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 3); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c new file mode 100644 index 00000000000..499e5780381 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-extractu-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 1); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c new file mode 100644 index 00000000000..d7c9d4ed212 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-b-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 3); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c new file mode 100644 index 00000000000..e10389e6995 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-insert-h-compile-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 0); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 1); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h (a, b, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c new file mode 100644 index 00000000000..3fe01498356 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-march-compile-1.c @@ -0,0 +1,1765 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 0); +} + + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_b(a, b); +} + + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_h(a, 20); +} + + +int +foo5 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + + +int +foo6 (int a) +{ + return __builtin_riscv_cv_simd_add_sc_b(a, 20); +} + + +int +foo7 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + + +int +foo8 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + + +int +foo9 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + + +int +foo10 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 20); +} + + +int +foo11 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + + +int +foo12 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 20); +} + + +int +foo13 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_h(a, b); +} + + +int +foo14 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_b(a, b); +} + + +int +foo15 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + + +int +foo16 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_h(a, 20); +} + + +int +foo17 (int a, int b) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + + +int +foo18 (int a) +{ + return __builtin_riscv_cv_simd_avg_sc_b(a, 20); +} + + +int +foo19 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + + +int +foo20 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + + +int +foo21 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + + +int +foo22 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_h(a, 20); +} + + +int +foo23 (int a, int b) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + + +int +foo24 (int a) +{ + return __builtin_riscv_cv_simd_avgu_sc_b(a, 20); +} + + +int +foo25 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + + +int +foo26 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + + +int +foo27 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + + +int +foo28 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 20); +} + + +int +foo29 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + + +int +foo30 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 20); +} + + +int +foo31 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + + +int +foo32 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + + +int +foo33 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + + +int +foo34 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 20); +} + + +int +foo35 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + + +int +foo36 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 20); +} + + +int +foo37 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + + +int +foo38 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + + +int +foo39 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + + +int +foo40 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 20); +} + + +int +foo41 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + + +int +foo42 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 20); +} + + +int +foo43 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + + +int +foo44 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + + +int +foo45 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + + +int +foo46 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 20); +} + + +int +foo47 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + + +int +foo48 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 20); +} + + +int +foo49 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + + +int +foo50 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + + +int +foo51 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, b); +} + + +int +foo52 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h(a, 20); +} + + +int +foo53 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, b); +} + + +int +foo54 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b(a, 20); +} + + +int +foo55 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + + +int +foo56 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + + +int +foo57 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, b); +} + + +int +foo58 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h(a, 20); +} + + +int +foo59 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, b); +} + + +int +foo60 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b(a, 20); +} + + +int +foo61 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + + +int +foo62 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + + +int +foo63 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, b); +} + + +int +foo64 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h(a, 20); +} + + +int +foo65 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, b); +} + + +int +foo66 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b(a, 20); +} + + +int +foo67 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + + +int +foo68 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + + +int +foo69 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + + +int +foo70 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 20); +} + + +int +foo71 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + + +int +foo72 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 20); +} + + +int +foo73 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + + +int +foo74 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + + +int +foo75 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + + +int +foo76 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 20); +} + + +int +foo77 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + + +int +foo78 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 20); +} + + +int +foo79 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_h(a, b); +} + + +int +foo80 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_b(a, b); +} + + +int +foo81 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + + +int +foo82 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_h(a, 20); +} + + +int +foo83 (int a, int b) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + + +int +foo84 (int a) +{ + return __builtin_riscv_cv_simd_and_sc_b(a, 20); +} + + +int +foo85 (int a) +{ + return __builtin_riscv_cv_simd_abs_h(a); +} + + +int +foo86 (int a) +{ + return __builtin_riscv_cv_simd_abs_b(a); +} + + +int +foo87 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + + +int +foo88 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + + +int +foo89 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + + +int +foo90 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_h(a, 20); +} + + +int +foo91 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + + +int +foo92 (int a) +{ + return __builtin_riscv_cv_simd_dotup_sc_b(a, 20); +} + + +int +foo93 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + + +int +foo94 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + + +int +foo95 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + + +int +foo96 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_h(a, 20); +} + + +int +foo97 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + + +int +foo98 (int a) +{ + return __builtin_riscv_cv_simd_dotusp_sc_b(a, 20); +} + + +int +foo99 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + + +int +foo100 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + + +int +foo101 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + + +int +foo102 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_h(a, 20); +} + + +int +foo103 (int a, int b) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + + +int +foo104 (int a) +{ + return __builtin_riscv_cv_simd_dotsp_sc_b(a, 20); +} + + +int +foo105 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + + +int +foo106 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + + +int +foo107 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + + +int +foo108 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 20, b); +} + + +int +foo109 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + + +int +foo110 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 20, b); +} + + +int +foo111 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + + +int +foo112 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + + +int +foo113 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + + +int +foo114 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 20, b); +} + + +int +foo115 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + + +int +foo116 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 20, b); +} + + +int +foo117 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + + +int +foo118 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + + +int +foo119 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + + +int +foo120 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 20, b); +} + + +int +foo121 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + + +int +foo122 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 20, b); +} + + +int +foo123 (int a) +{ + return __builtin_riscv_cv_simd_extract_h(a, 20); +} + + +int +foo124 (int a) +{ + return __builtin_riscv_cv_simd_extract_b(a, 20); +} + + +int +foo125 (int a) +{ + return __builtin_riscv_cv_simd_extractu_h(a, 20); +} + + +int +foo126 (int a) +{ + return __builtin_riscv_cv_simd_extractu_b(a, 20); +} + + +int +foo127 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_h(a, b, 20); +} + + +int +foo128 (int a, int b) +{ + return __builtin_riscv_cv_simd_insert_b(a, b, 20); +} + + +int +foo129 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_h(a, b); +} + + +int +foo130 (int a, int b) +{ + return __builtin_riscv_cv_simd_shuffle_b(a, b); +} + + +int +foo131 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 20); +} + + +int +foo132 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 0); +} + + +int +foo133 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 64); +} + + +int +foo134 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 128); +} + + +int +foo135 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b(a, 192); +} + + +int +foo136 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + + +int +foo137 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + + +int +foo138 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + + +int +foo139 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + + +int +foo140 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + + +int +foo141 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + + +int +foo142 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + + +int +foo143 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + + +int +foo144 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + + +int +foo145 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, 20); +} + + +int +foo146 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + + +int +foo147 (int a) +{ + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, 20); +} + + +int +foo148 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + + +int +foo149 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + + +int +foo150 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + + +int +foo151 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_h(a, 20); +} + + +int +foo152 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + + +int +foo153 (int a) +{ + return __builtin_riscv_cv_simd_cmpne_sc_b(a, 20); +} + + +int +foo154 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + + +int +foo155 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + + +int +foo156 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + + +int +foo157 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, 20); +} + + +int +foo158 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + + +int +foo159 (int a) +{ + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, 20); +} + + +int +foo160 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + + +int +foo161 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + + +int +foo162 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + + +int +foo163 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_h(a, 20); +} + + +int +foo164 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + + +int +foo165 (int a) +{ + return __builtin_riscv_cv_simd_cmpge_sc_b(a, 20); +} + + +int +foo166 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + + +int +foo167 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + + +int +foo168 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + + +int +foo169 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_h(a, 20); +} + + +int +foo170 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + + +int +foo171 (int a) +{ + return __builtin_riscv_cv_simd_cmplt_sc_b(a, 20); +} + + +int +foo172 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + + +int +foo173 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + + +int +foo174 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + + +int +foo175 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_h(a, 20); +} + + +int +foo176 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + + +int +foo177 (int a) +{ + return __builtin_riscv_cv_simd_cmple_sc_b(a, 20); +} + + +int +foo178 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + + +int +foo179 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + + +int +foo180 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + + +int +foo181 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, 20); +} + + +int +foo182 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + + +int +foo183 (int a) +{ + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, 20); +} + + +int +foo184 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + + +int +foo185 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + + +int +foo186 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + + +int +foo187 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, 20); +} + + +int +foo188 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + + +int +foo189 (int a) +{ + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, 20); +} + + +int +foo190 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + + +int +foo191 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + + +int +foo192 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + + +int +foo193 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, 20); +} + + +int +foo194 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + + +int +foo195 (int a) +{ + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, 20); +} + + +int +foo196 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + + +int +foo197 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + + +int +foo198 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + + +int +foo199 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, 20); +} + + +int +foo200 (int a, int b) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + + +int +foo201 (int a) +{ + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, 20); +} + + +int +foo202 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + + +int +foo203 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + + +int +foo204 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 1); +} + + +int +foo205 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 1); +} + + +int +foo206 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 2); +} + + +int +foo207 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 2); +} + + +int +foo208 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 3); +} + + +int +foo209 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 3); +} + + +int +foo210 (int a) +{ + return __builtin_riscv_cv_simd_cplxconj(a); +} + + +int +foo211 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + + +int +foo212 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + + +int +foo213 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + + +int +foo214 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + + +int +foo215 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 1); +} + + +int +foo216 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 2); +} + + +int +foo217 (int a, int b) +{ + return __builtin_riscv_cv_simd_add_h(a, b, 3); +} + + +int +foo218 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + + +int +foo219 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + + +int +foo220 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + + +/* { dg-final { scan-assembler-times "cv\\.add\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avg\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.avgu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.and\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.abs\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.dotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extract\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.extractu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.insert\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpeq\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpne\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpge\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmplt\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmple\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgtu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpgeu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpltu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cmpleu\\.sci\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.r\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxmul\\.i\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.cplxconj" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 4 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.add\\.div8" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c new file mode 100644 index 00000000000..05c5b078129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c new file mode 100644 index 00000000000..a24308b38bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c new file mode 100644 index 00000000000..a82ceba459a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c new file mode 100644 index 00000000000..baa52d52f62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-max-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_max_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.max\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.max\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c new file mode 100644 index 00000000000..e6a96958f02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c new file mode 100644 index 00000000000..ee95b139c58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c new file mode 100644 index 00000000000..48a3c6f7922 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c new file mode 100644 index 00000000000..0a776774596 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-maxu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_maxu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.maxu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c new file mode 100644 index 00000000000..474d96ddf4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c new file mode 100644 index 00000000000..493bbdcd92d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c new file mode 100644 index 00000000000..30ede85c2e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c new file mode 100644 index 00000000000..a99b012c425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-min-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_min_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.min\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.min\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c new file mode 100644 index 00000000000..43582b28f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c new file mode 100644 index 00000000000..e44113bbae4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c new file mode 100644 index 00000000000..eec0a56f959 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_b(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c new file mode 100644 index 00000000000..6fc29abc3fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-minu-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_minu_sc_h(a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.minu\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.minu\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c new file mode 100644 index 00000000000..3f8bb7ceced --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_b(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c new file mode 100644 index 00000000000..2b6ecb0fb18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-neg-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_neg_h(a); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c new file mode 100644 index 00000000000..d6bd54f97e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c new file mode 100644 index 00000000000..cff54f344f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c new file mode 100644 index 00000000000..cd8b2dcb0dc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c new file mode 100644 index 00000000000..95352fe9b16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-or-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_or_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.or\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.or\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c new file mode 100644 index 00000000000..286d36640aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c new file mode 100644 index 00000000000..2d7f1b0bcf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-pack-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.pack\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c new file mode 100644 index 00000000000..deb25d022a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packhi-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packhi\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c new file mode 100644 index 00000000000..23489301e30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-packlo-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.packlo\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c new file mode 100644 index 00000000000..14e5baa27f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c new file mode 100644 index 00000000000..e0d7f587816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c new file mode 100644 index 00000000000..2f314142e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c new file mode 100644 index 00000000000..03481e24c9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotsp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotsp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c new file mode 100644 index 00000000000..63017c87c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c new file mode 100644 index 00000000000..70f12643c7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c new file mode 100644 index 00000000000..812faab72c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_b(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c new file mode 100644 index 00000000000..546a13b2812 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotup-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 0, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotup_sc_h(a, 63, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotup\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c new file mode 100644 index 00000000000..f0b522160f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c new file mode 100644 index 00000000000..8078c96702b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c new file mode 100644 index 00000000000..d1ce8fe62de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c new file mode 100644 index 00000000000..55410209450 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sdotusp-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + +int +foo2 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, -32, b); +} + +int +foo3 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 0, b); +} + +int +foo4 (int a, int b) +{ + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, 31, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sdotusp\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c new file mode 100644 index 00000000000..08c7a819b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle-sci-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_h(a, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle\\.sci\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c new file mode 100644 index 00000000000..7475a844ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_b(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c new file mode 100644 index 00000000000..fe4fcc613d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shuffle2-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b, int c) +{ + return __builtin_riscv_cv_simd_shuffle2_h(a, b, c); +} + +/* { dg-final { scan-assembler-times "cv\\.shuffle2\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c new file mode 100644 index 00000000000..024e4e23af2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei0-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 0); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei0\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c new file mode 100644 index 00000000000..7b971c1dcf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei1-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 64); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 127); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei1\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c new file mode 100644 index 00000000000..63995981141 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei2-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +unsigned int +foo1 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 128); +} + +unsigned int +foo2 (unsigned int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 191); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei2\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c new file mode 100644 index 00000000000..6f02cb5dd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-shufflei3-sci-b-compile-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 192); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_shuffle_sci_b (a, 255); +} + +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b" 2 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],0" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.shufflei3\\.sci\\.b\t\[a-z\]\[0-99\],\[a-z\]\[0-99\],63" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c new file mode 100644 index 00000000000..1392e7bfb1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c new file mode 100644 index 00000000000..84eba7515e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c new file mode 100644 index 00000000000..fa56156185a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c new file mode 100644 index 00000000000..12a1ffd3c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sll-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sll_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sll\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sll\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c new file mode 100644 index 00000000000..c5693023c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c new file mode 100644 index 00000000000..033aabb633f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c new file mode 100644 index 00000000000..133d9199374 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c new file mode 100644 index 00000000000..2830f44c3f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sra-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sra_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.sra\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sra\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c new file mode 100644 index 00000000000..ae848b1860e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c new file mode 100644 index 00000000000..797524ee783 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c new file mode 100644 index 00000000000..e62f8fa561c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-b-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_b (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.b" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c new file mode 100644 index 00000000000..6f7592a83b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-srl-sc-h-compile-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 0); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_srl_sc_h (a, 63); +} + +/* { dg-final { scan-assembler-times "cv\\.srl\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.srl\\.sci\\.h" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c new file mode 100644 index 00000000000..45120bcafda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c new file mode 100644 index 00000000000..e79a001508c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c new file mode 100644 index 00000000000..d8630f7ac63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c new file mode 100644 index 00000000000..efad60017b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c new file mode 100644 index 00000000000..a80e441f488 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_h(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c new file mode 100644 index 00000000000..30ce64689bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c new file mode 100644 index 00000000000..ac6d27d0eda --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-sub-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_sub_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.sub\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.sub\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c new file mode 100644 index 00000000000..8ecac97a9e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 0); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c new file mode 100644 index 00000000000..c77395d31c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div2-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 1); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div2" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c new file mode 100644 index 00000000000..e53c6d1bbab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div4-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 2); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c new file mode 100644 index 00000000000..ebd431efda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-subrotmj-div8-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_subrotmj(a, b, 3); +} + +/* { dg-final { scan-assembler-times "cv\\.subrotmj\\.div8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c new file mode 100644 index 00000000000..56ba1cd4d62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-b-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_b(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.b" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c new file mode 100644 index 00000000000..d07bceabe52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-h-compile-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_h(a, b); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.h" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c new file mode 100644 index 00000000000..7fe0f79d8a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-b-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_b(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.b" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.b" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c new file mode 100644 index 00000000000..5227a2bf862 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cv-simd-xor-sc-h-compile-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target cv_simd } */ +/* { dg-options "-march=rv32i_xcvsimd -mabi=ilp32" } */ + +int +foo1 (int a, int b) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + +int +foo2 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, -32); +} + +int +foo3 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 0); +} + +int +foo4 (int a) +{ + return __builtin_riscv_cv_simd_xor_sc_h(a, 31); +} + +/* { dg-final { scan-assembler-times "cv\\.xor\\.sc\\.h" 1 } } */ +/* { dg-final { scan-assembler-times "cv\\.xor\\.sci\\.h" 3 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fac32fb3d0e..6829978e330 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -13345,6 +13345,19 @@ proc check_effective_target_cv_elw { } { } "-march=rv32i_xcvelw" ] } +# Return 1 if the CORE-V SIMD extension is available. +proc check_effective_target_cv_simd { } { + if { !([istarget riscv*-*-*]) } { + return 0 + } + return [check_no_compiler_messages cv_simd object { + void foo (void) + { + asm ("cv.add.sc.b x0, x0, x0"); + } + } "-march=rv32i_xcvsimd" ] +} + proc check_effective_target_loongarch_sx { } { return [check_no_compiler_messages loongarch_lsx assembly { #if !defined(__loongarch_sx) -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/2] RISC-V: Fix XCValu test 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett @ 2024-01-16 17:13 ` Mary Bennett 2024-01-21 23:25 ` Jeff Law 2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng 2 siblings, 1 reply; 12+ messages in thread From: Mary Bennett @ 2024-01-16 17:13 UTC (permalink / raw) To: gcc-patches; +Cc: mary.bennett gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-alu-fail-compile.c: Change warning to error. --- .../gcc.target/riscv/cv-alu-fail-compile.c | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c index bbdb2d58c3f..89c7f6f2f5a 100644 --- a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c +++ b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c @@ -7,26 +7,26 @@ extern int d; int foo(int a, int b, int c) { - d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_sletu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_addN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_extbs (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_extbz (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_exths (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_exthz (a); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_min (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_max (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ - d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-warning "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_sletu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_addN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_extbs (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_extbz (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_exths (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_exthz (a); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_min (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_max (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-error "implicit declaration of function" } */ + d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-error "implicit declaration of function" } */ return d; } -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] RISC-V: Fix XCValu test 2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett @ 2024-01-21 23:25 ` Jeff Law 0 siblings, 0 replies; 12+ messages in thread From: Jeff Law @ 2024-01-21 23:25 UTC (permalink / raw) To: Mary Bennett, gcc-patches On 1/16/24 10:13, Mary Bennett wrote: > gcc/testsuite/ChangeLog: > * gcc.target/riscv/cv-alu-fail-compile.c: Change warning to error. AFAICT this is independent of the other patches and fixes a clear testsuite issue. I've pushed it to the trunk. Thanks, Jeff ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett @ 2024-01-25 13:53 ` Kito Cheng 2024-01-25 14:52 ` Kito Cheng 2 siblings, 1 reply; 12+ messages in thread From: Kito Cheng @ 2024-01-25 13:53 UTC (permalink / raw) To: Mary Bennett; +Cc: gcc-patches It's stage 4, so I think it would be great to not disturb code base too much, and adding intrinsic without adding VLS modes should be better way to go, and here is not really something serious coding style issue, just few minor indentation issue, so I gonna run regression to make not break anything else and then commit to trunk :) ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension 2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng @ 2024-01-25 14:52 ` Kito Cheng 0 siblings, 0 replies; 12+ messages in thread From: Kito Cheng @ 2024-01-25 14:52 UTC (permalink / raw) To: Mary Bennett; +Cc: gcc-patches pushed :) On Thu, Jan 25, 2024 at 9:53 PM Kito Cheng <kito.cheng@gmail.com> wrote: > > It's stage 4, so I think it would be great to not disturb code base > too much, and adding intrinsic without adding VLS modes should be > better way to go, and here is not really something serious coding > style issue, just few minor indentation issue, so I gonna run > regression to make not break anything else and then commit to trunk :) ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-01-25 14:52 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-11-09 11:57 [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2023-11-09 11:57 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2023-12-05 16:12 ` Kito Cheng 2024-01-16 16:35 ` [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 16:35 ` [PATCH v2 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2024-01-16 16:35 ` [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett 2024-01-16 17:13 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett 2024-01-16 17:13 ` [PATCH v3 1/2] RISC-V: Add support for XCVsimd extension in CV32E40P Mary Bennett 2024-01-16 17:13 ` [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett 2024-01-21 23:25 ` Jeff Law 2024-01-25 13:53 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Kito Cheng 2024-01-25 14:52 ` Kito Cheng
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