* [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions
@ 2023-11-08 11:09 Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
` (3 more replies)
0 siblings, 4 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-08 11:09 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/constraints.md | 21 +++++---
gcc/config/riscv/corev.def | 3 ++
gcc/config/riscv/corev.md | 33 ++++++++++++-
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.md | 9 +++-
gcc/config/riscv/riscv.opt | 4 ++
gcc/doc/extend.texi | 8 ++++
gcc/doc/sourcebuild.texi | 6 +++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++
gcc/testsuite/lib/target-supports.exp | 26 ++++++++++
17 files changed, 252 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
@ 2023-11-08 11:09 ` Mary Bennett
2023-11-09 17:11 ` Jeff Law
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
` (2 subsequent siblings)
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-08 11:09 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/corev.def | 3 +++
gcc/config/riscv/corev.md | 15 +++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 ++
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.opt | 2 ++
gcc/doc/extend.texi | 8 ++++++++
gcc/doc/sourcebuild.texi | 3 +++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
10 files changed, 60 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..6a1978bd0e4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+ {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT
RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..be66b1428a7 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
UNSPEC_CV_ALU_CLIPR
UNSPEC_CV_ALU_CLIPU
UNSPEC_CV_ALU_CLIPUR
+
+ ;;CORE-V EVENT LOAD
+ UNSPECV_CV_ELW
])
;; XCVMAC extension.
@@ -691,3 +694,15 @@
cv.suburnr\t%0,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
// CORE-V AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
+#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..3e7d5c69503 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
+DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UQI))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..0eac6d44fae 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
Mask(XCVALU) Var(riscv_xcv_subext)
+Mask(XCVELW) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c8fc4e391b5..b890acccac1 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21970,6 +21970,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in
Generated assembler @code{cv.subuRNr} if the it is a register.
@end deftypefn
+These built-in functions are available for the CORE-V Event Load machine
+architecture. For more information on CORE-V ELW builtins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
+
+@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *)
+Generated assembler @code{cv.elw}
+@end deftypefn
+
@node RX Built-in Functions
@subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c20af31c642..06a6d1776ff 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
@item cv_alu
Test system has support for the CORE-V ALU extension.
+@item cv_elw
+Test system has support for the CORE-V ELW extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
new file mode 100644
index 00000000000..bafb9f29e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_elw } */
+/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
+
+int
+foo (void* b)
+{
+ return __builtin_riscv_cv_elw_elw (b + 8);
+}
+
+/* { dg-final { scan-assembler-times "cv\\.elw" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 024939ee2e7..f388360ae56 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13085,6 +13085,19 @@ proc check_effective_target_cv_alu { } {
} "-march=rv32i_xcvalu" ]
}
+# Return 1 if the CORE-V ELW extension is available.
+proc check_effective_target_cv_elw { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_elw object {
+ void foo (void)
+ {
+ asm ("cv.elw x0, 0(x0)");
+ }
+ } "-march=rv32i_xcvelw" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-08 11:09 ` Mary Bennett
2023-11-10 1:08 ` Jeff Law
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-08 11:09 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
gcc/config/riscv/constraints.md | 15 ++++++++-------
gcc/config/riscv/corev.md | 4 ++--
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
(define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
"An integer register for ZFA or XTheadFmv.")
-;; CORE-V Constraints
-(define_constraint "CVP2"
- "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
- (and (match_code "const_int")
- (and (match_test "IN_RANGE (ival, 0, 1073741823)")
- (match_test "exact_log2 (ival + 1) != -1"))))
-
;; Vector constraints.
(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
(and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+ "@internal
+ Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+ (and (match_code "const_int")
+ (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+ (match_test "exact_log2 (ival + 1) != -1"))))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index be66b1428a7..0109e1836cf 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
(define_insn "riscv_cv_alu_clip"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIP))]
"TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
(define_insn "riscv_cv_alu_clipu"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIPU))]
"TARGET_XCVALU && !TARGET_64BIT"
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-11-08 11:09 ` Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-08 11:09 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/corev.md | 14 ++++++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 9 +++-
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+ {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
(and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
(match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+ "@internal
+ A 5-bit signed immediate for CORE-V Immediate Branch."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 0109e1836cf..7d7b952d817 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+ "cv.b%C1imm\t%2,%3,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index a37d035fa61..69a6319c2c8 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -400,6 +400,10 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
+(define_predicate "const_int5s_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
;; Predicates for the V extension.
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ae2217d0907..168c8665a7a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,14 @@
(define_asm_attributes
[(set_attr "type" "multi")])
+;; ..............................
+;;
+;; Machine Description Patterns
+;;
+;; ..............................
+
+(include "corev.md")
+
;; Ghost instructions produce no real code and introduce no hazards.
;; They exist purely to express an effect on dataflow.
(define_insn_reservation "ghost" 0
@@ -3632,4 +3640,3 @@
(include "vector.md")
(include "zicond.md")
(include "zc.md")
-(include "corev.md")
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0eac6d44fae..d06c0f8f416 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVELW) Var(riscv_xcv_subext)
+Mask(XCVBI) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 06a6d1776ff..6fee1144238 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
@item cv_elw
Test system has support for the CORE-V ELW extension.
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 12);
+ return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, 10);
+ return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, -16);
+ return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+ a = __builtin_expect(a, 0);
+ return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+ a = __builtin_expect(a, 15);
+ return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+ a = __builtin_expect(a, -17);
+ return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+ a = __builtin_expect(a, 16);
+ return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f388360ae56..0eae746e848 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
} "-march=rv32i_xcvelw" ]
}
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_bi object {
+ void foo (void)
+ {
+ asm ("cv.beqimm t0, -16, foo");
+ }
+ } "-march=rv32i_xcvbi" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-09 17:11 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-11-09 17:11 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 11/8/23 04:09, Mary Bennett wrote:
> +;; XCVELW builtins
> +(define_insn "riscv_cv_elw_elw_si"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
> + UNSPECV_CV_ELW))]
> +
> + "TARGET_XCVELW && !TARGET_64BIT"
> + "cv.elw\t%0,%a1"
> +
> + [(set_attr "type" "load")
> + (set_attr "mode" "SI")])
Would it make more sense to pull the MEM into the operand? So instead
of "address_operand", you'd define a new operand predicate which
accepted (mem (...)) and that chunk of your insn looks like
(unspec_volatile [(match_operand:SI 1 "new_predicate" "")] UNSPEC_CV_ELW))]
Or something close to that.
From a quick look at the docs it looks like the addressing modes are
similar to other extensions and could be re-used.
Thoughts?
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-11-10 1:08 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-11-10 1:08 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 11/8/23 04:09, Mary Bennett wrote:
> gcc/ChangeLog:
> * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
> * config/riscv/corev.md: Likewise.
Bikeshedding alert... Usually we keep constraint names pretty small. It
helps when you've got patterns that may have many constraints. I don't
see that likely happening here, so I think we're OK. But something to
keep in mind.
2^n - 1 is a pretty common constraint and normally I might suggest we
make this more generic for use elsewhere. But in this case there's a
restriction on the upper bound of 0x3fffffff, so it's not as generic as
2^n - 1 up to word size.
So OK for the trunk as-is.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-11-10 20:24 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-11-10 20:24 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 11/8/23 04:09, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Change pattern priority so corev.md
> patterns run before riscv.md patterns.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 0109e1836cf..7d7b952d817 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
> [(set_attr "type" "load")
> (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch<mode>"
> + [(set (pc)
> + (if_then_else
> + (match_operator 1 "equality_operator"
> + [(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> + (label_ref (match_operand 0 "" ""))
> + (pc)))]
> + "TARGET_XCVBI"
> + "cv.b%C1imm\t%2,%3,%0"
> + [(set_attr "type" "branch")
> + (set_attr "mode" "none")])
Note that technically you could use "i" or "n" for the constraint of
operand 3. This works because the predicate has priority and it only
allows -16..15.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index ae2217d0907..168c8665a7a 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -579,6 +579,14 @@
> (define_asm_attributes
> [(set_attr "type" "multi")])
>
> +;; ..............................
> +;;
> +;; Machine Description Patterns
> +;;
> +;; ..............................
> +
> +(include "corev.md")
I would put a comment here indicating why a subtarget might want to
include its patterns before the standard patterns in riscv.md.
OK with the comment added. Your decision on whether or not to drop the
CV_bi_sign5 constraint and replace it with "n".
Jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
` (2 preceding siblings ...)
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-11-13 13:35 ` Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
` (3 more replies)
3 siblings, 4 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-13 13:35 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
v1 -> v2:
* Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
* Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.
This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/constraints.md | 21 +++++---
gcc/config/riscv/corev.def | 3 ++
gcc/config/riscv/corev.md | 33 ++++++++++++-
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.md | 11 ++++-
gcc/config/riscv/riscv.opt | 4 ++
gcc/doc/extend.texi | 8 ++++
gcc/doc/sourcebuild.texi | 6 +++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++
gcc/testsuite/lib/target-supports.exp | 26 ++++++++++
17 files changed, 254 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
@ 2023-11-13 13:35 ` Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
` (2 subsequent siblings)
3 siblings, 0 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-13 13:35 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/corev.def | 3 +++
gcc/config/riscv/corev.md | 15 +++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 ++
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.opt | 2 ++
gcc/doc/extend.texi | 8 ++++++++
gcc/doc/sourcebuild.texi | 3 +++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
10 files changed, 60 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..6a1978bd0e4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+ {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT
RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
UNSPEC_CV_ALU_CLIPR
UNSPEC_CV_ALU_CLIPU
UNSPEC_CV_ALU_CLIPUR
+
+ ;;CORE-V EVENT LOAD
+ UNSPECV_CV_ELW
])
;; XCVMAC extension.
@@ -691,3 +694,15 @@
cv.suburnr\t%0,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
// CORE-V AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
+#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..3e7d5c69503 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
+DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UQI))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..0eac6d44fae 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
Mask(XCVALU) Var(riscv_xcv_subext)
+Mask(XCVELW) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index c8fc4e391b5..b890acccac1 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21970,6 +21970,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in
Generated assembler @code{cv.subuRNr} if the it is a register.
@end deftypefn
+These built-in functions are available for the CORE-V Event Load machine
+architecture. For more information on CORE-V ELW builtins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
+
+@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *)
+Generated assembler @code{cv.elw}
+@end deftypefn
+
@node RX Built-in Functions
@subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c20af31c642..06a6d1776ff 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
@item cv_alu
Test system has support for the CORE-V ALU extension.
+@item cv_elw
+Test system has support for the CORE-V ELW extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
new file mode 100644
index 00000000000..30f951c3f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_elw } */
+/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
+
+int
+foo (void* b)
+{
+ return __builtin_riscv_cv_elw_elw (b + 8);
+}
+
+/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 024939ee2e7..f388360ae56 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13085,6 +13085,19 @@ proc check_effective_target_cv_alu { } {
} "-march=rv32i_xcvalu" ]
}
+# Return 1 if the CORE-V ELW extension is available.
+proc check_effective_target_cv_elw { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_elw object {
+ void foo (void)
+ {
+ asm ("cv.elw x0, 0(x0)");
+ }
+ } "-march=rv32i_xcvelw" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-13 13:35 ` Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 0 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-13 13:35 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
gcc/config/riscv/constraints.md | 15 ++++++++-------
gcc/config/riscv/corev.md | 4 ++--
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
(define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
"An integer register for ZFA or XTheadFmv.")
-;; CORE-V Constraints
-(define_constraint "CVP2"
- "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
- (and (match_code "const_int")
- (and (match_test "IN_RANGE (ival, 0, 1073741823)")
- (match_test "exact_log2 (ival + 1) != -1"))))
-
;; Vector constraints.
(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
(and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+ "@internal
+ Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+ (and (match_code "const_int")
+ (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+ (match_test "exact_log2 (ival + 1) != -1"))))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
(define_insn "riscv_cv_alu_clip"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIP))]
"TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
(define_insn "riscv_cv_alu_clipu"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIPU))]
"TARGET_XCVALU && !TARGET_64BIT"
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-11-13 13:35 ` Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 2 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-13 13:35 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/corev.md | 14 ++++++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 11 ++++-
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 184 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+ {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
(and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
(match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+ "@internal
+ A 5-bit signed immediate for CORE-V Immediate Branch."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+ "cv.b%C1imm\t%2,%3,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index a37d035fa61..69a6319c2c8 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -400,6 +400,10 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
+(define_predicate "const_int5s_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
;; Predicates for the V extension.
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ae2217d0907..9a8572e6ef3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,16 @@
(define_asm_attributes
[(set_attr "type" "multi")])
+;; ..............................
+;;
+;; Machine Description Patterns
+;;
+;; ..............................
+
+;; To encourage the use of CORE-V specific branch instructions, the CORE-V
+;; instructions must be defined before the generic RISC-V instructions.
+(include "corev.md")
+
;; Ghost instructions produce no real code and introduce no hazards.
;; They exist purely to express an effect on dataflow.
(define_insn_reservation "ghost" 0
@@ -3632,4 +3642,3 @@
(include "vector.md")
(include "zicond.md")
(include "zc.md")
-(include "corev.md")
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0eac6d44fae..d06c0f8f416 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVELW) Var(riscv_xcv_subext)
+Mask(XCVBI) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 06a6d1776ff..6fee1144238 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
@item cv_elw
Test system has support for the CORE-V ELW extension.
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 12);
+ return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, 10);
+ return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, -16);
+ return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+ a = __builtin_expect(a, 0);
+ return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+ a = __builtin_expect(a, 15);
+ return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+ a = __builtin_expect(a, -17);
+ return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+ a = __builtin_expect(a, 16);
+ return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f388360ae56..0eae746e848 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
} "-march=rv32i_xcvelw" ]
}
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_bi object {
+ void foo (void)
+ {
+ asm ("cv.beqimm t0, -16, foo");
+ }
+ } "-march=rv32i_xcvbi" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
1 sibling, 0 replies; 32+ messages in thread
From: Kito Cheng @ 2023-11-13 14:41 UTC (permalink / raw)
To: Mary Bennett; +Cc: gcc-patches
I would prefer you suppress those patterns in riscv.cc rather than
adjust the including order, T-Head extension goes that way too, so I
would prefer to keep it using a consistent way.
you can search !TARGET_XTHEAD in riscv.md
On Mon, Nov 13, 2023 at 9:36 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Change pattern priority so corev.md
> patterns run before riscv.md patterns.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
> gcc/config/riscv/constraints.md | 6 +++
> gcc/config/riscv/corev.md | 14 ++++++
> gcc/config/riscv/predicates.md | 4 ++
> gcc/config/riscv/riscv.md | 11 ++++-
> gcc/config/riscv/riscv.opt | 2 +
> gcc/doc/sourcebuild.texi | 3 ++
> .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 13 +++++
> 12 files changed, 184 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6a1978bd0e4..04631e007f0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
> {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
> {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
> + {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
>
> {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
> {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
> (and (match_code "const_int")
> (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> + "@internal
> + A 5-bit signed immediate for CORE-V Immediate Branch."
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
> [(set_attr "type" "load")
> (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch<mode>"
> + [(set (pc)
> + (if_then_else
> + (match_operator 1 "equality_operator"
> + [(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> + (label_ref (match_operand 0 "" ""))
> + (pc)))]
> + "TARGET_XCVBI"
> + "cv.b%C1imm\t%2,%3,%0"
> + [(set_attr "type" "branch")
> + (set_attr "mode" "none")])
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index a37d035fa61..69a6319c2c8 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -400,6 +400,10 @@
> (ior (match_operand 0 "register_operand")
> (match_code "const_int")))
>
> +(define_predicate "const_int5s_operand"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
> +
> ;; Predicates for the V extension.
> (define_special_predicate "vector_length_operand"
> (ior (match_operand 0 "pmode_register_operand")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index ae2217d0907..9a8572e6ef3 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -579,6 +579,16 @@
> (define_asm_attributes
> [(set_attr "type" "multi")])
>
> +;; ..............................
> +;;
> +;; Machine Description Patterns
> +;;
> +;; ..............................
> +
> +;; To encourage the use of CORE-V specific branch instructions, the CORE-V
> +;; instructions must be defined before the generic RISC-V instructions.
> +(include "corev.md")
> +
> ;; Ghost instructions produce no real code and introduce no hazards.
> ;; They exist purely to express an effect on dataflow.
> (define_insn_reservation "ghost" 0
> @@ -3632,4 +3642,3 @@
> (include "vector.md")
> (include "zicond.md")
> (include "zc.md")
> -(include "corev.md")
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 0eac6d44fae..d06c0f8f416 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
>
> Mask(XCVELW) Var(riscv_xcv_subext)
>
> +Mask(XCVBI) Var(riscv_xcv_subext)
> +
> TargetVariable
> int riscv_xthead_subext
>
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index 06a6d1776ff..6fee1144238 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
> @item cv_elw
> Test system has support for the CORE-V ELW extension.
>
> +@item cv_bi
> +Test system has support for the CORE-V BI extension.
> +
> @end table
>
> @subsubsection Other hardware attributes
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> new file mode 100644
> index 00000000000..5b6ba5b8ae6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 12);
> + return a != 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> new file mode 100644
> index 00000000000..bb2e5843957
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != -16 ? x : y;
> +}
> +
> +int
> +foo2 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 0 ? x : y;
> +}
> +
> +int
> +foo3 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 15 ? x : y;
> +}
> +
> +int
> +foo4 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != -17 ? x : y;
> +}
> +
> +int
> +foo5 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> new file mode 100644
> index 00000000000..21eab38a08d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 10);
> + return a == 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> new file mode 100644
> index 00000000000..a028f684489
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> + a = __builtin_expect(a, -16);
> + return a == -16 ? x : y;
> +}
> +
> +int
> +foo2(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 0);
> + return a == 0 ? x : y;
> +}
> +
> +int
> +foo3(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 15);
> + return a == 15 ? x : y;
> +}
> +
> +int
> +foo4(int a, int x, int y)
> +{
> + a = __builtin_expect(a, -17);
> + return a == -17 ? x : y;
> +}
> +
> +int
> +foo5(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 16);
> + return a == 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index f388360ae56..0eae746e848 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
> } "-march=rv32i_xcvelw" ]
> }
>
> +# Return 1 if the CORE-V BI extension is available
> +proc check_effective_target_cv_bi { } {
> + if { !([istarget riscv*-*-*]) } {
> + return 0
> + }
> + return [check_no_compiler_messages cv_bi object {
> + void foo (void)
> + {
> + asm ("cv.beqimm t0, -16, foo");
> + }
> + } "-march=rv32i_xcvbi" ]
> +}
> +
> proc check_effective_target_loongarch_sx { } {
> return [check_no_compiler_messages loongarch_lsx assembly {
> #if !defined(__loongarch_sx)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
@ 2023-11-13 19:14 ` Patrick O'Neill
1 sibling, 0 replies; 32+ messages in thread
From: Patrick O'Neill @ 2023-11-13 19:14 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 17206 bytes --]
Hi Mary,
GCC tip-of-tree with this patch series applied fails to build glibc with:
--with-arch=rv32imac --with-abi=ilp32
--with-arch=rv32imafdc --with-abi=ilp32d
Failing command:
./bin/riscv32-unknown-elf-gcc
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/
-isystem
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/targ-include
-isystem
/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/newlib/libc/include
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/riscv32
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/libnosys
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/libgloss/riscv32
-DPACKAGE_NAME=\"newlib\" -DPACKAGE_TARNAME=\"newlib\"
-DPACKAGE_VERSION=\"4.1.0\" -DPACKAGE_STRING=\"newlib\ 4.1.0\"
-DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -I.
-I/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time
-fno-builtin -DHAVE_NANOSLEEP -O2 -D_POSIX_MODE -ffunction-sections
-fdata-sections -mcmodel=medlow -c -o lib_a-mktime.o `test -f
'mktime.c' || echo
'/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/'`mktime.c
during RTL pass: combine
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c:
In function 'validate_structure':
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c:148:1:
internal compiler error: Segmentation fault
148 | }
| ^
0x1276843 crash_signal
../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Creduced testcase:
./bin/riscv32-unknown-elf-gcc -O1 mktime.c -freport-bug
int a, b;
void c() { a = b % 7; }
during RTL pass: combine
mktime.c: In function 'c':
mktime.c:2:23: internal compiler error: Segmentation fault
2 | void c() { a = b % 7; }
| ^
0x1276843 crash_signal
../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /tmp/ccJL816S.out file, please attach
this to your bugreport.
I've attached the -freport-bug output to this email.
Thanks,
Patrick
glibc: a704fd9a133bfb10510e18702f48a6a9c88dbbd5
gcc base hash: 2020bce38cf2e02cbd1097faa8f1fd6586364a7e
On 11/13/23 05:35, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Change pattern priority so corev.md
> patterns run before riscv.md patterns.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
> gcc/config/riscv/constraints.md | 6 +++
> gcc/config/riscv/corev.md | 14 ++++++
> gcc/config/riscv/predicates.md | 4 ++
> gcc/config/riscv/riscv.md | 11 ++++-
> gcc/config/riscv/riscv.opt | 2 +
> gcc/doc/sourcebuild.texi | 3 ++
> .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 13 +++++
> 12 files changed, 184 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6a1978bd0e4..04631e007f0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
> {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
> {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
> + {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
>
> {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
> {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
> (and (match_code "const_int")
> (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> + "@internal
> + A 5-bit signed immediate for CORE-V Immediate Branch."
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
> [(set_attr "type" "load")
> (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch<mode>"
> + [(set (pc)
> + (if_then_else
> + (match_operator 1 "equality_operator"
> + [(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> + (label_ref (match_operand 0 "" ""))
> + (pc)))]
> + "TARGET_XCVBI"
> + "cv.b%C1imm\t%2,%3,%0"
> + [(set_attr "type" "branch")
> + (set_attr "mode" "none")])
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index a37d035fa61..69a6319c2c8 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -400,6 +400,10 @@
> (ior (match_operand 0 "register_operand")
> (match_code "const_int")))
>
> +(define_predicate "const_int5s_operand"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
> +
> ;; Predicates for the V extension.
> (define_special_predicate "vector_length_operand"
> (ior (match_operand 0 "pmode_register_operand")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index ae2217d0907..9a8572e6ef3 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -579,6 +579,16 @@
> (define_asm_attributes
> [(set_attr "type" "multi")])
>
> +;; ..............................
> +;;
> +;; Machine Description Patterns
> +;;
> +;; ..............................
> +
> +;; To encourage the use of CORE-V specific branch instructions, the CORE-V
> +;; instructions must be defined before the generic RISC-V instructions.
> +(include "corev.md")
> +
> ;; Ghost instructions produce no real code and introduce no hazards.
> ;; They exist purely to express an effect on dataflow.
> (define_insn_reservation "ghost" 0
> @@ -3632,4 +3642,3 @@
> (include "vector.md")
> (include "zicond.md")
> (include "zc.md")
> -(include "corev.md")
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 0eac6d44fae..d06c0f8f416 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
>
> Mask(XCVELW) Var(riscv_xcv_subext)
>
> +Mask(XCVBI) Var(riscv_xcv_subext)
> +
> TargetVariable
> int riscv_xthead_subext
>
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index 06a6d1776ff..6fee1144238 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
> @item cv_elw
> Test system has support for the CORE-V ELW extension.
>
> +@item cv_bi
> +Test system has support for the CORE-V BI extension.
> +
> @end table
>
> @subsubsection Other hardware attributes
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> new file mode 100644
> index 00000000000..5b6ba5b8ae6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 12);
> + return a != 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> new file mode 100644
> index 00000000000..bb2e5843957
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != -16 ? x : y;
> +}
> +
> +int
> +foo2 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 0 ? x : y;
> +}
> +
> +int
> +foo3 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 15 ? x : y;
> +}
> +
> +int
> +foo4 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != -17 ? x : y;
> +}
> +
> +int
> +foo5 (int a, int x, int y)
> +{
> + a = __builtin_expect (a, 10);
> + return a != 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> new file mode 100644
> index 00000000000..21eab38a08d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 10);
> + return a == 10 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> new file mode 100644
> index 00000000000..a028f684489
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
> @@ -0,0 +1,48 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_bi } */
> +/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
> +
> +/* __builtin_expect is used to provide the compiler with
> + branch prediction information and to direct the compiler
> + to the expected flow through the code. */
> +
> +int
> +foo1(int a, int x, int y)
> +{
> + a = __builtin_expect(a, -16);
> + return a == -16 ? x : y;
> +}
> +
> +int
> +foo2(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 0);
> + return a == 0 ? x : y;
> +}
> +
> +int
> +foo3(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 15);
> + return a == 15 ? x : y;
> +}
> +
> +int
> +foo4(int a, int x, int y)
> +{
> + a = __builtin_expect(a, -17);
> + return a == -17 ? x : y;
> +}
> +
> +int
> +foo5(int a, int x, int y)
> +{
> + a = __builtin_expect(a, 16);
> + return a == 16 ? x : y;
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
> +/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index f388360ae56..0eae746e848 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -13098,6 +13098,19 @@ proc check_effective_target_cv_elw { } {
> } "-march=rv32i_xcvelw" ]
> }
>
> +# Return 1 if the CORE-V BI extension is available
> +proc check_effective_target_cv_bi { } {
> + if { !([istarget riscv*-*-*]) } {
> + return 0
> + }
> + return [check_no_compiler_messages cv_bi object {
> + void foo (void)
> + {
> + asm ("cv.beqimm t0, -16, foo");
> + }
> + } "-march=rv32i_xcvbi" ]
> +}
> +
> proc check_effective_target_loongarch_sx { } {
> return [check_no_compiler_messages loongarch_lsx assembly {
> #if !defined(__loongarch_sx)
[-- Attachment #2: ccJL816S.out --]
[-- Type: text/plain, Size: 2170 bytes --]
// Target: riscv32-unknown-elf
// Configured with: /scratch/tc-testing/tc-nov-13-zcvbi-series/build/../gcc/configure --target=riscv32-unknown-elf --prefix=/scratch/tc-testing/tc-nov-13-zcvbi-series/build --disable-shared --disable-threads --disable-tls --enable-languages=c,c++ --with-system-zlib --with-newlib --with-sysroot=/scratch/tc-testing/tc-nov-13-zcvbi-series/build/riscv32-unknown-elf --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../gcc --disable-multilib --with-abi=ilp32 --with-arch=rv32imac --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-Os -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medlow'
// Thread model: single
// Supported LTO compression algorithms: zlib zstd
// gcc version 14.0.0 20231109 (experimental) (GCC)
//
// during RTL pass: combine
// mktime.c: In function 'c':
// mktime.c:2:23: internal compiler error: Segmentation fault
// 2 | void c() { a = b % 7; }
// | ^
// 0x1276843 crash_signal
// ../../../gcc/gcc/toplev.cc:316
// 0x2136c93 recog_1349
// ../../../gcc/gcc/config/riscv/thead.md:438
// 0x21dcab5 recog_for_combine_1
// ../../../gcc/gcc/combine.cc:11382
// 0x21e12ae recog_for_combine
// ../../../gcc/gcc/combine.cc:11652
// 0x21f594a try_combine
// ../../../gcc/gcc/combine.cc:3867
// 0x21f8159 combine_instructions
// ../../../gcc/gcc/combine.cc:1285
// 0x21f8159 rest_of_handle_combine
// ../../../gcc/gcc/combine.cc:15080
// 0x21f8159 execute
// ../../../gcc/gcc/combine.cc:15124
// Please submit a full bug report, with preprocessed source.
// Please include the complete backtrace with any bug report.
// See <https://gcc.gnu.org/bugs/> for instructions.
// /scratch/tc-testing/tc-nov-13-zcvbi-series/build/libexec/gcc/riscv32-unknown-elf/14.0.0/cc1 -quiet -imultilib . mktime.c -quiet -dumpdir a- -dumpbase mktime.c -dumpbase-ext .c -mtune=rocket -march=rv32imac -mabi=ilp32 -misa-spec=20191213 -march=rv32imac -O1 -freport-bug -o - -frandom-seed=0 -fdump-noaddr
# 0 "mktime.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "mktime.c"
int a, b;
void c() { a = b % 7; }
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
` (2 preceding siblings ...)
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-11-28 13:16 ` Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
` (3 more replies)
3 siblings, 4 replies; 32+ messages in thread
From: Mary Bennett @ 2023-11-28 13:16 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
v1 -> v2:
* Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
* Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.
v2 -> v3:
* Merged patterns for CORE-V branch immediate and generic RISC-V so to
supress the generic patterns if XCVbi is available.
This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/constraints.md | 21 +++++---
gcc/config/riscv/corev.def | 3 ++
gcc/config/riscv/corev.md | 33 ++++++++++++-
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.md | 4 ++
gcc/config/riscv/riscv.opt | 4 ++
gcc/doc/extend.texi | 8 ++++
gcc/doc/sourcebuild.texi | 6 +++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++
gcc/testsuite/lib/target-supports.exp | 26 ++++++++++
17 files changed, 248 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
@ 2023-11-28 13:16 ` Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
` (2 subsequent siblings)
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-28 13:16 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/corev.def | 3 +++
gcc/config/riscv/corev.md | 15 +++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 ++
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.opt | 2 ++
gcc/doc/extend.texi | 8 ++++++++
gcc/doc/sourcebuild.texi | 3 +++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
10 files changed, 60 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..c8c0d0a2252 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+ {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT
RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
UNSPEC_CV_ALU_CLIPR
UNSPEC_CV_ALU_CLIPU
UNSPEC_CV_ALU_CLIPUR
+
+ ;;CORE-V EVENT LOAD
+ UNSPECV_CV_ELW
])
;; XCVMAC extension.
@@ -691,3 +694,15 @@
cv.suburnr\t%0,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
// CORE-V AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
+#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..3e7d5c69503 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
+DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UQI))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 11526f9cc2a..bfa0945daca 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
Mask(XCVALU) Var(riscv_xcv_subext)
+Mask(XCVELW) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 9474e9398bb..b89aa915b7e 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22084,6 +22084,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in
Generated assembler @code{cv.subuRNr} if the it is a register.
@end deftypefn
+These built-in functions are available for the CORE-V Event Load machine
+architecture. For more information on CORE-V ELW builtins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
+
+@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *)
+Generated assembler @code{cv.elw}
+@end deftypefn
+
@node RX Built-in Functions
@subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index e27e0fa606c..d63b11d245c 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
@item cv_alu
Test system has support for the CORE-V ALU extension.
+@item cv_elw
+Test system has support for the CORE-V ELW extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
new file mode 100644
index 00000000000..30f951c3f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_elw } */
+/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
+
+int
+foo (void* b)
+{
+ return __builtin_riscv_cv_elw_elw (b + 8);
+}
+
+/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 87b2ae58720..c324a7898fc 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13147,6 +13147,19 @@ proc check_effective_target_cv_alu { } {
} "-march=rv32i_xcvalu" ]
}
+# Return 1 if the CORE-V ELW extension is available.
+proc check_effective_target_cv_elw { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_elw object {
+ void foo (void)
+ {
+ asm ("cv.elw x0, 0(x0)");
+ }
+ } "-march=rv32i_xcvelw" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-11-28 13:16 ` Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-28 13:16 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
gcc/config/riscv/constraints.md | 15 ++++++++-------
gcc/config/riscv/corev.md | 4 ++--
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
(define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
"An integer register for ZFA or XTheadFmv.")
-;; CORE-V Constraints
-(define_constraint "CVP2"
- "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
- (and (match_code "const_int")
- (and (match_test "IN_RANGE (ival, 0, 1073741823)")
- (match_test "exact_log2 (ival + 1) != -1"))))
-
;; Vector constraints.
(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
(and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+ "@internal
+ Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+ (and (match_code "const_int")
+ (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+ (match_test "exact_log2 (ival + 1) != -1"))))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
(define_insn "riscv_cv_alu_clip"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIP))]
"TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
(define_insn "riscv_cv_alu_clipu"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIPU))]
"TARGET_XCVALU && !TARGET_64BIT"
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-11-28 13:16 ` Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
3 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-11-28 13:16 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/corev.md | 14 ++++++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 4 ++
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 178 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c8c0d0a2252..125f8fb71f7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1678,6 +1679,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+ {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
(and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
(match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+ "@internal
+ A 5-bit signed immediate for CORE-V Immediate Branch."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+ "cv.b%C1imm\t%2,%3,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index ff213e5f8a3..dfe0db02ac1 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -406,6 +406,10 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
+(define_predicate "const_int5s_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
;; Predicates for the V extension.
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 935eeb7fd8e..467cd09d8b0 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2647,6 +2647,10 @@
(pc)))]
""
{
+ if (TARGET_XCVBI && const_int5s_operand (operands[3], SImode)
+ && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE))
+ return "cv.b%C1imm\t%2,%3,%0";
+
if (get_attr_length (insn) == 12)
return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index bfa0945daca..e11172388b5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVELW) Var(riscv_xcv_subext)
+Mask(XCVBI) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index d63b11d245c..3d72b88a4a9 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
@item cv_elw
Test system has support for the CORE-V ELW extension.
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 12);
+ return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, 10);
+ return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, -16);
+ return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+ a = __builtin_expect(a, 0);
+ return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+ a = __builtin_expect(a, 15);
+ return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+ a = __builtin_expect(a, -17);
+ return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+ a = __builtin_expect(a, 16);
+ return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index c324a7898fc..9c8e2ed1896 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13160,6 +13160,19 @@ proc check_effective_target_cv_elw { } {
} "-march=rv32i_xcvelw" ]
}
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_bi object {
+ void foo (void)
+ {
+ asm ("cv.beqimm t0, -16, foo");
+ }
+ } "-march=rv32i_xcvbi" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-12-05 15:11 ` Kito Cheng
0 siblings, 0 replies; 32+ messages in thread
From: Kito Cheng @ 2023-12-05 15:11 UTC (permalink / raw)
To: Mary Bennett; +Cc: gcc-patches
LGTM
On Tue, Nov 28, 2023 at 9:17 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Add XCVelw.
> * config/riscv/corev.def: Likewise.
> * config/riscv/corev.md: Likewise.
> * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
> * config/riscv/riscv-ftypes.def: Likewise.
> * config/riscv/riscv.opt: Likewise.
> * doc/extend.texi: Add XCVelw builtin documentation.
> * doc/sourcebuild.texi: Likewise.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
> * testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 ++
> gcc/config/riscv/corev.def | 3 +++
> gcc/config/riscv/corev.md | 15 +++++++++++++++
> gcc/config/riscv/riscv-builtins.cc | 2 ++
> gcc/config/riscv/riscv-ftypes.def | 1 +
> gcc/config/riscv/riscv.opt | 2 ++
> gcc/doc/extend.texi | 8 ++++++++
> gcc/doc/sourcebuild.texi | 3 +++
> .../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
> gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
> 10 files changed, 60 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 5111626157b..c8c0d0a2252 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>
> {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>
> {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
> {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
> + {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
>
> {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
> {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
> index 17580df3c41..3b9ec029d06 100644
> --- a/gcc/config/riscv/corev.def
> +++ b/gcc/config/riscv/corev.def
> @@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT
> RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
> RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
> RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
> +
> +// XCVELW
> +RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 1350bd4b81e..c7a2ba07bcc 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -24,6 +24,9 @@
> UNSPEC_CV_ALU_CLIPR
> UNSPEC_CV_ALU_CLIPU
> UNSPEC_CV_ALU_CLIPUR
> +
> + ;;CORE-V EVENT LOAD
> + UNSPECV_CV_ELW
> ])
>
> ;; XCVMAC extension.
> @@ -691,3 +694,15 @@
> cv.suburnr\t%0,%2,%3"
> [(set_attr "type" "arith")
> (set_attr "mode" "SI")])
> +
> +;; XCVELW builtins
> +(define_insn "riscv_cv_elw_elw_si"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
> + UNSPECV_CV_ELW))]
> +
> + "TARGET_XCVELW && !TARGET_64BIT"
> + "cv.elw\t%0,%a1"
> +
> + [(set_attr "type" "load")
> + (set_attr "mode" "SI")])
> diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
> index fc3976f3ba1..5ee11ebe3bc 100644
> --- a/gcc/config/riscv/riscv-builtins.cc
> +++ b/gcc/config/riscv/riscv-builtins.cc
> @@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
> // CORE-V AVAIL
> AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
> AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
> +AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
>
> /* Construct a riscv_builtin_description from the given arguments.
>
> @@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
> #define RISCV_ATYPE_HI intHI_type_node
> #define RISCV_ATYPE_SI intSI_type_node
> #define RISCV_ATYPE_VOID_PTR ptr_type_node
> +#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
>
> /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
> their associated RISCV_ATYPEs. */
> diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
> index 0d1e4dd061e..3e7d5c69503 100644
> --- a/gcc/config/riscv/riscv-ftypes.def
> +++ b/gcc/config/riscv/riscv-ftypes.def
> @@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
> DEF_RISCV_FTYPE (0, (VOID))
> DEF_RISCV_FTYPE (1, (VOID, USI))
> DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
> +DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
> DEF_RISCV_FTYPE (1, (USI, USI))
> DEF_RISCV_FTYPE (1, (UDI, UDI))
> DEF_RISCV_FTYPE (1, (USI, UQI))
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 11526f9cc2a..bfa0945daca 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
>
> Mask(XCVALU) Var(riscv_xcv_subext)
>
> +Mask(XCVELW) Var(riscv_xcv_subext)
> +
> TargetVariable
> int riscv_xthead_subext
>
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 9474e9398bb..b89aa915b7e 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22084,6 +22084,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in
> Generated assembler @code{cv.subuRNr} if the it is a register.
> @end deftypefn
>
> +These built-in functions are available for the CORE-V Event Load machine
> +architecture. For more information on CORE-V ELW builtins, please see
> +@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
> +
> +@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *)
> +Generated assembler @code{cv.elw}
> +@end deftypefn
> +
> @node RX Built-in Functions
> @subsection RX Built-in Functions
> GCC supports some of the RX instructions which cannot be expressed in
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index e27e0fa606c..d63b11d245c 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
> @item cv_alu
> Test system has support for the CORE-V ALU extension.
>
> +@item cv_elw
> +Test system has support for the CORE-V ELW extension.
> +
> @end table
>
> @subsubsection Other hardware attributes
> diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
> new file mode 100644
> index 00000000000..30f951c3f0a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target cv_elw } */
> +/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
> +
> +int
> +foo (void* b)
> +{
> + return __builtin_riscv_cv_elw_elw (b + 8);
> +}
> +
> +/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index 87b2ae58720..c324a7898fc 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -13147,6 +13147,19 @@ proc check_effective_target_cv_alu { } {
> } "-march=rv32i_xcvalu" ]
> }
>
> +# Return 1 if the CORE-V ELW extension is available.
> +proc check_effective_target_cv_elw { } {
> + if { !([istarget riscv*-*-*]) } {
> + return 0
> + }
> + return [check_no_compiler_messages cv_elw object {
> + void foo (void)
> + {
> + asm ("cv.elw x0, 0(x0)");
> + }
> + } "-march=rv32i_xcvelw" ]
> +}
> +
> proc check_effective_target_loongarch_sx { } {
> return [check_no_compiler_messages loongarch_lsx assembly {
> #if !defined(__loongarch_sx)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-12-05 15:11 ` Kito Cheng
0 siblings, 0 replies; 32+ messages in thread
From: Kito Cheng @ 2023-12-05 15:11 UTC (permalink / raw)
To: Mary Bennett; +Cc: gcc-patches
LGTM
On Tue, Nov 28, 2023 at 9:17 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> gcc/ChangeLog:
> * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
> * config/riscv/corev.md: Likewise.
> ---
> gcc/config/riscv/constraints.md | 15 ++++++++-------
> gcc/config/riscv/corev.md | 4 ++--
> 2 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 68be4515c04..2711efe68c5 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -151,13 +151,6 @@
> (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
> "An integer register for ZFA or XTheadFmv.")
>
> -;; CORE-V Constraints
> -(define_constraint "CVP2"
> - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
> - (and (match_code "const_int")
> - (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> - (match_test "exact_log2 (ival + 1) != -1"))))
> -
> ;; Vector constraints.
>
> (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
> @@ -246,3 +239,11 @@
> A MEM with a valid address for th.[l|s]*ur* instructions."
> (and (match_code "mem")
> (match_test "th_memidx_legitimate_index_p (op, true)")))
> +
> +;; CORE-V Constraints
> +(define_constraint "CV_alu_pow2"
> + "@internal
> + Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
> + (and (match_code "const_int")
> + (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> + (match_test "exact_log2 (ival + 1) != -1"))))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index c7a2ba07bcc..92bf0b5d6a6 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -516,7 +516,7 @@
> (define_insn "riscv_cv_alu_clip"
> [(set (match_operand:SI 0 "register_operand" "=r,r")
> (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
> - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
> + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
> UNSPEC_CV_ALU_CLIP))]
>
> "TARGET_XCVALU && !TARGET_64BIT"
> @@ -529,7 +529,7 @@
> (define_insn "riscv_cv_alu_clipu"
> [(set (match_operand:SI 0 "register_operand" "=r,r")
> (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
> - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
> + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
> UNSPEC_CV_ALU_CLIPU))]
>
> "TARGET_XCVALU && !TARGET_64BIT"
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-12-05 15:24 ` Kito Cheng
0 siblings, 0 replies; 32+ messages in thread
From: Kito Cheng @ 2023-12-05 15:24 UTC (permalink / raw)
To: Mary Bennett; +Cc: gcc-patches
On Tue, Nov 28, 2023 at 9:17 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
> branch instruction pattern.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
> gcc/config/riscv/constraints.md | 6 +++
> gcc/config/riscv/corev.md | 14 ++++++
> gcc/config/riscv/predicates.md | 4 ++
> gcc/config/riscv/riscv.md | 4 ++
> gcc/config/riscv/riscv.opt | 2 +
> gcc/doc/sourcebuild.texi | 3 ++
> .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 13 +++++
> 12 files changed, 178 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index c8c0d0a2252..125f8fb71f7 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1678,6 +1679,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
> {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
> {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
> + {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
>
> {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
> {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
> (and (match_code "const_int")
> (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> + "@internal
> + A 5-bit signed immediate for CORE-V Immediate Branch."
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
> [(set_attr "type" "load")
> (set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
It's not builtin I think? maybe just "XCVBI Instructions"
> +(define_insn "cv_branch<mode>"
"*cv_branch<mode>"
> + [(set (pc)
> + (if_then_else
> + (match_operator 1 "equality_operator"
> + [(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> + (label_ref (match_operand 0 "" ""))
> + (pc)))]
> + "TARGET_XCVBI"
> + "cv.b%C1imm\t%2,%3,%0"
And then duplicate content of "*branch<mode>" here.
> + [(set_attr "type" "branch")
> + (set_attr "mode" "none")])
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index ff213e5f8a3..dfe0db02ac1 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -406,6 +406,10 @@
> (ior (match_operand 0 "register_operand")
> (match_code "const_int")))
>
> +(define_predicate "const_int5s_operand"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
> +
> ;; Predicates for the V extension.
> (define_special_predicate "vector_length_operand"
> (ior (match_operand 0 "pmode_register_operand")
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 935eeb7fd8e..467cd09d8b0 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2647,6 +2647,10 @@
> (pc)))]
> ""
I would prefer to put (!TARGET_XCVBI || !equality_operator
(operands[1], <MODE>mode)) here,
The intention of that is dispatch == and != to cv_branch if it is enabled.
> {
> + if (TARGET_XCVBI && const_int5s_operand (operands[3], SImode)
> + && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE))
> + return "cv.b%C1imm\t%2,%3,%0";
then this is not necessary, just use cv_branch,
and I guess this can't not handle long branches well, you may need
something like that:
if (get_attr_length (insn) == 12)
return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
> +
> if (get_attr_length (insn) == 12)
> return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
` (2 preceding siblings ...)
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-12-12 19:32 ` Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
` (2 more replies)
3 siblings, 3 replies; 32+ messages in thread
From: Mary Bennett @ 2023-12-12 19:32 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Thank you for reviewing my patches!
v1 -> v2:
* Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
* Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.
v2 -> v3:
* Merge patterns for CORE-V branch immediate and generic RISC-V so to
supress the generic patterns if XCVbi is available.
v3 -> v4:
* Add duplicate content of "*branch<mode>" to corev.md.
This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/constraints.md | 21 +++++---
gcc/config/riscv/corev.def | 3 ++
gcc/config/riscv/corev.md | 51 ++++++++++++++++++-
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 4 ++
gcc/doc/extend.texi | 8 +++
gcc/doc/sourcebuild.texi | 6 +++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 ++++
gcc/testsuite/lib/target-supports.exp | 26 ++++++++++
17 files changed, 263 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
@ 2023-12-12 19:32 ` Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-12-12 19:32 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/corev.def | 3 +++
gcc/config/riscv/corev.md | 15 +++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 ++
gcc/config/riscv/riscv-ftypes.def | 1 +
gcc/config/riscv/riscv.opt | 2 ++
gcc/doc/extend.texi | 8 ++++++++
gcc/doc/sourcebuild.texi | 3 +++
.../gcc.target/riscv/cv-elw-elw-compile-1.c | 11 +++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++++++++++
10 files changed, 60 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..c8c0d0a2252 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+ {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", RISCV_BUILTIN_DIRECT, RISCV_SI_FT
RISCV_BUILTIN (cv_alu_subuN, "cv_alu_subuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subRN, "cv_alu_subRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
RISCV_BUILTIN (cv_alu_subuRN, "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
UNSPEC_CV_ALU_CLIPR
UNSPEC_CV_ALU_CLIPU
UNSPEC_CV_ALU_CLIPUR
+
+ ;;CORE-V EVENT LOAD
+ UNSPECV_CV_ELW
])
;; XCVMAC extension.
@@ -691,3 +694,15 @@
cv.suburnr\t%0,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+ "TARGET_XCVELW && !TARGET_64BIT"
+ "cv.elw\t%0,%a1"
+
+ [(set_attr "type" "load")
+ (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
// CORE-V AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
/* Construct a riscv_builtin_description from the given arguments.
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
#define RISCV_ATYPE_HI intHI_type_node
#define RISCV_ATYPE_SI intSI_type_node
#define RISCV_ATYPE_VOID_PTR ptr_type_node
+#define RISCV_ATYPE_INT_PTR integer_ptr_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..3e7d5c69503 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,6 +30,7 @@ DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (0, (VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
+DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
DEF_RISCV_FTYPE (1, (USI, USI))
DEF_RISCV_FTYPE (1, (UDI, UDI))
DEF_RISCV_FTYPE (1, (USI, UQI))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 11526f9cc2a..bfa0945daca 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -411,6 +411,8 @@ Mask(XCVMAC) Var(riscv_xcv_subext)
Mask(XCVALU) Var(riscv_xcv_subext)
+Mask(XCVELW) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 9474e9398bb..b89aa915b7e 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22084,6 +22084,14 @@ Generated assembler @code{cv.subuRN} if the uint8_t operand is a constant and in
Generated assembler @code{cv.subuRNr} if the it is a register.
@end deftypefn
+These built-in functions are available for the CORE-V Event Load machine
+architecture. For more information on CORE-V ELW builtins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-event-load-word-builtins-xcvelw}
+
+@deftypefn {Built-in Function} {uint32_t} __builtin_riscv_cv_elw_elw (uint32_t *)
+Generated assembler @code{cv.elw}
+@end deftypefn
+
@node RX Built-in Functions
@subsection RX Built-in Functions
GCC supports some of the RX instructions which cannot be expressed in
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index e27e0fa606c..d63b11d245c 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2481,6 +2481,9 @@ Test system has support for the CORE-V MAC extension.
@item cv_alu
Test system has support for the CORE-V ALU extension.
+@item cv_elw
+Test system has support for the CORE-V ELW extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
new file mode 100644
index 00000000000..30f951c3f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_elw } */
+/* { dg-options "-march=rv32i_xcvelw -mabi=ilp32" } */
+
+int
+foo (void* b)
+{
+ return __builtin_riscv_cv_elw_elw (b + 8);
+}
+
+/* { dg-final { scan-assembler-times "cv\\.elw\t\[a-z\]\[0-99\],\[0-99\]\\(\[a-z\]\[0-99\]\\)" 1 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 87b2ae58720..c324a7898fc 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13147,6 +13147,19 @@ proc check_effective_target_cv_alu { } {
} "-march=rv32i_xcvalu" ]
}
+# Return 1 if the CORE-V ELW extension is available.
+proc check_effective_target_cv_elw { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_elw object {
+ void foo (void)
+ {
+ asm ("cv.elw x0, 0(x0)");
+ }
+ } "-march=rv32i_xcvelw" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-12-12 19:32 ` Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2023-12-12 19:32 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
gcc/config/riscv/constraints.md | 15 ++++++++-------
gcc/config/riscv/corev.md | 4 ++--
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
(define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
"An integer register for ZFA or XTheadFmv.")
-;; CORE-V Constraints
-(define_constraint "CVP2"
- "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
- (and (match_code "const_int")
- (and (match_test "IN_RANGE (ival, 0, 1073741823)")
- (match_test "exact_log2 (ival + 1) != -1"))))
-
;; Vector constraints.
(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
(and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+ "@internal
+ Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+ (and (match_code "const_int")
+ (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+ (match_test "exact_log2 (ival + 1) != -1"))))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
(define_insn "riscv_cv_alu_clip"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIP))]
"TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
(define_insn "riscv_cv_alu_clipu"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+ (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
UNSPEC_CV_ALU_CLIPU))]
"TARGET_XCVALU && !TARGET_64BIT"
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-12-12 19:32 ` Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2 siblings, 2 replies; 32+ messages in thread
From: Mary Bennett @ 2023-12-12 19:32 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/corev.md | 32 +++++++++++++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index c8c0d0a2252..125f8fb71f7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1678,6 +1679,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+ {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
(and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
(match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+ "@internal
+ A 5-bit signed immediate for CORE-V Immediate Branch."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..92e30a8ae04 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,35 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Instructions
+(define_insn "cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+ "cv.b%C1imm\t%2,%3,%0"
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+(define_insn "*branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "ordered_comparison_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "reg_or_0_operand" "rJ")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+{
+ if (get_attr_length (insn) == 12)
+ return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+ return "b%C1\t%2,%z3,%l0";
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index ff213e5f8a3..dfe0db02ac1 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -406,6 +406,10 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
+(define_predicate "const_int5s_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
;; Predicates for the V extension.
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 935eeb7fd8e..884dcb041e6 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2645,7 +2645,7 @@
(match_operand:X 3 "reg_or_0_operand" "rJ")])
(label_ref (match_operand 0 "" ""))
(pc)))]
- ""
+ "!TARGET_XCVBI"
{
if (get_attr_length (insn) == 12)
return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index bfa0945daca..e11172388b5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -413,6 +413,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVELW) Var(riscv_xcv_subext)
+Mask(XCVBI) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index d63b11d245c..3d72b88a4a9 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2484,6 +2484,9 @@ Test system has support for the CORE-V ALU extension.
@item cv_elw
Test system has support for the CORE-V ELW extension.
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 12);
+ return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, 10);
+ return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, -16);
+ return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+ a = __builtin_expect(a, 0);
+ return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+ a = __builtin_expect(a, 15);
+ return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+ a = __builtin_expect(a, -17);
+ return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+ a = __builtin_expect(a, 16);
+ return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index c324a7898fc..9c8e2ed1896 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13160,6 +13160,19 @@ proc check_effective_target_cv_elw { } {
} "-march=rv32i_xcvelw" ]
}
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_bi object {
+ void foo (void)
+ {
+ asm ("cv.beqimm t0, -16, foo");
+ }
+ } "-march=rv32i_xcvbi" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
@ 2023-12-15 22:01 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-12-15 22:01 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 12/12/23 12:32, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Add XCVelw.
> * config/riscv/corev.def: Likewise.
> * config/riscv/corev.md: Likewise.
> * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
> * config/riscv/riscv-ftypes.def: Likewise.
> * config/riscv/riscv.opt: Likewise.
> * doc/extend.texi: Add XCVelw builtin documentation.
> * doc/sourcebuild.texi: Likewise.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
> * testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
Kito ACK'd V3. I'm going to go ahead and push this to the trunk on
Mary's behalf. It looks independent to me and there's no need for it to
wait.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
@ 2023-12-15 23:11 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-12-15 23:11 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 12/12/23 12:32, Mary Bennett wrote:
> gcc/ChangeLog:
> * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
> * config/riscv/corev.md: Likewise.
> ---
Kito ack'd the V3 patch, so I went ahead and pushed this to the trunk.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
1 sibling, 0 replies; 32+ messages in thread
From: Jeff Law @ 2023-12-15 23:21 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 12/12/23 12:32, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
> branch instruction pattern.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
> gcc/config/riscv/constraints.md | 6 +++
> gcc/config/riscv/corev.md | 32 +++++++++++++
> gcc/config/riscv/predicates.md | 4 ++
> gcc/config/riscv/riscv.md | 2 +-
> gcc/config/riscv/riscv.opt | 2 +
> gcc/doc/sourcebuild.texi | 3 ++
> .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
> .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 13 +++++
> 12 files changed, 193 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
> (and (match_code "const_int")
> (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> (match_test "exact_log2 (ival + 1) != -1"))))
> +
> +(define_constraint "CV_bi_sign5"
> + "@internal
> + A 5-bit signed immediate for CORE-V Immediate Branch."
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..92e30a8ae04 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,35 @@
>
> [(set_attr "type" "load")
> (set_attr "mode" "SI")])
> +
> +;; XCVBI Instructions
> +(define_insn "cv_branch<mode>" > + [(set (pc)
> + (if_then_else
> + (match_operator 1 "equality_operator"
> + [(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
> + (label_ref (match_operand 0 "" ""))
> + (pc)))]
> + "TARGET_XCVBI"
> + "cv.b%C1imm\t%2,%3,%0"
> + [(set_attr "type" "branch")
> + (set_attr "mode" "none")])
So I think Kito wanted the name of this pattern to be prefixed with '*'.
My question is how does that pattern deal with out of range branch
targets? As Kito mentioned on the V3, you probably need to handle that.
I think this suggestion from Kito was meant to be added to that pattern
so that it works in a manner similar to the *branch<mode> pattern:
> if (get_attr_length (insn) == 12)
> return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
Jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
@ 2024-01-08 13:14 ` Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
1 sibling, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2024-01-08 13:14 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Thank you for reviewing my patches and merging XCVelw.
This patch series presents the comprehensive implementation of the BI
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Add support for XCVbi extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/constraints.md | 21 +++++---
gcc/config/riscv/corev.def | 3 ++
gcc/config/riscv/corev.md | 51 ++++++++++++++++++-
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
@ 2024-01-08 13:14 ` Mary Bennett
2024-01-09 18:43 ` Jeff Law
0 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2024-01-08 13:14 UTC (permalink / raw)
To: gcc-patches; +Cc: mary.bennett
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch<mode> pattern
for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/corev.md | 37 ++++++++++++++
gcc/config/riscv/predicates.md | 4 ++
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 2 +
gcc/doc/sourcebuild.texi | 3 ++
.../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
.../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 13 +++++
12 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..d61164a42b9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -355,6 +355,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1730,6 +1731,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
{"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
{"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+ {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
{"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
{"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index ee1c12b2e51..e4bfa227a2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -262,3 +262,9 @@
(and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
(match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+ "@internal
+ A 5-bit signed immediate for CORE-V Immediate Branch."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index adad2409fb6..66e0e998e41 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,40 @@
[(set_attr "type" "load")
(set_attr "mode" "SI")])
+
+;; XCVBI Instructions
+(define_insn "*cv_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "equality_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+{
+ if (get_attr_length (insn) == 12)
+ return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+ return "cv.b%C1imm\t%2,%3,%0";
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
+
+(define_insn "*branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "ordered_comparison_operator"
+ [(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "reg_or_0_operand" "rJ")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_XCVBI"
+{
+ if (get_attr_length (insn) == 12)
+ return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+ return "b%C1\t%2,%z3,%l0";
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index b1a79cae50a..26a67ddf628 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -425,6 +425,10 @@
(ior (match_operand 0 "register_operand")
(match_code "const_int")))
+(define_predicate "const_int5s_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
;; Predicates for the V extension.
(define_special_predicate "vector_length_operand"
(ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..5b7bae1ce71 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2732,7 +2732,7 @@
(match_operand:X 3 "reg_or_0_operand" "rJ")])
(label_ref (match_operand 0 "" ""))
(pc)))]
- ""
+ "!TARGET_XCVBI"
{
if (get_attr_length (insn) == 12)
return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..d51027350af 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -425,6 +425,8 @@ Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVELW) Var(riscv_xcv_subext)
+Mask(XCVBI) Var(riscv_xcv_subext)
+
TargetVariable
int riscv_xthead_subext
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 3a394e7739b..130a6d964e3 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2505,6 +2505,9 @@ Test system has support for the CORE-V ALU extension.
@item cv_elw
Test system has support for the CORE-V ELW extension.
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
@end table
@subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 12);
+ return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+ a = __builtin_expect (a, 10);
+ return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, 10);
+ return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+ branch prediction information and to direct the compiler
+ to the expected flow through the code. */
+
+int
+foo1(int a, int x, int y)
+{
+ a = __builtin_expect(a, -16);
+ return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+ a = __builtin_expect(a, 0);
+ return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+ a = __builtin_expect(a, 15);
+ return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+ a = __builtin_expect(a, -17);
+ return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+ a = __builtin_expect(a, 16);
+ return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b27c30b8c51..8d90aa15c95 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13314,6 +13314,19 @@ proc check_effective_target_cv_elw { } {
} "-march=rv32i_xcvelw" ]
}
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+ if { !([istarget riscv*-*-*]) } {
+ return 0
+ }
+ return [check_no_compiler_messages cv_bi object {
+ void foo (void)
+ {
+ asm ("cv.beqimm t0, -16, foo");
+ }
+ } "-march=rv32i_xcvbi" ]
+}
+
proc check_effective_target_loongarch_sx { } {
return [check_no_compiler_messages loongarch_lsx assembly {
#if !defined(__loongarch_sx)
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
@ 2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett
0 siblings, 1 reply; 32+ messages in thread
From: Jeff Law @ 2024-01-09 18:43 UTC (permalink / raw)
To: Mary Bennett, gcc-patches
On 1/8/24 06:14, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
> Mary Bennett <mary.bennett@embecosm.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
> support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch<mode> pattern
> for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
> branch instruction pattern.
> * config/riscv/constraints.md: Implement constraints
> cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
> const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
Assuming this has gone through a testing cycle, this is fine for the trunk.
Thanks,
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
2024-01-09 18:43 ` Jeff Law
@ 2024-01-22 13:30 ` Mary Bennett
2024-03-19 3:34 ` Jeff Law
0 siblings, 1 reply; 32+ messages in thread
From: Mary Bennett @ 2024-01-22 13:30 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc-patches, Mary Bennett
[-- Attachment #1.1.1: Type: text/plain, Size: 1914 bytes --]
On 09/01/2024 18:43, Jeff Law wrote:
>
>
> On 1/8/24 06:14, Mary Bennett wrote:
>> Spec:
>> github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>>
>> Contributors:
>> Mary Bennett <mary.bennett@embecosm.com>
>> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>> Pietra Ferreira <pietra.ferreira@embecosm.com>
>> Charlie Keaney
>> Jessica Mills
>> Craig Blackmore <craig.blackmore@embecosm.com>
>> Simon Cook <simon.cook@embecosm.com>
>> Jeremy Bennett <jeremy.bennett@embecosm.com>
>> Helene Chelin <helene.chelin@embecosm.com>
>>
>> gcc/ChangeLog:
>> * common/config/riscv/riscv-common.cc: Create XCVbi extension
>> support.
>> * config/riscv/riscv.opt: Likewise.
>> * config/riscv/corev.md: Implement cv_branch<mode> pattern
>> for cv.beqimm and cv.bneimm.
>> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
>> branch instruction pattern.
>> * config/riscv/constraints.md: Implement constraints
>> cv_bi_s5 - signed 5-bit immediate.
>> * config/riscv/predicates.md: Implement predicate
>> const_int5s_operand - signed 5 bit immediate.
>> * doc/sourcebuild.texi: Add XCVbi documentation.
>>
>> gcc/testsuite/ChangeLog:
>> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>> * lib/target-supports.exp: Add proc for XCVbi.
> Assuming this has gone through a testing cycle, this is fine for the
> trunk.
>
> Thanks,
> jeff
This patch passes regression. Are there any other changes required
before it can be merged?
Kind regards,
Mary
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3203 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
2024-01-22 13:30 ` Mary Bennett
@ 2024-03-19 3:34 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2024-03-19 3:34 UTC (permalink / raw)
To: 623765fe-16e6-4065-81ba-6c3426e9388c; +Cc: gcc-patches, Mary Bennett
On 1/22/24 6:30 AM, Mary Bennett wrote:
>
> On 09/01/2024 18:43, Jeff Law wrote:
>>
>>
>> On 1/8/24 06:14, Mary Bennett wrote:
>>> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/
>>> corev-builtin-spec.md
>>>
>>> Contributors:
>>> Mary Bennett <mary.bennett@embecosm.com>
>>> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>>> Pietra Ferreira <pietra.ferreira@embecosm.com>
>>> Charlie Keaney
>>> Jessica Mills
>>> Craig Blackmore <craig.blackmore@embecosm.com>
>>> Simon Cook <simon.cook@embecosm.com>
>>> Jeremy Bennett <jeremy.bennett@embecosm.com>
>>> Helene Chelin <helene.chelin@embecosm.com>
>>>
>>> gcc/ChangeLog:
>>> * common/config/riscv/riscv-common.cc: Create XCVbi extension
>>> support.
>>> * config/riscv/riscv.opt: Likewise.
>>> * config/riscv/corev.md: Implement cv_branch<mode> pattern
>>> for cv.beqimm and cv.bneimm.
>>> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
>>> branch instruction pattern.
>>> * config/riscv/constraints.md: Implement constraints
>>> cv_bi_s5 - signed 5-bit immediate.
>>> * config/riscv/predicates.md: Implement predicate
>>> const_int5s_operand - signed 5 bit immediate.
>>> * doc/sourcebuild.texi: Add XCVbi documentation.
>>>
>>> gcc/testsuite/ChangeLog:
>>> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>>> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>>> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>>> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>>> * lib/target-supports.exp: Add proc for XCVbi.
>> Assuming this has gone through a testing cycle, this is fine for the
>> trunk.
>>
>> Thanks,
>> jeff
>
> This patch passes regression. Are there any other changes required
> before it can be merged?
I pushed this to the trunk. Sorry for the delays.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2024-03-19 3:34 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-09 17:11 ` Jeff Law
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-10 1:08 ` Jeff Law
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett
2024-03-19 3:34 ` Jeff Law
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