From: Jeff Law <jeffreyalaw@gmail.com>
To: "Christoph Müllner" <cmuellner@gcc.gnu.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>
Cc: gcc-patches@gcc.gnu.org, "Vineet Gupta" <vineetg@rivosinc.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
gnu-toolchain@rivosinc.com,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266]
Date: Fri, 14 Oct 2022 14:39:33 -0600 [thread overview]
Message-ID: <818c3a05-feec-4f0a-8268-48074af14ac6@gmail.com> (raw)
In-Reply-To: <CAHB2gtS1GofPUy6Lzs7CcS5sm282V79pYNwFFpF9jEOMotCNJA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
On 10/14/22 05:03, Christoph Müllner wrote:
>
> My guess is people like the ISA mapping (more) because it has been
> documented and reviewed.
> And it is the product of a working group that worked out the
> RVWMO specification.
> This gives some confidence that we don't need to rework it massively
> because of correctness issues in the future.
This stuff can be hard and if someone with deep experience in memory
models has reviewed the ISA mapping, then I'd prefer it over the GCC
mapping. It's just more likely the experts in the memory model space
are more likely to get it right than a bunch of compiler junkies, no
matter how smart we think we are :-)
Maybe I'm being too optimistic, but it's not hard for me to see a path
where GCC and LLVM both implement the ISA mapping by default. Anything
else is just a path of long term pain.
Jeff
next prev parent reply other threads:[~2022-10-14 20:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 19:36 Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 01/10] RISC-V: Simplify memory model code [PR 100265] Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 04/10] RISC-V: Use STORE instead of AMOSWAP for atomic stores " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 05/10] RISC-V: Emit fences according to chosen memory model " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 06/10] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 08/10] RISC-V: Add s.ext-consuming " Christoph Muellner
2021-05-05 19:36 ` [PATCH v2 09/10] RISC-V: Provide programmatic implementation of CAS " Christoph Muellner
2021-05-06 0:27 ` Jim Wilson
2021-05-05 19:36 ` [PATCH v2 10/10] RISC-V: Introduce predicate "riscv_sync_memory_operand" " Christoph Muellner
2022-10-11 19:06 ` [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Vineet Gupta
2022-10-11 19:31 ` Palmer Dabbelt
2022-10-11 20:46 ` Christoph Müllner
2022-10-11 23:31 ` Vineet Gupta
2022-10-12 0:15 ` Palmer Dabbelt
2022-10-12 8:03 ` Christoph Müllner
2022-10-13 23:11 ` Jeff Law
2022-10-12 17:16 ` Andrea Parri
2022-10-20 19:01 ` Andrea Parri
2022-10-29 5:02 ` Jeff Law
2022-10-13 23:04 ` Jeff Law
2022-10-13 22:39 ` Jeff Law
2022-10-13 23:14 ` Palmer Dabbelt
2022-10-14 11:03 ` Christoph Müllner
2022-10-14 20:39 ` Jeff Law [this message]
2022-10-14 21:57 ` Palmer Dabbelt
2022-10-15 0:31 ` Palmer Dabbelt
2022-10-14 0:14 ` Vineet Gupta
2022-10-11 23:14 ` Jeff Law
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