Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266]

[Palmer Dabbelt <palmer@dabbelt.com>]

On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
> Hi Christoph, Kito,
>
> On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
>> This series provides a cleanup of the current atomics implementation
>> of RISC-V:
>>
>> * PR100265: Use proper fences for atomic load/store
>> * PR100266: Provide programmatic implementation of CAS
>>
>> As both are very related, I merged the patches into one series.
>>
>> The first patch could be squashed into the following patches,
>> but I found it easier to understand the chances with it in place.
>>
>> The series has been tested as follows:
>> * Building and testing a multilib RV32/64 toolchain
>>    (bootstrapped with riscv-gnu-toolchain repo)
>> * Manual review of generated sequences for GCC's atomic builtins API
>>
>> The programmatic re-implementation of CAS benefits from a REE improvement
>> (see PR100264):
>>    https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html
>> If this patch is not in place, then an additional extension instruction
>> is emitted after the SC.W (in case of RV64 and CAS for uint32_t).
>>
>> Further, the new CAS code requires cbranch INSN helpers to be present:
>>    https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html
>
> I was wondering is this patchset is blocked on some technical grounds.

There's a v3 (though I can't find all of it, so not quite sure what 
happened), but IIUC that still has the same fundamental problems that 
all these have had: changing over to the new fence model may by an ABI 
break and the split CAS implementation doesn't ensure eventual success 
(see Jim's comments).  Not sure if there's other comments floating 
around, though, that's just what I remember.

+Andrea, in case he has time to look at the memory model / ABI issues.  

We'd still need to sort out the CAS issues, though, and it's not 
abundantly clear it's worth the work: we're essentailly constrained to 
just emitting those fixed CAS sequences due to the eventual success 
rules, so it's not clear what the benefit of splitting those up is.  
With WRS there are some routines we might want to generate code for 
(cond_read_acquire() in Linux, for example) but we'd really need to dig 
into those to see if it's even sane/fast.

There's another patch set to fix the lack of inline atomic routines 
without breaking stuff, there were some minor comments from Kito and 
IIRC I had some test failures that I needed to chase down as well.  
That's a much safer fix in the short term, we'll need to deal with this 
eventually but at least we can stop the libatomic issues for the distro 
folks.

>
> Thx,
> -Vineet
>
>> Changes for v2:
>> * Guard LL/SC sequence by compiler barriers ("blockage")
>>    (suggested by Andrew Waterman)
>> * Changed commit message for AMOSWAP->STORE change
>>    (suggested by Andrew Waterman)
>> * Extracted cbranch4 patch from patchset (suggested by Kito Cheng)
>> * Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson)
>> * Fix small code style issue
>>
>> Christoph Muellner (10):
>>    RISC-V: Simplify memory model code [PR 100265]
>>    RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265]
>>    RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265]
>>    RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265]
>>    RISC-V: Emit fences according to chosen memory model [PR 100265]
>>    RISC-V: Implement atomic_{load,store} [PR 100265]
>>    RISC-V: Model INSNs for LR and SC [PR 100266]
>>    RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266]
>>    RISC-V: Provide programmatic implementation of CAS [PR 100266]
>>    RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266]
>>
>>   gcc/config/riscv/riscv-protos.h |   1 +
>>   gcc/config/riscv/riscv.c        | 136 +++++++++++++-------
>>   gcc/config/riscv/sync.md        | 216 +++++++++++++++++++++-----------
>>   3 files changed, 235 insertions(+), 118 deletions(-)
>>