Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266]

[Vineet Gupta <vineetg@rivosinc.com>]

Hi Christoph, Kito,

On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
> This series provides a cleanup of the current atomics implementation
> of RISC-V:
>
> * PR100265: Use proper fences for atomic load/store
> * PR100266: Provide programmatic implementation of CAS
>
> As both are very related, I merged the patches into one series.
>
> The first patch could be squashed into the following patches,
> but I found it easier to understand the chances with it in place.
>
> The series has been tested as follows:
> * Building and testing a multilib RV32/64 toolchain
>    (bootstrapped with riscv-gnu-toolchain repo)
> * Manual review of generated sequences for GCC's atomic builtins API
>
> The programmatic re-implementation of CAS benefits from a REE improvement
> (see PR100264):
>    https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html
> If this patch is not in place, then an additional extension instruction
> is emitted after the SC.W (in case of RV64 and CAS for uint32_t).
>
> Further, the new CAS code requires cbranch INSN helpers to be present:
>    https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html

I was wondering is this patchset is blocked on some technical grounds.

Thx,
-Vineet

> Changes for v2:
> * Guard LL/SC sequence by compiler barriers ("blockage")
>    (suggested by Andrew Waterman)
> * Changed commit message for AMOSWAP->STORE change
>    (suggested by Andrew Waterman)
> * Extracted cbranch4 patch from patchset (suggested by Kito Cheng)
> * Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson)
> * Fix small code style issue
>
> Christoph Muellner (10):
>    RISC-V: Simplify memory model code [PR 100265]
>    RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265]
>    RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265]
>    RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265]
>    RISC-V: Emit fences according to chosen memory model [PR 100265]
>    RISC-V: Implement atomic_{load,store} [PR 100265]
>    RISC-V: Model INSNs for LR and SC [PR 100266]
>    RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266]
>    RISC-V: Provide programmatic implementation of CAS [PR 100266]
>    RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266]
>
>   gcc/config/riscv/riscv-protos.h |   1 +
>   gcc/config/riscv/riscv.c        | 136 +++++++++++++-------
>   gcc/config/riscv/sync.md        | 216 +++++++++++++++++++++-----------
>   3 files changed, 235 insertions(+), 118 deletions(-)
>