* [PATCH] RISC-V: Fix RVV testcases.
@ 2022-10-31 1:40 juzhe.zhong
2022-10-31 22:00 ` Jeff Law
0 siblings, 1 reply; 8+ messages in thread
From: juzhe.zhong @ 2022-10-31 1:40 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, schwab, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
* gcc.target/riscv/rvv/base/abi-3.c: Ditto.
* gcc.target/riscv/rvv/base/abi-4.c: Ditto.
* gcc.target/riscv/rvv/base/abi-5.c: Ditto.
* gcc.target/riscv/rvv/base/abi-6.c: Ditto.
* gcc.target/riscv/rvv/base/abi-7.c: Ditto.
* gcc.target/riscv/rvv/base/mov-1.c: Ditto.
* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
* gcc.target/riscv/rvv/base/mov-13.c: Ditto.
* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
* gcc.target/riscv/rvv/base/mov-7.c: Ditto.
* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
* gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
* gcc.target/riscv/rvv/base/user-1.c: Ditto.
* gcc.target/riscv/rvv/base/user-2.c: Ditto.
* gcc.target/riscv/rvv/base/user-3.c: Ditto.
* gcc.target/riscv/rvv/base/user-4.c: Ditto.
* gcc.target/riscv/rvv/base/user-5.c: Ditto.
* gcc.target/riscv/rvv/base/user-6.c: Ditto.
* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 8 ++++----
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 2 +-
27 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
index 92e61c255ac..9cd94c99308 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;} /* { dg-error {unknown type name '__rvv_bool32_t'} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
index b9adb3072f6..628a2753202 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
index 56a0ebed477..b4557aa6939 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
index af716094491..a58167f29ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
index e866c067e05..05b56e1cd28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
index 407756de183..cc35ba1c6cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e308f9..15e9c71f662 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa8297c30..e864554def6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb6b93..df5a36d0d68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40b62d..43a196a3e73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3bedb..23591aa8f7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd515747..90e67652056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db2735..dc3ca1f55cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b10b4..2d3744de66f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232ba867..13cc6699d6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73bb099..23b9da126de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0adfb..e87de71c677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05899d..1ea447b07bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c0f4d..7ed10bc5833 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
@@ -7,12 +7,12 @@
/* Test tieable of RVV types with same LMUL. */
/*
** mov1:
+** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
** vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2
** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2
** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** ret
*/
@@ -28,10 +28,10 @@ void mov1 (int8_t *in, int8_t *out, int M)
/*
** mov2:
+** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
** vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** ret
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
index 3d81b179235..b271b0a1f3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
@@ -1,4 +1,4 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */
#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' extension enabled} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
index 00fb73f220f..63eea3fe901 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
index 92f4ee02d20..59ffe1062de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
index 3a425721863..86105e80d3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
index 76c5e607137..c854e3f8d92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
index de850e5e10d..f2b24733e57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
index 1d79b6b8eac..2c2c1ca3636 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9170e..87698f306bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <stddef.h>
#include <riscv_vector.h>
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] RISC-V: Fix RVV testcases.
2022-10-31 1:40 [PATCH] RISC-V: Fix RVV testcases juzhe.zhong
@ 2022-10-31 22:00 ` Jeff Law
2022-10-31 22:25 ` 钟居哲
2022-10-31 22:30 ` Palmer Dabbelt
0 siblings, 2 replies; 8+ messages in thread
From: Jeff Law @ 2022-10-31 22:00 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: schwab, kito.cheng
On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
I'm pretty new to the RISC-V world, but don't some of the cases
(particularly the abi-* tests) verify that the ABI specification does
not override the arch specification WRT availability of types?
Jeff
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV testcases.
2022-10-31 22:00 ` Jeff Law
@ 2022-10-31 22:25 ` 钟居哲
2022-10-31 22:30 ` Palmer Dabbelt
1 sibling, 0 replies; 8+ messages in thread
From: 钟居哲 @ 2022-10-31 22:25 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: Andreas Schwab, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 2270 bytes --]
These testcases are not depend on the ABI specification.
I pick up the minimum ABI setting so that it won't fail.
The naming of abi-* tests may be confusing, I can change the naming in the next time.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2022-11-01 06:00
To: juzhe.zhong; gcc-patches
CC: schwab; kito.cheng
Subject: Re: [PATCH] RISC-V: Fix RVV testcases.
On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
I'm pretty new to the RISC-V world, but don't some of the cases
(particularly the abi-* tests) verify that the ABI specification does
not override the arch specification WRT availability of types?
Jeff
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] RISC-V: Fix RVV testcases.
2022-10-31 22:00 ` Jeff Law
2022-10-31 22:25 ` 钟居哲
@ 2022-10-31 22:30 ` Palmer Dabbelt
2022-10-31 23:52 ` 钟居哲
1 sibling, 1 reply; 8+ messages in thread
From: Palmer Dabbelt @ 2022-10-31 22:30 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, gcc-patches, schwab, Kito Cheng
On Mon, 31 Oct 2022 15:00:49 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
> On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
>> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
>> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
>> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
>
> I'm pretty new to the RISC-V world, but don't some of the cases
> (particularly the abi-* tests) verify that the ABI specification does
> not override the arch specification WRT availability of types?
I think that depends on what the ABI specification says here, as it
could really go many ways. Most of the RISC-V targets just use -mabi to
control how arguments end up passed in functions, not the availability
of types. I can't find the ABI spec for these, though, so I'm not
entirely sure how they're supposed to work...
That said, I'm not sure why we need any of these -mabi changes? Just
from spot checking some of the examples it doesn't look like there
should be any functional difference between ilp32 and ilp32d here:
-march is always specified so ilp32d looks valid. If this is just to
fix the "fails on targets without ilp32d" [1], then IMO it's not really
a fix: we're essentially just changing that to "fails on targets without
ilp32", we either need some sort of automatic march/mabi setting or a
dependency on the availiable multilibs. Some of these can probably
avoid linking, but we'll have execution tests at some point.
1: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604644.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV testcases.
2022-10-31 22:30 ` Palmer Dabbelt
@ 2022-10-31 23:52 ` 钟居哲
2022-11-01 18:35 ` Palmer Dabbelt
0 siblings, 1 reply; 8+ messages in thread
From: 钟居哲 @ 2022-10-31 23:52 UTC (permalink / raw)
To: palmer, gcc-patches; +Cc: gcc-patches, Andreas Schwab, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3663 bytes --]
These cases actually doesn't care about -mabi, they just need 'v' in -march.
Can you tell me how to fix these testcases for "fails on targets without ilp32d" ?
These failures are bogus failures since if you specify -mabi=ilp32d when you are using GNU toolchain which is build up with "--arch=ilp32" let say.
It will fail. Report there is no "ilp32d". So I fix these testcase by replacing "ilp32d" into "ilp32".
Thank you.
juzhe.zhong@rivai.ai
From: Palmer Dabbelt
Date: 2022-11-01 06:30
To: gcc-patches
CC: juzhe.zhong; gcc-patches; schwab; Kito Cheng
Subject: Re: [PATCH] RISC-V: Fix RVV testcases.
On Mon, 31 Oct 2022 15:00:49 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
> On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
>> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
>> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
>> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
>> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
>> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
>> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
>
> I'm pretty new to the RISC-V world, but don't some of the cases
> (particularly the abi-* tests) verify that the ABI specification does
> not override the arch specification WRT availability of types?
I think that depends on what the ABI specification says here, as it
could really go many ways. Most of the RISC-V targets just use -mabi to
control how arguments end up passed in functions, not the availability
of types. I can't find the ABI spec for these, though, so I'm not
entirely sure how they're supposed to work...
That said, I'm not sure why we need any of these -mabi changes? Just
from spot checking some of the examples it doesn't look like there
should be any functional difference between ilp32 and ilp32d here:
-march is always specified so ilp32d looks valid. If this is just to
fix the "fails on targets without ilp32d" [1], then IMO it's not really
a fix: we're essentially just changing that to "fails on targets without
ilp32", we either need some sort of automatic march/mabi setting or a
dependency on the availiable multilibs. Some of these can probably
avoid linking, but we'll have execution tests at some point.
1: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604644.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV testcases.
2022-10-31 23:52 ` 钟居哲
@ 2022-11-01 18:35 ` Palmer Dabbelt
2022-11-06 0:13 ` Kito Cheng
0 siblings, 1 reply; 8+ messages in thread
From: Palmer Dabbelt @ 2022-11-01 18:35 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, schwab, gcc-patches, Kito Cheng
On Mon, 31 Oct 2022 16:52:25 PDT (-0700), juzhe.zhong@rivai.ai wrote:
> These cases actually doesn't care about -mabi, they just need 'v' in -march.
> Can you tell me how to fix these testcases for "fails on targets without ilp32d" ?
> These failures are bogus failures since if you specify -mabi=ilp32d when you are using GNU toolchain which is build up with "--arch=ilp32" let say.
> It will fail. Report there is no "ilp32d". So I fix these testcase by replacing "ilp32d" into "ilp32".
So the problem is this just moves the failures around, rather than
failing on toolchains that lack ilp32d support it'll fail on toolchains
that lack ilp32 support. The ABI naming scheme sort of makes them look
like extensions, but they're just incompatible with each other.
I can see a handful of ways to fix this:
* Add some sort of automatic ABI scheme to GCC. LLVM already does this
and there was a GCC patch for it that had some issues, but IMO having
something like -mabi=auto-{min,max} would be useful as users keep
running into this problem. We could also add something to DejaGNU
that does this.
* Add some sort of -march=+v to GCC, along the lines of the .option
arch,+v stuff in assembly but from the command line. I seem to
remember proposals for that floating around somewhere, but can't find
anything. This could probably also to DejaGNU.
* Decorate all these V functions with the +arch attributes. That
wouldn't require any compiler changes, but it's kind of clunky.
* Add some sort of test suite logic (maybe in DejaGNU?) to check and see
if the desired ABI is linkable before attempting to do so. That might
be generically useful.
> Thank you.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Palmer Dabbelt
> Date: 2022-11-01 06:30
> To: gcc-patches
> CC: juzhe.zhong; gcc-patches; schwab; Kito Cheng
> Subject: Re: [PATCH] RISC-V: Fix RVV testcases.
> On Mon, 31 Oct 2022 15:00:49 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>>
>> On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
>>> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
>>> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
>>> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
>>> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
>>> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
>>> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
>>> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
>>> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
>>> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
>>> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
>>
>> I'm pretty new to the RISC-V world, but don't some of the cases
>> (particularly the abi-* tests) verify that the ABI specification does
>> not override the arch specification WRT availability of types?
>
> I think that depends on what the ABI specification says here, as it
> could really go many ways. Most of the RISC-V targets just use -mabi to
> control how arguments end up passed in functions, not the availability
> of types. I can't find the ABI spec for these, though, so I'm not
> entirely sure how they're supposed to work...
>
> That said, I'm not sure why we need any of these -mabi changes? Just
> from spot checking some of the examples it doesn't look like there
> should be any functional difference between ilp32 and ilp32d here:
> -march is always specified so ilp32d looks valid. If this is just to
> fix the "fails on targets without ilp32d" [1], then IMO it's not really
> a fix: we're essentially just changing that to "fails on targets without
> ilp32", we either need some sort of automatic march/mabi setting or a
> dependency on the availiable multilibs. Some of these can probably
> avoid linking, but we'll have execution tests at some point.
>
> 1: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604644.html
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV testcases.
2022-11-01 18:35 ` Palmer Dabbelt
@ 2022-11-06 0:13 ` Kito Cheng
2022-11-18 20:07 ` Jeff Law
0 siblings, 1 reply; 8+ messages in thread
From: Kito Cheng @ 2022-11-06 0:13 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: juzhe.zhong, schwab, gcc-patches
Alternative fix for those testcase has posted:
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605126.html
On Tue, Nov 1, 2022 at 11:36 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Mon, 31 Oct 2022 16:52:25 PDT (-0700), juzhe.zhong@rivai.ai wrote:
> > These cases actually doesn't care about -mabi, they just need 'v' in -march.
> > Can you tell me how to fix these testcases for "fails on targets without ilp32d" ?
> > These failures are bogus failures since if you specify -mabi=ilp32d when you are using GNU toolchain which is build up with "--arch=ilp32" let say.
> > It will fail. Report there is no "ilp32d". So I fix these testcase by replacing "ilp32d" into "ilp32".
>
> So the problem is this just moves the failures around, rather than
> failing on toolchains that lack ilp32d support it'll fail on toolchains
> that lack ilp32 support. The ABI naming scheme sort of makes them look
> like extensions, but they're just incompatible with each other.
>
> I can see a handful of ways to fix this:
>
> * Add some sort of automatic ABI scheme to GCC. LLVM already does this
> and there was a GCC patch for it that had some issues, but IMO having
> something like -mabi=auto-{min,max} would be useful as users keep
> running into this problem. We could also add something to DejaGNU
> that does this.
> * Add some sort of -march=+v to GCC, along the lines of the .option
> arch,+v stuff in assembly but from the command line. I seem to
> remember proposals for that floating around somewhere, but can't find
> anything. This could probably also to DejaGNU.
> * Decorate all these V functions with the +arch attributes. That
> wouldn't require any compiler changes, but it's kind of clunky.
> * Add some sort of test suite logic (maybe in DejaGNU?) to check and see
> if the desired ABI is linkable before attempting to do so. That might
> be generically useful.
>
> > Thank you.
> >
> >
> >
> > juzhe.zhong@rivai.ai
> >
> > From: Palmer Dabbelt
> > Date: 2022-11-01 06:30
> > To: gcc-patches
> > CC: juzhe.zhong; gcc-patches; schwab; Kito Cheng
> > Subject: Re: [PATCH] RISC-V: Fix RVV testcases.
> > On Mon, 31 Oct 2022 15:00:49 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> >>
> >> On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
> >>> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >>>
> >>> gcc/testsuite/ChangeLog:
> >>>
> >>> * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
> >>> * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-1.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-2.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-3.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-4.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-5.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/user-6.c: Ditto.
> >>> * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
> >>
> >> I'm pretty new to the RISC-V world, but don't some of the cases
> >> (particularly the abi-* tests) verify that the ABI specification does
> >> not override the arch specification WRT availability of types?
> >
> > I think that depends on what the ABI specification says here, as it
> > could really go many ways. Most of the RISC-V targets just use -mabi to
> > control how arguments end up passed in functions, not the availability
> > of types. I can't find the ABI spec for these, though, so I'm not
> > entirely sure how they're supposed to work...
> >
> > That said, I'm not sure why we need any of these -mabi changes? Just
> > from spot checking some of the examples it doesn't look like there
> > should be any functional difference between ilp32 and ilp32d here:
> > -march is always specified so ilp32d looks valid. If this is just to
> > fix the "fails on targets without ilp32d" [1], then IMO it's not really
> > a fix: we're essentially just changing that to "fails on targets without
> > ilp32", we either need some sort of automatic march/mabi setting or a
> > dependency on the availiable multilibs. Some of these can probably
> > avoid linking, but we'll have execution tests at some point.
> >
> > 1: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604644.html
> >
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] RISC-V: Fix RVV testcases.
2022-11-06 0:13 ` Kito Cheng
@ 2022-11-18 20:07 ` Jeff Law
0 siblings, 0 replies; 8+ messages in thread
From: Jeff Law @ 2022-11-18 20:07 UTC (permalink / raw)
To: Kito Cheng, Palmer Dabbelt; +Cc: gcc-patches, schwab, juzhe.zhong
On 11/5/22 18:13, Kito Cheng via Gcc-patches wrote:
> Alternative fix for those testcase has posted:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605126.html
Did this ever get addressed, in either form?
jeff
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-11-18 20:07 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-31 1:40 [PATCH] RISC-V: Fix RVV testcases juzhe.zhong
2022-10-31 22:00 ` Jeff Law
2022-10-31 22:25 ` 钟居哲
2022-10-31 22:30 ` Palmer Dabbelt
2022-10-31 23:52 ` 钟居哲
2022-11-01 18:35 ` Palmer Dabbelt
2022-11-06 0:13 ` Kito Cheng
2022-11-18 20:07 ` Jeff Law
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