* [PATCH] minimal support for xtheadv
@ 2023-11-08 13:12 chenyixuan
2023-11-09 7:39 ` Kito Cheng
0 siblings, 1 reply; 6+ messages in thread
From: chenyixuan @ 2023-11-08 13:12 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, shiyulong, oriachiuan, shihua, jiawei
From: XYenChi <oriachiuan@gmail.com>
This patch is for support xtheadv.
gcc/ChangeLog:
2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn>
* common/config/riscv/riscv-common.cc: Add xthead minimal support.
gcc/config/ChangeLog:
2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn>
* riscv/riscv.opt: Add xthead minimal support.
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/riscv.opt | 2 ++
2 files changed, 4 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..d5ea0ee9b70 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -325,6 +325,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xtheadv", ISA_SPEC_CLASS_NONE, 0, 7},
{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xtheadv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV},
{"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..2bbdf680fa2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
Mask(XTHEADSYNC) Var(riscv_xthead_subext)
+Mask(XTHEADV) Var(riscv_xthead_subext)
+
TargetVariable
int riscv_xventana_subext
--
2.42.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] minimal support for xtheadv 2023-11-08 13:12 [PATCH] minimal support for xtheadv chenyixuan @ 2023-11-09 7:39 ` Kito Cheng 2023-11-09 8:05 ` Christoph Müllner 0 siblings, 1 reply; 6+ messages in thread From: Kito Cheng @ 2023-11-09 7:39 UTC (permalink / raw) To: chenyixuan Cc: gcc-patches, shiyulong, oriachiuan, shihua, jiawei, Christoph Müllner, Jojo R Hi Yi Xuan: This patch is trivial, and generally LGTM, but I would require putting the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions before merging this, also don't forget include "RISC-V:" in the title, it would be easier to track during the RISC-V GCC sync meeting :) And I am a little bit confused by the author's info? is it from you or "XYenChi <oriachiuan@gmail.com>"? or oriachiuan@gmail.com is also your mail address? cc Christoph since I believe you may know more about that process. cc JoJo since you are T-head folk :P On Wed, Nov 8, 2023 at 9:13 PM <chenyixuan@iscas.ac.cn> wrote: > > From: XYenChi <oriachiuan@gmail.com> > > This patch is for support xtheadv. > > gcc/ChangeLog: > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > * common/config/riscv/riscv-common.cc: Add xthead minimal support. > > gcc/config/ChangeLog: > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > * riscv/riscv.opt: Add xthead minimal support. > --- > gcc/common/config/riscv/riscv-common.cc | 2 ++ > gcc/config/riscv/riscv.opt | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index 526dbb7603b..d5ea0ee9b70 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -325,6 +325,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadv", ISA_SPEC_CLASS_NONE, 0, 7}, > > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, > + {"xtheadv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV}, > > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 70d78151cee..2bbdf680fa2 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) > > Mask(XTHEADSYNC) Var(riscv_xthead_subext) > > +Mask(XTHEADV) Var(riscv_xthead_subext) > + > TargetVariable > int riscv_xventana_subext > > -- > 2.42.0 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] minimal support for xtheadv 2023-11-09 7:39 ` Kito Cheng @ 2023-11-09 8:05 ` Christoph Müllner 2023-11-09 8:38 ` Yixuan Chen 0 siblings, 1 reply; 6+ messages in thread From: Christoph Müllner @ 2023-11-09 8:05 UTC (permalink / raw) To: Kito Cheng Cc: chenyixuan, gcc-patches, shiyulong, oriachiuan, shihua, jiawei, Jojo R, Philipp Tomsich, Cooper Qu On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng <kito.cheng@gmail.com> wrote: > > Hi Yi Xuan: > > This patch is trivial, and generally LGTM, but I would require putting > the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions > before merging this, also don't forget include "RISC-V:" in the title, > it would be easier to track during the RISC-V GCC sync meeting :) > > And I am a little bit confused by the author's info? is it from you or > "XYenChi <oriachiuan@gmail.com>"? or oriachiuan@gmail.com is also your > mail address? > > cc Christoph since I believe you may know more about that process. > cc JoJo since you are T-head folk :P Hi Yi Xuan and Kito, I was not aware that CAS is working on getting T-Head's Vector extension supported. My biggest concern with this patch is that "XTheadV" does not have a specification. T-Head and VRULL are currently working on support patches for T-Head's Vector extension implementation. We've named the extension XTheadVector. Supporting XTheadVector means to address a range of issues (e.g. defining a formal ISA vendor extension specification, extension discovery, addressing implementation details, differences among available cores, intrinsics, ...). We've already made good progress on that and expect to publish first results soon. BR Christoph > > > On Wed, Nov 8, 2023 at 9:13 PM <chenyixuan@iscas.ac.cn> wrote: > > > > From: XYenChi <oriachiuan@gmail.com> > > > > This patch is for support xtheadv. > > > > gcc/ChangeLog: > > > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > > > * common/config/riscv/riscv-common.cc: Add xthead minimal support. > > > > gcc/config/ChangeLog: > > > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > > > * riscv/riscv.opt: Add xthead minimal support. > > --- > > gcc/common/config/riscv/riscv-common.cc | 2 ++ > > gcc/config/riscv/riscv.opt | 2 ++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > > index 526dbb7603b..d5ea0ee9b70 100644 > > --- a/gcc/common/config/riscv/riscv-common.cc > > +++ b/gcc/common/config/riscv/riscv-common.cc > > @@ -325,6 +325,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"xtheadv", ISA_SPEC_CLASS_NONE, 0, 7}, > > > > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > > > > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, > > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, > > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, > > + {"xtheadv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV}, > > > > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, > > > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > > index 70d78151cee..2bbdf680fa2 100644 > > --- a/gcc/config/riscv/riscv.opt > > +++ b/gcc/config/riscv/riscv.opt > > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) > > > > Mask(XTHEADSYNC) Var(riscv_xthead_subext) > > > > +Mask(XTHEADV) Var(riscv_xthead_subext) > > + > > TargetVariable > > int riscv_xventana_subext > > > > -- > > 2.42.0 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] minimal support for xtheadv 2023-11-09 8:05 ` Christoph Müllner @ 2023-11-09 8:38 ` Yixuan Chen 2023-11-09 16:04 ` Jeff Law 0 siblings, 1 reply; 6+ messages in thread From: Yixuan Chen @ 2023-11-09 8:38 UTC (permalink / raw) To: Christoph Müllner Cc: Kito Cheng, chenyixuan, gcc-patches, shiyulong, shihua, jiawei, Jojo R, Philipp Tomsich, Cooper Qu [-- Attachment #1: Type: text/plain, Size: 4500 bytes --] Hi Kito and Christoph, XYenChi (oriachiaun@gmail.com) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so port the XTheadV. If T-Head and VRULL have made great progress, it's pleasure to follow your work. By the way, I have sent the opcode patch to binutils, if you have any concern, please check the patch: https://sourceware.org/pipermail/binutils/2023-November/130431.html If our team could provide any help, please let us know. Best regards Yixuan Christoph Müllner <christoph.muellner@vrull.eu> 于2023年11月9日周四 16:06写道： > On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng <kito.cheng@gmail.com> wrote: > > > > Hi Yi Xuan: > > > > This patch is trivial, and generally LGTM, but I would require putting > > the spec into > https://github.com/riscv-non-isa/riscv-toolchain-conventions > > before merging this, also don't forget include "RISC-V:" in the title, > > it would be easier to track during the RISC-V GCC sync meeting :) > > > > And I am a little bit confused by the author's info? is it from you or > > "XYenChi <oriachiuan@gmail.com>"? or oriachiuan@gmail.com is also your > > mail address? > > > > cc Christoph since I believe you may know more about that process. > > cc JoJo since you are T-head folk :P > > Hi Yi Xuan and Kito, > > I was not aware that CAS is working on getting T-Head's Vector > extension supported. > My biggest concern with this patch is that "XTheadV" does not have a > specification. > > T-Head and VRULL are currently working on support patches for T-Head's > Vector extension > implementation. We've named the extension XTheadVector. > Supporting XTheadVector means to address a range of issues (e.g. > defining a formal ISA > vendor extension specification, extension discovery, addressing > implementation details, > differences among available cores, intrinsics, ...). > We've already made good progress on that and expect to publish first > results soon. > > BR > Christoph > > > > > > > On Wed, Nov 8, 2023 at 9:13 PM <chenyixuan@iscas.ac.cn> wrote: > > > > > > From: XYenChi <oriachiuan@gmail.com> > > > > > > This patch is for support xtheadv. > > > > > > gcc/ChangeLog: > > > > > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > > > > > * common/config/riscv/riscv-common.cc: Add xthead minimal > support. > > > > > > gcc/config/ChangeLog: > > > > > > 2023-11-08 Chen Yixuan <chenyixuan@iscas.an.cn> > > > > > > * riscv/riscv.opt: Add xthead minimal support. > > > --- > > > gcc/common/config/riscv/riscv-common.cc | 2 ++ > > > gcc/config/riscv/riscv.opt | 2 ++ > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > > > index 526dbb7603b..d5ea0ee9b70 100644 > > > --- a/gcc/common/config/riscv/riscv-common.cc > > > +++ b/gcc/common/config/riscv/riscv-common.cc > > > @@ -325,6 +325,7 @@ static const struct riscv_ext_version > riscv_ext_version_table[] = > > > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > > > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > > > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > > > + {"xtheadv", ISA_SPEC_CLASS_NONE, 0, 7}, > > > > > > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > > > > > > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t > riscv_ext_flag_table[] = > > > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, > MASK_XTHEADMEMIDX}, > > > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, > MASK_XTHEADMEMPAIR}, > > > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, > MASK_XTHEADSYNC}, > > > + {"xtheadv", &gcc_options::x_riscv_xthead_subext, > MASK_XTHEADV}, > > > > > > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, > MASK_XVENTANACONDOPS}, > > > > > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > > > index 70d78151cee..2bbdf680fa2 100644 > > > --- a/gcc/config/riscv/riscv.opt > > > +++ b/gcc/config/riscv/riscv.opt > > > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) > > > > > > Mask(XTHEADSYNC) Var(riscv_xthead_subext) > > > > > > +Mask(XTHEADV) Var(riscv_xthead_subext) > > > + > > > TargetVariable > > > int riscv_xventana_subext > > > > > > -- > > > 2.42.0 > > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] minimal support for xtheadv 2023-11-09 8:38 ` Yixuan Chen @ 2023-11-09 16:04 ` Jeff Law 2023-11-09 16:22 ` Kito Cheng 0 siblings, 1 reply; 6+ messages in thread From: Jeff Law @ 2023-11-09 16:04 UTC (permalink / raw) To: Yixuan Chen, Christoph Müllner Cc: Kito Cheng, chenyixuan, gcc-patches, shiyulong, shihua, jiawei, Jojo R, Philipp Tomsich, Cooper Qu On 11/9/23 01:38, Yixuan Chen wrote: > Hi Kito and Christoph, > > XYenChi (oriachiaun@gmail.com <mailto:oriachiaun@gmail.com>) is my > e-mail address too. I didn't notice the git email config have changed, > very sorry about that. > > We want to support other operate system project from our team, so port > the XTheadV. If T-Head and VRULL have made great progress, it's pleasure > to follow your work. By the way, I have sent the opcode patch to > binutils, if you have any concern, please check the patch: > https://sourceware.org/pipermail/binutils/2023-November/130431.html > <https://sourceware.org/pipermail/binutils/2023-November/130431.html> > > If our team could provide any help, please let us know. Given we see multiple organizations with an interest in this work, but that the bulk of the work can't be integrated in the short term, y'all might consider a shared development branch for coordination. That gives the two organizations a place to coordinate their work while things like the ISA spec and such get solidified. Presumably the goal for the main body of work is not gcc-14, but gcc-15. I don't want to dictate how coordination happens. Ultimately it's something the relevant developers can decide. jeff ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] minimal support for xtheadv 2023-11-09 16:04 ` Jeff Law @ 2023-11-09 16:22 ` Kito Cheng 0 siblings, 0 replies; 6+ messages in thread From: Kito Cheng @ 2023-11-09 16:22 UTC (permalink / raw) To: Jeff Law Cc: Yixuan Chen, Christoph Müllner, chenyixuan, gcc-patches, shiyulong, shihua, jiawei, Jojo R, Philipp Tomsich, Cooper Qu Give a few more thought behind my first LGTM: I am OK *IF* binutils bits accepted since it's just kind of bypassing the -march to bintuils to enable those instructions for assembly code. However the situation seems is little more complicated than my expect at beginning...:P Anyway, I still think it's fine to accept that to me *IF* bintuils part has landed, but only limited to -march support, no further things for GCC 14 like intrinsic and auto vectorizer stuff for t-head vector (or vector 0.7). On Fri, Nov 10, 2023 at 12:05 AM Jeff Law <jeffreyalaw@gmail.com> wrote: > > > > On 11/9/23 01:38, Yixuan Chen wrote: > > Hi Kito and Christoph, > > > > XYenChi (oriachiaun@gmail.com <mailto:oriachiaun@gmail.com>) is my > > e-mail address too. I didn't notice the git email config have changed, > > very sorry about that. > > > > We want to support other operate system project from our team, so port > > the XTheadV. If T-Head and VRULL have made great progress, it's pleasure > > to follow your work. By the way, I have sent the opcode patch to > > binutils, if you have any concern, please check the patch: > > https://sourceware.org/pipermail/binutils/2023-November/130431.html > > <https://sourceware.org/pipermail/binutils/2023-November/130431.html> > > > > If our team could provide any help, please let us know. > Given we see multiple organizations with an interest in this work, but > that the bulk of the work can't be integrated in the short term, y'all > might consider a shared development branch for coordination. > > That gives the two organizations a place to coordinate their work while > things like the ISA spec and such get solidified. Presumably the goal > for the main body of work is not gcc-14, but gcc-15. > > I don't want to dictate how coordination happens. Ultimately it's > something the relevant developers can decide. > > jeff ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-11-09 16:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-11-08 13:12 [PATCH] minimal support for xtheadv chenyixuan 2023-11-09 7:39 ` Kito Cheng 2023-11-09 8:05 ` Christoph Müllner 2023-11-09 8:38 ` Yixuan Chen 2023-11-09 16:04 ` Jeff Law 2023-11-09 16:22 ` Kito Cheng
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