* [RFC] Intel AVX10.1 Compiler Design and Support
@ 2023-11-10 1:41 Haochen Jiang
2023-11-10 1:41 ` [PATCH] Initial support for AVX10.1 Haochen Jiang
2023-11-10 10:15 ` [RFC] Intel AVX10.1 Compiler Design and Support Richard Biener
0 siblings, 2 replies; 11+ messages in thread
From: Haochen Jiang @ 2023-11-10 1:41 UTC (permalink / raw)
To: gcc-patches; +Cc: hongtao.liu, ubizjak
Hi all,
This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
support, it makes a lot easier to add them comparing to the August version.
Detail for AVX10 is shown below:
Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
It describes the Intel Advanced Vector Extensions 10 Instruction Set
Architecture.
https://cdrdv2.intel.com/v1/dl/getContent/784267
The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
It provides introductory information regarding the converged vector ISA: Intel
Advanced Vector Extensions 10.
https://cdrdv2.intel.com/v1/dl/getContent/784343
Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
anything at first. At the end of the option handling, we will check whether
the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.
It means that AVX10 options will be separated from the existing AVX512 and the
newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
(enable/disable/set vector size) the AVX512 features underneath independently.
If there’s potential overlap or conflict between AVX10 and AVX512 options,
some rules are provided to define the behavior, which will be described below.
avx10.1 option will be provided as an alias of avx10.1-256.
In the future, the AVX10 options will imply like this:
AVX10.1-256 <---- AVX10.1-512
^ ^
| |
AVX10.2-256 <---- AVX10.2-512
^ ^
| |
AVX10.3-256 <---- AVX10.3-512
^ ^
| |
Each of them will have its own option to enable/disabled corresponding
features. The alias avx10.x will also be provided.
As mentioned in August version RFC, since we lean towards the adoption of
AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
AVX10 and legacy AVX512 options. However, we would like to introduce some
simple rules for user when it comes to combination.
1. Enabling AVX10 and AVX512 at the same command line with different vector
size will lead to a warning message. The behavior of the compiler will be
enabling AVX10 with longer, i.e., 512 bit vector size.
If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
-mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.
2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
impact the vector size, and vice versa. The compiler will emit warnings if
necessary.
For the auto dispatch support including function multi versioning, function
attribute usage, the behavior will be identical to compiler options.
If you have any questions, feel free to ask in this thread.
Thx,
Haochen
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] Initial support for AVX10.1
2023-11-10 1:41 [RFC] Intel AVX10.1 Compiler Design and Support Haochen Jiang
@ 2023-11-10 1:41 ` Haochen Jiang
2023-11-20 6:34 ` Hongtao Liu
2023-11-10 10:15 ` [RFC] Intel AVX10.1 Compiler Design and Support Richard Biener
1 sibling, 1 reply; 11+ messages in thread
From: Haochen Jiang @ 2023-11-10 1:41 UTC (permalink / raw)
To: gcc-patches; +Cc: hongtao.liu, ubizjak
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Add avx10_set and version and detect avx10.1.
(cpu_indicator_init): Handle avx10.1-512.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_256_SET): New.
(OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
(ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
Add indicator for explicit no-avx512 and no-avx10.1 options.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
AVX10_1_256 and AVX10_1_512.
* config/i386/cpuid.h (bit_AVX10): New.
(bit_AVX10_256): Ditto.
(bit_AVX10_512): Ditto.
* config/i386/driver-i386.cc (check_avx10_avx512_features): New.
(host_detect_local_cpu): Do not append "-mno-" options under
specific scenarios to avoid emitting a warning.
* config/i386/i386-isa.def
(EVEX512): Add DEF_PTA(EVEX512).
(AVX10_1_256): Add DEF_PTA(AVX10_1_256).
(AVX10_1_512): Add DEF_PTA(AVX10_1_512).
* config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
-mavx10.1-512.
(ix86_function_specific_save): Save explicit no indicator.
(ix86_function_specific_restore): Restore explicit no indicator.
(ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
avx10.1-512.
(ix86_valid_target_attribute_tree): Handle avx512 function
attributes with avx10.1 command line option.
(ix86_option_override_internal): Handle AVX10.1 options.
* config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
machines.
* config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
-mavx10.1-512.
* doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
* doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
* doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
and avx10.1-512.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_1-1.c: New test.
* gcc.target/i386/avx10_1-10.c: Ditto.
* gcc.target/i386/avx10_1-11.c: Ditto.
* gcc.target/i386/avx10_1-12.c: Ditto.
* gcc.target/i386/avx10_1-13.c: Ditto.
* gcc.target/i386/avx10_1-14.c: Ditto.
* gcc.target/i386/avx10_1-15.c: Ditto.
* gcc.target/i386/avx10_1-16.c: Ditto.
* gcc.target/i386/avx10_1-17.c: Ditto.
* gcc.target/i386/avx10_1-18.c: Ditto.
* gcc.target/i386/avx10_1-19.c: Ditto.
* gcc.target/i386/avx10_1-2.c: Ditto.
* gcc.target/i386/avx10_1-20.c: Ditto.
* gcc.target/i386/avx10_1-21.c: Ditto.
* gcc.target/i386/avx10_1-22.c: Ditto.
* gcc.target/i386/avx10_1-23.c: Ditto.
* gcc.target/i386/avx10_1-3.c: Ditto.
* gcc.target/i386/avx10_1-4.c: Ditto.
* gcc.target/i386/avx10_1-5.c: Ditto.
* gcc.target/i386/avx10_1-6.c: Ditto.
* gcc.target/i386/avx10_1-7.c: Ditto.
* gcc.target/i386/avx10_1-8.c: Ditto.
* gcc.target/i386/avx10_1-9.c: Ditto.
---
gcc/common/config/i386/cpuinfo.h | 33 ++++++
gcc/common/config/i386/i386-common.cc | 55 ++++++++-
gcc/common/config/i386/i386-cpuinfo.h | 2 +
gcc/common/config/i386/i386-isas.h | 3 +
gcc/config/i386/cpuid.h | 5 +
gcc/config/i386/driver-i386.cc | 43 ++++++-
gcc/config/i386/i386-isa.def | 3 +
gcc/config/i386/i386-options.cc | 132 +++++++++++++++++++--
gcc/config/i386/i386.h | 2 +-
gcc/config/i386/i386.opt | 30 +++++
gcc/doc/extend.texi | 15 +++
gcc/doc/invoke.texi | 17 ++-
gcc/doc/sourcebuild.texi | 9 ++
gcc/testsuite/gcc.target/i386/avx10_1-1.c | 22 ++++
gcc/testsuite/gcc.target/i386/avx10_1-10.c | 6 +
gcc/testsuite/gcc.target/i386/avx10_1-11.c | 6 +
gcc/testsuite/gcc.target/i386/avx10_1-12.c | 6 +
gcc/testsuite/gcc.target/i386/avx10_1-13.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-14.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-15.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-16.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-17.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-18.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-19.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-2.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-20.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-21.c | 6 +
gcc/testsuite/gcc.target/i386/avx10_1-22.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-23.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-3.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-4.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-5.c | 5 +
gcc/testsuite/gcc.target/i386/avx10_1-6.c | 13 ++
gcc/testsuite/gcc.target/i386/avx10_1-7.c | 5 +
gcc/testsuite/gcc.target/i386/avx10_1-8.c | 4 +
gcc/testsuite/gcc.target/i386/avx10_1-9.c | 6 +
36 files changed, 579 insertions(+), 18 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-10.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-11.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-12.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-13.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-14.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-15.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-16.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-17.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-18.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-19.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-20.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-21.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-22.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-23.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-7.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-8.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-9.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 7d25479eb89..f90fb4d56a2 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -715,6 +715,9 @@ get_available_features (struct __processor_model *cpu_model,
int apx_usable = 0;
/* Check if KL is usable. */
int has_kl = 0;
+ /* Record AVX10 version. */
+ int avx10_set = 0;
+ int version = 0;
if ((ecx & bit_OSXSAVE))
{
/* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
@@ -941,6 +944,9 @@ get_available_features (struct __processor_model *cpu_model,
{
if (eax & bit_AVX512BF16)
set_feature (FEATURE_AVX512BF16);
+ /* AVX10 has the same XSTATE with AVX512. */
+ if (edx & bit_AVX10)
+ avx10_set = 1;
}
if (amx_usable)
{
@@ -992,6 +998,33 @@ get_available_features (struct __processor_model *cpu_model,
}
}
+ /* Get Advanced Features at level 0x24 (eax = 0x24). */
+ if (avx10_set && max_cpuid_level >= 0x24)
+ {
+ __cpuid (0x24, eax, ebx, ecx, edx);
+ version = ebx & 0xff;
+ if (ebx & bit_AVX10_256)
+ switch (version)
+ {
+ case 1:
+ set_feature (FEATURE_AVX10_1_256);
+ break;
+ default:
+ set_feature (FEATURE_AVX10_1_256);
+ break;
+ }
+ if (ebx & bit_AVX10_512)
+ switch (version)
+ {
+ case 1:
+ set_feature (FEATURE_AVX10_1_512);
+ break;
+ default:
+ set_feature (FEATURE_AVX10_1_512);
+ break;
+ }
+ }
+
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 1b09499cd26..f101e4dd461 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -126,6 +126,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
+#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
+#define OPTION_MASK_ISA2_AVX10_1_512_SET \
+ (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -235,7 +238,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX2_UNSET \
(OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
| OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
- | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
+ | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
+ | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
#define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
@@ -315,6 +319,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
+#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
+ (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
+#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -616,6 +623,7 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -629,6 +637,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -903,6 +912,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -918,6 +928,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -931,6 +942,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -946,6 +958,7 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -960,6 +973,7 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -975,6 +989,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1042,6 +1057,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1057,6 +1073,7 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1070,6 +1087,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1083,6 +1101,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1096,6 +1115,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1372,6 +1392,7 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
+ opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1388,6 +1409,38 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mavx10_1_256:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+ opts->x_ix86_no_avx10_1_explicit = 1;
+ }
+ return true;
+
+ case OPT_mavx10_1_512:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+ opts->x_ix86_no_avx10_1_explicit = 1;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index a0552ef99a2..38fa7650de2 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -266,6 +266,8 @@ enum processor_features
FEATURE_SM4,
FEATURE_APX_F,
FEATURE_USER_MSR,
+ FEATURE_AVX10_1_256,
+ FEATURE_AVX10_1_512,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 6875924994d..a7b7c52394e 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -193,4 +193,7 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
+ ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
+ ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1-256")
+ ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, "-mavx10.1-512")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 75ef2718204..d1fc93ec91e 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -150,6 +150,7 @@
#define bit_AVXVNNIINT16 (1 << 10)
#define bit_PREFETCHI (1 << 14)
#define bit_USER_MSR (1 << 15)
+#define bit_AVX10 (1 << 19)
#define bit_APX_F (1 << 21)
/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
@@ -166,6 +167,10 @@
#define bit_AESKLE ( 1<<0 )
#define bit_WIDEKL ( 1<<2 )
+/* AVX10 sub leaf (%eax == 0x24) */
+/* %ebx */
+#define bit_AVX10_256 (1 << 17)
+#define bit_AVX10_512 (1 << 18)
/* Signatures for different CPU implementations as returned in uses
of cpuid with level 0. */
diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
index 55d40450c6d..ae67efc49c3 100644
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@@ -369,6 +369,42 @@ detect_caches_intel (bool xeon_mp, unsigned max_level,
return describe_cache (level1, level2);
}
+/* Extended features */
+#define has_feature(f) \
+ has_cpu_feature (&cpu_model, cpu_features2, f)
+
+/* We will emit a warning when using AVX10.1 and AVX512 options with one
+ enabled and the other disabled. Add this function to avoid push "-mno-"
+ options under this scenario for -march=native. */
+
+bool check_avx10_avx512_features (__processor_model &cpu_model,
+ unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES],
+ const enum processor_features feature)
+{
+ if (has_feature (FEATURE_AVX512F)
+ && ((feature == FEATURE_AVX10_1_256)
+ || (feature == FEATURE_AVX10_1_512)))
+ return false;
+
+ if (has_feature (FEATURE_AVX10_1_256)
+ && ((feature == FEATURE_AVX512F)
+ || (feature == FEATURE_AVX512CD)
+ || (feature == FEATURE_AVX512DQ)
+ || (feature == FEATURE_AVX512BW)
+ || (feature == FEATURE_AVX512VL)
+ || (feature == FEATURE_AVX512IFMA)
+ || (feature == FEATURE_AVX512VBMI)
+ || (feature == FEATURE_AVX512VBMI2)
+ || (feature == FEATURE_AVX512VNNI)
+ || (feature == FEATURE_AVX512VPOPCNTDQ)
+ || (feature == FEATURE_AVX512BITALG)
+ || (feature == FEATURE_AVX512FP16)
+ || (feature == FEATURE_AVX512BF16)))
+ return false;
+
+ return true;
+}
+
/* This will be called by the spec parser in gcc.cc when it sees
a %:local_cpu_detect(args) construct. Currently it will be
called with either "arch [32|64]" or "tune [32|64]" as argument
@@ -447,10 +483,6 @@ const char *host_detect_local_cpu (int argc, const char **argv)
}
}
- /* Extended features */
-#define has_feature(f) \
- has_cpu_feature (&cpu_model, cpu_features2, f)
-
if (vendor == VENDOR_AMD)
{
unsigned int name;
@@ -868,7 +900,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
options = concat (options, " ",
isa_names_table[i].option, NULL);
}
- else
+ else if (check_avx10_avx512_features (cpu_model, cpu_features2,
+ isa_names_table[i].feature))
options = concat (options, neg_option,
isa_names_table[i].option + 2, NULL);
}
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 991df5e2ef0..f730aa27a18 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -123,3 +123,6 @@ DEF_PTA(SHA512)
DEF_PTA(SM4)
DEF_PTA(APX_F)
DEF_PTA(USER_MSR)
+DEF_PTA(EVEX512)
+DEF_PTA(AVX10_1_256)
+DEF_PTA(AVX10_1_512)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index df7d24352d1..dd5df559c84 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -258,7 +258,9 @@ static struct ix86_target_opts isa2_opts[] =
{ "-msha512", OPTION_MASK_ISA2_SHA512 },
{ "-msm4", OPTION_MASK_ISA2_SM4 },
{ "-mevex512", OPTION_MASK_ISA2_EVEX512 },
- { "-musermsr", OPTION_MASK_ISA2_USER_MSR }
+ { "-musermsr", OPTION_MASK_ISA2_USER_MSR },
+ { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 },
+ { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -705,6 +707,8 @@ ix86_function_specific_save (struct cl_target_option *ptr,
ptr->x_ix86_apx_features = opts->x_ix86_apx_features;
ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit;
+ ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit;
+ ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit;
ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
ptr->x_ix86_arch_string = opts->x_ix86_arch_string;
ptr->x_ix86_tune_string = opts->x_ix86_tune_string;
@@ -847,6 +851,8 @@ ix86_function_specific_restore (struct gcc_options *opts,
opts->x_ix86_apx_features = ptr->x_ix86_apx_features;
opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit;
+ opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit;
+ opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit;
opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
opts->x_ix86_arch_string = ptr->x_ix86_arch_string;
opts->x_ix86_tune_string = ptr->x_ix86_tune_string;
@@ -1125,6 +1131,9 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
IX86_ATTR_ISA ("apxf", OPT_mapxf),
IX86_ATTR_ISA ("evex512", OPT_mevex512),
IX86_ATTR_ISA ("usermsr", OPT_musermsr),
+ IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
+ IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
+ IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
@@ -1411,6 +1420,17 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
target_clone_attr))
return error_mark_node;
+ /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all
+ AVX512 related ISA flags and not setting EVEX512. When it is used
+ with avx512 related function attribute, we need to enable 512 bit to
+ align with the command line behavior. Manually set EVEX512 for this
+ scenario. */
+ if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
+ && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
+ && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
+
/* If the changed options are different from the default, rerun
ix86_option_override_internal, and then save the options away.
The string options are attribute options, and will be undone
@@ -1421,7 +1441,10 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
|| option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
|| option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
|| enum_opts_set.x_ix86_fpmath
- || enum_opts_set.x_prefer_vector_width_type)
+ || enum_opts_set.x_prefer_vector_width_type
+ || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256)
+ && (opts->x_ix86_isa_flags2_explicit
+ & OPTION_MASK_ISA2_AVX10_1_256)))
{
/* If we are using the default tune= or arch=, undo the string assigned,
and use the default. */
@@ -1963,7 +1986,7 @@ ix86_option_override_internal (bool main_args_p,
struct gcc_options *opts_set)
{
unsigned int i;
- unsigned HOST_WIDE_INT ix86_arch_mask;
+ unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
/* -mrecip options. */
@@ -1982,6 +2005,14 @@ ix86_option_override_internal (bool main_args_p,
{ "vec-sqrt", RECIP_MASK_VEC_SQRT },
};
+ avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD
+ | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW
+ | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA
+ | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2
+ | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ
+ | OPTION_MASK_ISA_AVX512BITALG;
+ avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16
+ | OPTION_MASK_ISA2_AVX512BF16;
/* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
@@ -2590,12 +2621,99 @@ ix86_option_override_internal (bool main_args_p,
&= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
& ~opts->x_ix86_isa_flags_explicit);
- /* Set EVEX512 target if it is not explicitly set
- when AVX512 is enabled. */
- if (TARGET_AVX512F_P(opts->x_ix86_isa_flags)
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
+ /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options except
+ for the following option combinations:
+ 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with no
+ explicit disable on other AVX512 features.
+ 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no
+ explicit disable on other AVX512 features.
+ 3. Both AVX10.1 and AVX512 are disabled. */
+ if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2))
+ {
+ if (opts->x_ix86_no_avx512_explicit
+ && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
+ & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
+ || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
+ & opts->x_ix86_isa_flags2)
+ & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
+ & opts->x_ix86_isa_flags2_explicit)))))
+ warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable "
+ "AVX10 instructions when AVX10.1-512 is available");
+ }
+ else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
+ {
+ if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2)
+ && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit))
+ {
+ if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
+ {
+ /* We should not emit 512 bit instructions under AVX10.1-256
+ when EVEX512 is enabled w/o any AVX512 features enabled.
+ Disable EVEX512 bit for this. */
+ warning (0, "Using %<-mevex512%> without any AVX512 features "
+ "enabled together with AVX10.1 only will not enable "
+ "any AVX512 or AVX10.1-512 features, using 256 as "
+ "max vector size");
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512;
+ }
+ else
+ warning (0, "Vector size conflicts between AVX10.1 and AVX512, "
+ "using 512 as max vector size");
+ }
+ else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && !(OPTION_MASK_ISA2_EVEX512
+ & opts->x_ix86_isa_flags2_explicit))
+ warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
+ "512 as max vector size");
+ else if (opts->x_ix86_no_avx512_explicit
+ && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
+ & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
+ || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2)
+ & (avx512_isa_flags2
+ & opts->x_ix86_isa_flags2_explicit)))))
+ warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions "
+ "when AVX10 is available");
+ }
+ else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
+ {
+ if (opts->x_ix86_no_avx10_1_explicit
+ && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
+ & opts->x_ix86_isa_flags2_explicit))
+ {
+ warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
+ "cannot disable AVX512 instructions when "
+ "%<-mavx512XXX%>");
+ /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is
+ disabled. */
+ if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit)
+ {
+ opts->x_ix86_isa_flags = (~avx512_isa_flags
+ & opts->x_ix86_isa_flags)
+ | (avx512_isa_flags & opts->x_ix86_isa_flags_explicit);
+ opts->x_ix86_isa_flags2 = (~avx512_isa_flags
+ & opts->x_ix86_isa_flags2)
+ | (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit);
+ }
+ }
+ }
+
+ /* Set EVEX512 if one of the following conditions meets:
+ 1. AVX512 is enabled while EVEX512 is not explicitly set/unset.
+ 2. AVX10.1-512 is enabled. */
+ if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2)
+ || (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
+ /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */
+ if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
+ {
+ opts->x_ix86_isa_flags |= avx512_isa_flags;
+ opts->x_ix86_isa_flags2 |= avx512_isa_flags2;
+ }
+
/* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */
if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2))
{
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a56367a947b..fe264d142f0 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2374,7 +2374,7 @@ constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
- | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
+ | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512;
constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
| PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
| PTA_RDPID | PTA_AVX512VPOPCNTDQ;
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 0c3b8f4b621..b81c968876e 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -36,6 +36,13 @@ HOST_WIDE_INT ix86_isa_flags_explicit
Variable
HOST_WIDE_INT ix86_isa_flags2_explicit
+; Indicate if AVX512 and AVX10.1 are explicitly set no.
+Variable
+int ix86_no_avx512_explicit = 0
+
+Variable
+int ix86_no_avx10_1_explicit = 0
+
; Additional target flags
Variable
int ix86_target_flags
@@ -96,6 +103,14 @@ HOST_WIDE_INT x_ix86_isa_flags2_explicit
TargetSave
HOST_WIDE_INT x_ix86_isa_flags_explicit
+;; which flags were passed by the user
+TargetSave
+HOST_WIDE_INT x_ix86_no_avx512_explicit
+
+;; which flags were passed by the user
+TargetSave
+HOST_WIDE_INT x_ix86_no_avx10_1_explicit
+
;; whether -mtune was not specified
TargetSave
unsigned char tune_defaulted
@@ -1348,3 +1363,18 @@ Support 512 bit vector built-in functions and code generation.
musermsr
Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save
Support USER_MSR built-in functions and code generation.
+
+mavx10.1-256
+Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1 built-in functions and code generation.
+
+mavx10.1-512
+Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1-512 built-in functions and code generation.
+
+mavx10.1
+Target Alias(mavx10.1-256)
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+and AVX10.1 built-in functions and code generation.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index fa7402813e7..a4ce2f46d85 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7283,6 +7283,21 @@ Enable/disable the generation of the SM4 instructions.
@itemx no-usermsr
Enable/disable the generation of the USER_MSR instructions.
+@cindex @code{target("avx10.1")} function attribute, x86
+@item avx10.1
+@itemx no-avx10.1
+Enable/disable the generation of the AVX10.1 instructions.
+
+@cindex @code{target("avx10.1-256")} function attribute, x86
+@item avx10.1-256
+@itemx no-avx10.1-256
+Enable/disable the generation of the AVX10.1 instructions.
+
+@cindex @code{target("avx10.1-512")} function attribute, x86
+@item avx10.1-512
+@itemx no-avx10.1-512
+Enable/disable the generation of the AVX10.1 512 bit instructions.
+
@cindex @code{target("cld")} function attribute, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6e776a0faa1..7b98f93bd6a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1449,7 +1449,7 @@ See RS/6000 and PowerPC Options.
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -34027,6 +34027,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@need 200
@opindex musermsr
@itemx -musermsr
+@need 200
+@opindex mavx10.1
+@itemx -mavx10.1
+@need 200
+@opindex mavx10.1-256
+@itemx -mavx10.1-256
+@need 200
+@opindex mavx10.1-512
+@itemx -mavx10.1-512
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -34037,9 +34046,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR or CLDEMOTE
-extended instruction sets. Each has a corresponding @option{-mno-} option
-to disable use of these instructions.
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR, AVX10.1 or
+CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
+option to disable use of these instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c20af31c642..8dfd8435811 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2496,6 +2496,15 @@ Target supports compiling @code{avx} instructions.
@item avx_runtime
Target supports the execution of @code{avx} instructions.
+@item avx10.1
+Target supports the execution of @code{avx10.1} instructions.
+
+@item avx10.1-256
+Target supports the execution of @code{avx10.1} instructions.
+
+@item avx10.1-512
+Target supports the execution of @code{avx10.1-512} instructions.
+
@item avx2
Target supports compiling @code{avx2} instructions.
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
new file mode 100644
index 00000000000..cfd9662bb13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+void
+f1 ()
+{
+ register __m256d a __asm ("ymm17");
+ register __m256d b __asm ("ymm16");
+ a = _mm256_add_pd (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+void
+f2 ()
+{
+ register __m128d a __asm ("xmm17");
+ register __m128d b __asm ("xmm16");
+ a = _mm_add_pd (a, b);
+ asm volatile ("" : "+v" (a));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c
new file mode 100644
index 00000000000..0db5240a30f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-10.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f -mno-evex512" } */
+/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c
new file mode 100644
index 00000000000..c0ad4fc27fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-11.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mno-avx512f" } */
+/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
new file mode 100644
index 00000000000..61f0e4db61b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
+/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
new file mode 100644
index 00000000000..8a111190025
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
new file mode 100644
index 00000000000..03222a7a031
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c
new file mode 100644
index 00000000000..d1731f09a45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-15.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f,no-evex512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c
new file mode 100644
index 00000000000..f5f3ff8127e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-16.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1-512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
new file mode 100644
index 00000000000..a19230f597b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("no-avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c
new file mode 100644
index 00000000000..c50fd2bb29b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-18.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("no-avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
new file mode 100644
index 00000000000..7aacc15aad9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx512f"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
new file mode 100644
index 00000000000..0b3991dcf74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__m512d
+foo ()
+{
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c
new file mode 100644
index 00000000000..d63c6b40d80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-20.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mno-avx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1-512"))) __m512d
+foo ()
+{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
new file mode 100644
index 00000000000..27a7265df61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
+/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
new file mode 100644
index 00000000000..796262283d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("evex512"))) __m512d
+foo ()
+{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
new file mode 100644
index 00000000000..6e8d64d0f34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
+
+__attribute__ ((target ("avx10.1"))) __m512d
+foo ()
+{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
+ __m512d a, b;
+ a = a + b;
+ return a;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
new file mode 100644
index 00000000000..3be988a1a62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+int
+foo (int c)
+{
+ register int a __asm ("k7") = c;
+ int b = foo (a);
+ asm volatile ("" : "+k" (b));
+ return b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
new file mode 100644
index 00000000000..68cbf197d61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-512" } */
+
+#include <immintrin.h>
+
+long long
+foo (long long c)
+{
+ register long long a __asm ("k7") = c;
+ long long b = foo (a);
+ asm volatile ("" : "+k" (b));
+ return b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
new file mode 100644
index 00000000000..20b78ea9510
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-final { scan-assembler-not ".%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
new file mode 100644
index 00000000000..827c80ce51e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+
+#include <immintrin.h>
+
+long long
+foo (long long c)
+{
+ register long long a __asm ("k7") = c;
+ long long b = foo (a);
+ asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */
+ return b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
new file mode 100644
index 00000000000..afce2905421
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
new file mode 100644
index 00000000000..69b6c6a3e1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
@@ -0,0 +1,4 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
+
+#include "avx10_1-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c
new file mode 100644
index 00000000000..8e838277962
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-9.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */
+/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
--
2.31.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-10 1:41 [RFC] Intel AVX10.1 Compiler Design and Support Haochen Jiang
2023-11-10 1:41 ` [PATCH] Initial support for AVX10.1 Haochen Jiang
@ 2023-11-10 10:15 ` Richard Biener
2023-11-13 7:07 ` Hongtao Liu
1 sibling, 1 reply; 11+ messages in thread
From: Richard Biener @ 2023-11-10 10:15 UTC (permalink / raw)
To: Haochen Jiang; +Cc: gcc-patches, hongtao.liu, ubizjak
On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> Hi all,
>
> This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
> support, it makes a lot easier to add them comparing to the August version.
> Detail for AVX10 is shown below:
>
> Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
> It describes the Intel Advanced Vector Extensions 10 Instruction Set
> Architecture.
> https://cdrdv2.intel.com/v1/dl/getContent/784267
>
> The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
> It provides introductory information regarding the converged vector ISA: Intel
> Advanced Vector Extensions 10.
> https://cdrdv2.intel.com/v1/dl/getContent/784343
>
> Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
> the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
> anything at first. At the end of the option handling, we will check whether
> the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
> ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.
>
> It means that AVX10 options will be separated from the existing AVX512 and the
> newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
> (enable/disable/set vector size) the AVX512 features underneath independently.
> If there’s potential overlap or conflict between AVX10 and AVX512 options,
> some rules are provided to define the behavior, which will be described below.
>
> avx10.1 option will be provided as an alias of avx10.1-256.
>
> In the future, the AVX10 options will imply like this:
>
> AVX10.1-256 <---- AVX10.1-512
> ^ ^
> | |
>
> AVX10.2-256 <---- AVX10.2-512
> ^ ^
> | |
>
> AVX10.3-256 <---- AVX10.3-512
> ^ ^
> | |
>
> Each of them will have its own option to enable/disabled corresponding
> features. The alias avx10.x will also be provided.
>
> As mentioned in August version RFC, since we lean towards the adoption of
> AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
> AVX10 and legacy AVX512 options.
I wonder whether adoption could be made easier by also providing a
-mavx10[.0] level that removes some of the more obscure sub-ISA requirements
to cover more existing implementations (I'd not add -mavx10.0-512 here).
I'd require only skylake-AVX512 features here, basically all non-KNL AVX512
CPUs should have a "virtual" AVX10 level that allows to use that feature set,
restricted to 256bits so future AVX10-256 implementations can handle it
as well as all existing (and relevant, which excludes KNL) AVX512
implementations.
Otherwise AVX10 is really a hard sell (as AVX512 was originally).
> However, we would like to introduce some
> simple rules for user when it comes to combination.
>
> 1. Enabling AVX10 and AVX512 at the same command line with different vector
> size will lead to a warning message. The behavior of the compiler will be
> enabling AVX10 with longer, i.e., 512 bit vector size.
>
> If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
> -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.
>
> 2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
> impact the vector size, and vice versa. The compiler will emit warnings if
> necessary.
>
> For the auto dispatch support including function multi versioning, function
> attribute usage, the behavior will be identical to compiler options.
>
> If you have any questions, feel free to ask in this thread.
>
> Thx,
> Haochen
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-10 10:15 ` [RFC] Intel AVX10.1 Compiler Design and Support Richard Biener
@ 2023-11-13 7:07 ` Hongtao Liu
2023-11-13 11:25 ` Richard Biener
0 siblings, 1 reply; 11+ messages in thread
From: Hongtao Liu @ 2023-11-13 7:07 UTC (permalink / raw)
To: Richard Biener; +Cc: Haochen Jiang, gcc-patches, hongtao.liu, ubizjak
On Fri, Nov 10, 2023 at 6:15 PM Richard Biener
<richard.guenther@gmail.com> wrote:
>
> On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
> >
> > Hi all,
> >
> > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
> > support, it makes a lot easier to add them comparing to the August version.
> > Detail for AVX10 is shown below:
> >
> > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
> > It describes the Intel Advanced Vector Extensions 10 Instruction Set
> > Architecture.
> > https://cdrdv2.intel.com/v1/dl/getContent/784267
> >
> > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
> > It provides introductory information regarding the converged vector ISA: Intel
> > Advanced Vector Extensions 10.
> > https://cdrdv2.intel.com/v1/dl/getContent/784343
> >
> > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
> > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
> > anything at first. At the end of the option handling, we will check whether
> > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
> > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.
> >
> > It means that AVX10 options will be separated from the existing AVX512 and the
> > newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
> > (enable/disable/set vector size) the AVX512 features underneath independently.
> > If there’s potential overlap or conflict between AVX10 and AVX512 options,
> > some rules are provided to define the behavior, which will be described below.
> >
> > avx10.1 option will be provided as an alias of avx10.1-256.
> >
> > In the future, the AVX10 options will imply like this:
> >
> > AVX10.1-256 <---- AVX10.1-512
> > ^ ^
> > | |
> >
> > AVX10.2-256 <---- AVX10.2-512
> > ^ ^
> > | |
> >
> > AVX10.3-256 <---- AVX10.3-512
> > ^ ^
> > | |
> >
> > Each of them will have its own option to enable/disabled corresponding
> > features. The alias avx10.x will also be provided.
> >
> > As mentioned in August version RFC, since we lean towards the adoption of
> > AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
> > AVX10 and legacy AVX512 options.
>
> I wonder whether adoption could be made easier by also providing a
> -mavx10[.0] level that removes some of the more obscure sub-ISA requirements
> to cover more existing implementations (I'd not add -mavx10.0-512 here).
> I'd require only skylake-AVX512 features here, basically all non-KNL AVX512
> CPUs should have a "virtual" AVX10 level that allows to use that feature set,
We have -mno-evex512 can cover those cases, so what you want is like a
simple alias of "-march=skylake-avx512 -mno-evex512"?
> restricted to 256bits so future AVX10-256 implementations can handle it
> as well as all existing (and relevant, which excludes KNL) AVX512
> implementations.
>
> Otherwise AVX10 is really a hard sell (as AVX512 was originally).
It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just
complicated things further(considering we already have x86-64-v4 which
is different from skylake-avx512).
>
> > However, we would like to introduce some
> > simple rules for user when it comes to combination.
> >
> > 1. Enabling AVX10 and AVX512 at the same command line with different vector
> > size will lead to a warning message. The behavior of the compiler will be
> > enabling AVX10 with longer, i.e., 512 bit vector size.
> >
> > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
> > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.
> >
> > 2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
> > impact the vector size, and vice versa. The compiler will emit warnings if
> > necessary.
> >
> > For the auto dispatch support including function multi versioning, function
> > attribute usage, the behavior will be identical to compiler options.
> >
> > If you have any questions, feel free to ask in this thread.
> >
> > Thx,
> > Haochen
> >
> >
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-13 7:07 ` Hongtao Liu
@ 2023-11-13 11:25 ` Richard Biener
2023-11-14 2:40 ` Hongtao Liu
2023-12-12 9:05 ` Florian Weimer
0 siblings, 2 replies; 11+ messages in thread
From: Richard Biener @ 2023-11-13 11:25 UTC (permalink / raw)
To: Hongtao Liu; +Cc: Haochen Jiang, gcc-patches, hongtao.liu, ubizjak
On Mon, Nov 13, 2023 at 7:58 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Fri, Nov 10, 2023 at 6:15 PM Richard Biener
> <richard.guenther@gmail.com> wrote:
> >
> > On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
> > >
> > > Hi all,
> > >
> > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
> > > support, it makes a lot easier to add them comparing to the August version.
> > > Detail for AVX10 is shown below:
> > >
> > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
> > > It describes the Intel Advanced Vector Extensions 10 Instruction Set
> > > Architecture.
> > > https://cdrdv2.intel.com/v1/dl/getContent/784267
> > >
> > > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
> > > It provides introductory information regarding the converged vector ISA: Intel
> > > Advanced Vector Extensions 10.
> > > https://cdrdv2.intel.com/v1/dl/getContent/784343
> > >
> > > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
> > > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
> > > anything at first. At the end of the option handling, we will check whether
> > > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
> > > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.
> > >
> > > It means that AVX10 options will be separated from the existing AVX512 and the
> > > newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
> > > (enable/disable/set vector size) the AVX512 features underneath independently.
> > > If there’s potential overlap or conflict between AVX10 and AVX512 options,
> > > some rules are provided to define the behavior, which will be described below.
> > >
> > > avx10.1 option will be provided as an alias of avx10.1-256.
> > >
> > > In the future, the AVX10 options will imply like this:
> > >
> > > AVX10.1-256 <---- AVX10.1-512
> > > ^ ^
> > > | |
> > >
> > > AVX10.2-256 <---- AVX10.2-512
> > > ^ ^
> > > | |
> > >
> > > AVX10.3-256 <---- AVX10.3-512
> > > ^ ^
> > > | |
> > >
> > > Each of them will have its own option to enable/disabled corresponding
> > > features. The alias avx10.x will also be provided.
> > >
> > > As mentioned in August version RFC, since we lean towards the adoption of
> > > AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
> > > AVX10 and legacy AVX512 options.
> >
> > I wonder whether adoption could be made easier by also providing a
> > -mavx10[.0] level that removes some of the more obscure sub-ISA requirements
> > to cover more existing implementations (I'd not add -mavx10.0-512 here).
> > I'd require only skylake-AVX512 features here, basically all non-KNL AVX512
> > CPUs should have a "virtual" AVX10 level that allows to use that feature set,
> We have -mno-evex512 can cover those cases, so what you want is like a
> simple alias of "-march=skylake-avx512 -mno-evex512"?
For the AVX512 enabled sub-isas of skylake-avx512 yes I guess.
> > restricted to 256bits so future AVX10-256 implementations can handle it
> > as well as all existing (and relevant, which excludes KNL) AVX512
> > implementations.
> >
> > Otherwise AVX10 is really a hard sell (as AVX512 was originally).
> It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just
> complicated things further(considering we already have x86-64-v4 which
> is different from skylake-avx512).
Well, the cut-off for "AVX512" is quite arbitrary. Introducing a
"new" ISA that's
only available in HW available in the future and suggesting users to embrace
that already (like Intel did with AVX512 without offering client SKU support)
is a hard sell.
I realize Intel thinks client SKU support for AVX10 (restricted to 256bit) will
be "easier". But then don't expect anybody to adopt that in the next 10 years.
Just to add - we were suggesting to use x86_64-v3 for the "next" enterprise
product but got downvoted to x86_64-v2 for compatibility reasons.
If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5
that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit
(and obviously not requiring more of the AVX512 features that v4 requires).
Richard.
> >
> > > However, we would like to introduce some
> > > simple rules for user when it comes to combination.
> > >
> > > 1. Enabling AVX10 and AVX512 at the same command line with different vector
> > > size will lead to a warning message. The behavior of the compiler will be
> > > enabling AVX10 with longer, i.e., 512 bit vector size.
> > >
> > > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
> > > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.
> > >
> > > 2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
> > > impact the vector size, and vice versa. The compiler will emit warnings if
> > > necessary.
> > >
> > > For the auto dispatch support including function multi versioning, function
> > > attribute usage, the behavior will be identical to compiler options.
> > >
> > > If you have any questions, feel free to ask in this thread.
> > >
> > > Thx,
> > > Haochen
> > >
> > >
>
>
>
> --
> BR,
> Hongtao
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-13 11:25 ` Richard Biener
@ 2023-11-14 2:40 ` Hongtao Liu
2023-11-14 6:25 ` Jiang, Haochen
2023-12-12 9:05 ` Florian Weimer
1 sibling, 1 reply; 11+ messages in thread
From: Hongtao Liu @ 2023-11-14 2:40 UTC (permalink / raw)
To: Richard Biener
Cc: Haochen Jiang, gcc-patches, hongtao.liu, ubizjak, Florian Weimer
On Mon, Nov 13, 2023 at 7:25 PM Richard Biener
<richard.guenther@gmail.com> wrote:
>
> On Mon, Nov 13, 2023 at 7:58 AM Hongtao Liu <crazylht@gmail.com> wrote:
> >
> > On Fri, Nov 10, 2023 at 6:15 PM Richard Biener
> > <richard.guenther@gmail.com> wrote:
> > >
> > > On Fri, Nov 10, 2023 at 2:42 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
> > > >
> > > > Hi all,
> > > >
> > > > This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512
> > > > support, it makes a lot easier to add them comparing to the August version.
> > > > Detail for AVX10 is shown below:
> > > >
> > > > Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification
> > > > It describes the Intel Advanced Vector Extensions 10 Instruction Set
> > > > Architecture.
> > > > https://cdrdv2.intel.com/v1/dl/getContent/784267
> > > >
> > > > The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper
> > > > It provides introductory information regarding the converged vector ISA: Intel
> > > > Advanced Vector Extensions 10.
> > > > https://cdrdv2.intel.com/v1/dl/getContent/784343
> > > >
> > > > Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in
> > > > the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable
> > > > anything at first. At the end of the option handling, we will check whether
> > > > the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related
> > > > ISA bits. AVX10.1-512 will further set EVEX512 ISA bit.
> > > >
> > > > It means that AVX10 options will be separated from the existing AVX512 and the
> > > > newly added -m[no-]evex512 options. AVX10 and AVX512 options will control
> > > > (enable/disable/set vector size) the AVX512 features underneath independently.
> > > > If there’s potential overlap or conflict between AVX10 and AVX512 options,
> > > > some rules are provided to define the behavior, which will be described below.
> > > >
> > > > avx10.1 option will be provided as an alias of avx10.1-256.
> > > >
> > > > In the future, the AVX10 options will imply like this:
> > > >
> > > > AVX10.1-256 <---- AVX10.1-512
> > > > ^ ^
> > > > | |
> > > >
> > > > AVX10.2-256 <---- AVX10.2-512
> > > > ^ ^
> > > > | |
> > > >
> > > > AVX10.3-256 <---- AVX10.3-512
> > > > ^ ^
> > > > | |
> > > >
> > > > Each of them will have its own option to enable/disabled corresponding
> > > > features. The alias avx10.x will also be provided.
> > > >
> > > > As mentioned in August version RFC, since we lean towards the adoption of
> > > > AVX10 instead of AVX512 from now on, we don’t recommend users to combine the
> > > > AVX10 and legacy AVX512 options.
> > >
> > > I wonder whether adoption could be made easier by also providing a
> > > -mavx10[.0] level that removes some of the more obscure sub-ISA requirements
> > > to cover more existing implementations (I'd not add -mavx10.0-512 here).
> > > I'd require only skylake-AVX512 features here, basically all non-KNL AVX512
> > > CPUs should have a "virtual" AVX10 level that allows to use that feature set,
> > We have -mno-evex512 can cover those cases, so what you want is like a
> > simple alias of "-march=skylake-avx512 -mno-evex512"?
>
> For the AVX512 enabled sub-isas of skylake-avx512 yes I guess.
>
> > > restricted to 256bits so future AVX10-256 implementations can handle it
> > > as well as all existing (and relevant, which excludes KNL) AVX512
> > > implementations.
> > >
> > > Otherwise AVX10 is really a hard sell (as AVX512 was originally).
> > It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just
> > complicated things further(considering we already have x86-64-v4 which
> > is different from skylake-avx512).
>
> Well, the cut-off for "AVX512" is quite arbitrary. Introducing a
> "new" ISA that's
> only available in HW available in the future and suggesting users to embrace
> that already (like Intel did with AVX512 without offering client SKU support)
> is a hard sell.
>
> I realize Intel thinks client SKU support for AVX10 (restricted to 256bit) will
> be "easier". But then don't expect anybody to adopt that in the next 10 years.
>
> Just to add - we were suggesting to use x86_64-v3 for the "next" enterprise
> product but got downvoted to x86_64-v2 for compatibility reasons.
>
> If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5
> that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit
> (and obviously not requiring more of the AVX512 features that v4 requires).
About the arch level is indeed a problem, especially since the default
size of avx10 is 256.
+Florian Weimer for more inputs.
>
> Richard.
>
> > >
> > > > However, we would like to introduce some
> > > > simple rules for user when it comes to combination.
> > > >
> > > > 1. Enabling AVX10 and AVX512 at the same command line with different vector
> > > > size will lead to a warning message. The behavior of the compiler will be
> > > > enabling AVX10 with longer, i.e., 512 bit vector size.
> > > >
> > > > If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512,
> > > > -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size.
> > > >
> > > > 2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or
> > > > impact the vector size, and vice versa. The compiler will emit warnings if
> > > > necessary.
> > > >
> > > > For the auto dispatch support including function multi versioning, function
> > > > attribute usage, the behavior will be identical to compiler options.
> > > >
> > > > If you have any questions, feel free to ask in this thread.
> > > >
> > > > Thx,
> > > > Haochen
> > > >
> > > >
> >
> >
> >
> > --
> > BR,
> > Hongtao
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-14 2:40 ` Hongtao Liu
@ 2023-11-14 6:25 ` Jiang, Haochen
0 siblings, 0 replies; 11+ messages in thread
From: Jiang, Haochen @ 2023-11-14 6:25 UTC (permalink / raw)
To: Hongtao Liu, Richard Biener
Cc: gcc-patches, Liu, Hongtao, ubizjak, Florian Weimer
> > > > I wonder whether adoption could be made easier by also providing a
> > > > -mavx10[.0] level that removes some of the more obscure sub-ISA
> > > > requirements to cover more existing implementations (I'd not add -mavx10.0-512 here).
> > > > I'd require only skylake-AVX512 features here, basically all
> > > > non-KNL AVX512 CPUs should have a "virtual" AVX10 level that
> > > > allows to use that feature set,
> > >
> > > We have -mno-evex512 can cover those cases, so what you want is like
> > > a simple alias of "-march=skylake-avx512 -mno-evex512"?
> >
> > For the AVX512 enabled sub-isas of skylake-avx512 yes I guess.
> >
> > > > restricted to 256bits so future AVX10-256 implementations can
> > > > handle it as well as all existing (and relevant, which excludes
> > > > KNL) AVX512 implementations.
> > > >
> > > > Otherwise AVX10 is really a hard sell (as AVX512 was originally).
> > >
> > > It's a rebranding of the existing AVX512 to AVX10, AVX10.0 just
> > > complicated things further(considering we already have x86-64-v4
> > > which is different from skylake-avx512).
> >
> > Well, the cut-off for "AVX512" is quite arbitrary. Introducing a
> > "new" ISA that's only available in HW available in the future and
> > suggesting users to embrace that already (like Intel did with AVX512
> > without offering client SKU support) is a hard sell.
> >
> > I realize Intel thinks client SKU support for AVX10 (restricted to
> > 256bit) will be "easier". But then don't expect anybody to adopt that in the next 10 years.
> >
> > Just to add - we were suggesting to use x86_64-v3 for the "next"
> > enterprise product but got downvoted to x86_64-v2 for compatibility reasons.
> >
> > If it were possible I'd axe x86_64-v4. Maybe we should add a
> > x86_64-v3.5 that sits inbetween v3 and v4, offering AVX512 but
> > restricted to 256bit (and obviously not requiring more of the AVX512 features that v4 requires).
>
> About the arch level is indeed a problem, especially since the default size of
> avx10 is 256.
> +Florian Weimer for more inputs.
IMO, AVX10.1 options should be there and the arch level issue should not affect the
existence of this series of options.
The issue currently we are facing is much about the arch level issue actually since
we have defined x86-64-v4 before. The "-march=skylake-server -mno-evex512" is
much like something x86-64-v4-256.
Thx,
Haochen
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] Initial support for AVX10.1
2023-11-10 1:41 ` [PATCH] Initial support for AVX10.1 Haochen Jiang
@ 2023-11-20 6:34 ` Hongtao Liu
0 siblings, 0 replies; 11+ messages in thread
From: Hongtao Liu @ 2023-11-20 6:34 UTC (permalink / raw)
To: Haochen Jiang; +Cc: gcc-patches, hongtao.liu, ubizjak
On Fri, Nov 10, 2023 at 9:42 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Add avx10_set and version and detect avx10.1.
> (cpu_indicator_init): Handle avx10.1-512.
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_AVX10_1_256_SET): New.
> (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
> (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
> (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
> (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
> (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
> Add indicator for explicit no-avx512 and no-avx10.1 options.
> * common/config/i386/i386-cpuinfo.h (enum processor_features):
> Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
> * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
> AVX10_1_256 and AVX10_1_512.
> * config/i386/cpuid.h (bit_AVX10): New.
> (bit_AVX10_256): Ditto.
> (bit_AVX10_512): Ditto.
> * config/i386/driver-i386.cc (check_avx10_avx512_features): New.
> (host_detect_local_cpu): Do not append "-mno-" options under
> specific scenarios to avoid emitting a warning.
> * config/i386/i386-isa.def
> (EVEX512): Add DEF_PTA(EVEX512).
> (AVX10_1_256): Add DEF_PTA(AVX10_1_256).
> (AVX10_1_512): Add DEF_PTA(AVX10_1_512).
> * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
> -mavx10.1-512.
> (ix86_function_specific_save): Save explicit no indicator.
> (ix86_function_specific_restore): Restore explicit no indicator.
> (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
> avx10.1-512.
> (ix86_valid_target_attribute_tree): Handle avx512 function
> attributes with avx10.1 command line option.
> (ix86_option_override_internal): Handle AVX10.1 options.
> * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
> machines.
> * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
> ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
> -mavx10.1-512.
> * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
> * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
> * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
> and avx10.1-512.
The main concern from AVX10 is related to the arch level(x86-64-v4)
which is discussed in another thread.[1]
So I'm going to approve this patch.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636285.html
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx10_1-1.c: New test.
> * gcc.target/i386/avx10_1-10.c: Ditto.
> * gcc.target/i386/avx10_1-11.c: Ditto.
> * gcc.target/i386/avx10_1-12.c: Ditto.
> * gcc.target/i386/avx10_1-13.c: Ditto.
> * gcc.target/i386/avx10_1-14.c: Ditto.
> * gcc.target/i386/avx10_1-15.c: Ditto.
> * gcc.target/i386/avx10_1-16.c: Ditto.
> * gcc.target/i386/avx10_1-17.c: Ditto.
> * gcc.target/i386/avx10_1-18.c: Ditto.
> * gcc.target/i386/avx10_1-19.c: Ditto.
> * gcc.target/i386/avx10_1-2.c: Ditto.
> * gcc.target/i386/avx10_1-20.c: Ditto.
> * gcc.target/i386/avx10_1-21.c: Ditto.
> * gcc.target/i386/avx10_1-22.c: Ditto.
> * gcc.target/i386/avx10_1-23.c: Ditto.
> * gcc.target/i386/avx10_1-3.c: Ditto.
> * gcc.target/i386/avx10_1-4.c: Ditto.
> * gcc.target/i386/avx10_1-5.c: Ditto.
> * gcc.target/i386/avx10_1-6.c: Ditto.
> * gcc.target/i386/avx10_1-7.c: Ditto.
> * gcc.target/i386/avx10_1-8.c: Ditto.
> * gcc.target/i386/avx10_1-9.c: Ditto.
> ---
> gcc/common/config/i386/cpuinfo.h | 33 ++++++
> gcc/common/config/i386/i386-common.cc | 55 ++++++++-
> gcc/common/config/i386/i386-cpuinfo.h | 2 +
> gcc/common/config/i386/i386-isas.h | 3 +
> gcc/config/i386/cpuid.h | 5 +
> gcc/config/i386/driver-i386.cc | 43 ++++++-
> gcc/config/i386/i386-isa.def | 3 +
> gcc/config/i386/i386-options.cc | 132 +++++++++++++++++++--
> gcc/config/i386/i386.h | 2 +-
> gcc/config/i386/i386.opt | 30 +++++
> gcc/doc/extend.texi | 15 +++
> gcc/doc/invoke.texi | 17 ++-
> gcc/doc/sourcebuild.texi | 9 ++
> gcc/testsuite/gcc.target/i386/avx10_1-1.c | 22 ++++
> gcc/testsuite/gcc.target/i386/avx10_1-10.c | 6 +
> gcc/testsuite/gcc.target/i386/avx10_1-11.c | 6 +
> gcc/testsuite/gcc.target/i386/avx10_1-12.c | 6 +
> gcc/testsuite/gcc.target/i386/avx10_1-13.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-14.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-15.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-16.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-17.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-18.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-19.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-2.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-20.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-21.c | 6 +
> gcc/testsuite/gcc.target/i386/avx10_1-22.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-23.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-3.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-4.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-5.c | 5 +
> gcc/testsuite/gcc.target/i386/avx10_1-6.c | 13 ++
> gcc/testsuite/gcc.target/i386/avx10_1-7.c | 5 +
> gcc/testsuite/gcc.target/i386/avx10_1-8.c | 4 +
> gcc/testsuite/gcc.target/i386/avx10_1-9.c | 6 +
> 36 files changed, 579 insertions(+), 18 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-10.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-11.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-12.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-13.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-14.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-15.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-16.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-17.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-18.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-19.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-20.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-21.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-22.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-23.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-6.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-7.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-8.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-9.c
>
> diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
> index 7d25479eb89..f90fb4d56a2 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -715,6 +715,9 @@ get_available_features (struct __processor_model *cpu_model,
> int apx_usable = 0;
> /* Check if KL is usable. */
> int has_kl = 0;
> + /* Record AVX10 version. */
> + int avx10_set = 0;
> + int version = 0;
> if ((ecx & bit_OSXSAVE))
> {
> /* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
> @@ -941,6 +944,9 @@ get_available_features (struct __processor_model *cpu_model,
> {
> if (eax & bit_AVX512BF16)
> set_feature (FEATURE_AVX512BF16);
> + /* AVX10 has the same XSTATE with AVX512. */
> + if (edx & bit_AVX10)
> + avx10_set = 1;
> }
> if (amx_usable)
> {
> @@ -992,6 +998,33 @@ get_available_features (struct __processor_model *cpu_model,
> }
> }
>
> + /* Get Advanced Features at level 0x24 (eax = 0x24). */
> + if (avx10_set && max_cpuid_level >= 0x24)
> + {
> + __cpuid (0x24, eax, ebx, ecx, edx);
> + version = ebx & 0xff;
> + if (ebx & bit_AVX10_256)
> + switch (version)
> + {
> + case 1:
> + set_feature (FEATURE_AVX10_1_256);
> + break;
> + default:
> + set_feature (FEATURE_AVX10_1_256);
> + break;
> + }
> + if (ebx & bit_AVX10_512)
> + switch (version)
> + {
> + case 1:
> + set_feature (FEATURE_AVX10_1_512);
> + break;
> + default:
> + set_feature (FEATURE_AVX10_1_512);
> + break;
> + }
> + }
> +
> /* Check cpuid level of extended features. */
> __cpuid (0x80000000, ext_level, ebx, ecx, edx);
>
> diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
> index 1b09499cd26..f101e4dd461 100644
> --- a/gcc/common/config/i386/i386-common.cc
> +++ b/gcc/common/config/i386/i386-common.cc
> @@ -126,6 +126,9 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
> #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
> #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
> +#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
> +#define OPTION_MASK_ISA2_AVX10_1_512_SET \
> + (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
>
> /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
> as -msse4.2. */
> @@ -235,7 +238,8 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_AVX2_UNSET \
> (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
> | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
> - | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
> + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
> + | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
> #define OPTION_MASK_ISA_AVX512F_UNSET \
> (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
> | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
> @@ -315,6 +319,9 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
> #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
> #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
> +#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
> + (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET)
> +#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512
>
> /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
> as -mno-sse4.1. */
> @@ -616,6 +623,7 @@ ix86_handle_option (struct gcc_options *opts,
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
> opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
> opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -629,6 +637,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -903,6 +912,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -918,6 +928,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
> opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -931,6 +942,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -946,6 +958,7 @@ ix86_handle_option (struct gcc_options *opts,
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
> opts->x_ix86_isa_flags_explicit
> |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -960,6 +973,7 @@ ix86_handle_option (struct gcc_options *opts,
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
> opts->x_ix86_isa_flags_explicit
> |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -975,6 +989,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
> opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1042,6 +1057,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1057,6 +1073,7 @@ ix86_handle_option (struct gcc_options *opts,
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
> opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
> opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1070,6 +1087,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1083,6 +1101,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1096,6 +1115,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
> opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1372,6 +1392,7 @@ ix86_handle_option (struct gcc_options *opts,
> {
> opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
> opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
> + opts->x_ix86_no_avx512_explicit = 1;
> }
> return true;
>
> @@ -1388,6 +1409,38 @@ ix86_handle_option (struct gcc_options *opts,
> }
> return true;
>
> + case OPT_mavx10_1_256:
> + if (value)
> + {
> + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET;
> + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET;
> + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
> + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
> + }
> + else
> + {
> + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
> + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
> + opts->x_ix86_no_avx10_1_explicit = 1;
> + }
> + return true;
> +
> + case OPT_mavx10_1_512:
> + if (value)
> + {
> + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET;
> + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET;
> + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
> + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
> + }
> + else
> + {
> + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
> + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
> + opts->x_ix86_no_avx10_1_explicit = 1;
> + }
> + return true;
> +
> case OPT_mfma:
> if (value)
> {
> diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
> index a0552ef99a2..38fa7650de2 100644
> --- a/gcc/common/config/i386/i386-cpuinfo.h
> +++ b/gcc/common/config/i386/i386-cpuinfo.h
> @@ -266,6 +266,8 @@ enum processor_features
> FEATURE_SM4,
> FEATURE_APX_F,
> FEATURE_USER_MSR,
> + FEATURE_AVX10_1_256,
> + FEATURE_AVX10_1_512,
> CPU_FEATURE_MAX
> };
>
> diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
> index 6875924994d..a7b7c52394e 100644
> --- a/gcc/common/config/i386/i386-isas.h
> +++ b/gcc/common/config/i386/i386-isas.h
> @@ -193,4 +193,7 @@ ISA_NAMES_TABLE_START
> ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
> ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
> ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
> + ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
> + ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1-256")
> + ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, "-mavx10.1-512")
> ISA_NAMES_TABLE_END
> diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
> index 75ef2718204..d1fc93ec91e 100644
> --- a/gcc/config/i386/cpuid.h
> +++ b/gcc/config/i386/cpuid.h
> @@ -150,6 +150,7 @@
> #define bit_AVXVNNIINT16 (1 << 10)
> #define bit_PREFETCHI (1 << 14)
> #define bit_USER_MSR (1 << 15)
> +#define bit_AVX10 (1 << 19)
> #define bit_APX_F (1 << 21)
>
> /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
> @@ -166,6 +167,10 @@
> #define bit_AESKLE ( 1<<0 )
> #define bit_WIDEKL ( 1<<2 )
>
> +/* AVX10 sub leaf (%eax == 0x24) */
> +/* %ebx */
> +#define bit_AVX10_256 (1 << 17)
> +#define bit_AVX10_512 (1 << 18)
>
> /* Signatures for different CPU implementations as returned in uses
> of cpuid with level 0. */
> diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
> index 55d40450c6d..ae67efc49c3 100644
> --- a/gcc/config/i386/driver-i386.cc
> +++ b/gcc/config/i386/driver-i386.cc
> @@ -369,6 +369,42 @@ detect_caches_intel (bool xeon_mp, unsigned max_level,
> return describe_cache (level1, level2);
> }
>
> +/* Extended features */
> +#define has_feature(f) \
> + has_cpu_feature (&cpu_model, cpu_features2, f)
> +
> +/* We will emit a warning when using AVX10.1 and AVX512 options with one
> + enabled and the other disabled. Add this function to avoid push "-mno-"
> + options under this scenario for -march=native. */
> +
> +bool check_avx10_avx512_features (__processor_model &cpu_model,
> + unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES],
> + const enum processor_features feature)
> +{
> + if (has_feature (FEATURE_AVX512F)
> + && ((feature == FEATURE_AVX10_1_256)
> + || (feature == FEATURE_AVX10_1_512)))
> + return false;
> +
> + if (has_feature (FEATURE_AVX10_1_256)
> + && ((feature == FEATURE_AVX512F)
> + || (feature == FEATURE_AVX512CD)
> + || (feature == FEATURE_AVX512DQ)
> + || (feature == FEATURE_AVX512BW)
> + || (feature == FEATURE_AVX512VL)
> + || (feature == FEATURE_AVX512IFMA)
> + || (feature == FEATURE_AVX512VBMI)
> + || (feature == FEATURE_AVX512VBMI2)
> + || (feature == FEATURE_AVX512VNNI)
> + || (feature == FEATURE_AVX512VPOPCNTDQ)
> + || (feature == FEATURE_AVX512BITALG)
> + || (feature == FEATURE_AVX512FP16)
> + || (feature == FEATURE_AVX512BF16)))
> + return false;
> +
> + return true;
> +}
> +
> /* This will be called by the spec parser in gcc.cc when it sees
> a %:local_cpu_detect(args) construct. Currently it will be
> called with either "arch [32|64]" or "tune [32|64]" as argument
> @@ -447,10 +483,6 @@ const char *host_detect_local_cpu (int argc, const char **argv)
> }
> }
>
> - /* Extended features */
> -#define has_feature(f) \
> - has_cpu_feature (&cpu_model, cpu_features2, f)
> -
> if (vendor == VENDOR_AMD)
> {
> unsigned int name;
> @@ -868,7 +900,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
> options = concat (options, " ",
> isa_names_table[i].option, NULL);
> }
> - else
> + else if (check_avx10_avx512_features (cpu_model, cpu_features2,
> + isa_names_table[i].feature))
> options = concat (options, neg_option,
> isa_names_table[i].option + 2, NULL);
> }
> diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
> index 991df5e2ef0..f730aa27a18 100644
> --- a/gcc/config/i386/i386-isa.def
> +++ b/gcc/config/i386/i386-isa.def
> @@ -123,3 +123,6 @@ DEF_PTA(SHA512)
> DEF_PTA(SM4)
> DEF_PTA(APX_F)
> DEF_PTA(USER_MSR)
> +DEF_PTA(EVEX512)
> +DEF_PTA(AVX10_1_256)
> +DEF_PTA(AVX10_1_512)
> diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
> index df7d24352d1..dd5df559c84 100644
> --- a/gcc/config/i386/i386-options.cc
> +++ b/gcc/config/i386/i386-options.cc
> @@ -258,7 +258,9 @@ static struct ix86_target_opts isa2_opts[] =
> { "-msha512", OPTION_MASK_ISA2_SHA512 },
> { "-msm4", OPTION_MASK_ISA2_SM4 },
> { "-mevex512", OPTION_MASK_ISA2_EVEX512 },
> - { "-musermsr", OPTION_MASK_ISA2_USER_MSR }
> + { "-musermsr", OPTION_MASK_ISA2_USER_MSR },
> + { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 },
> + { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 }
> };
> static struct ix86_target_opts isa_opts[] =
> {
> @@ -705,6 +707,8 @@ ix86_function_specific_save (struct cl_target_option *ptr,
> ptr->x_ix86_apx_features = opts->x_ix86_apx_features;
> ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
> ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit;
> + ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit;
> + ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit;
> ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
> ptr->x_ix86_arch_string = opts->x_ix86_arch_string;
> ptr->x_ix86_tune_string = opts->x_ix86_tune_string;
> @@ -847,6 +851,8 @@ ix86_function_specific_restore (struct gcc_options *opts,
> opts->x_ix86_apx_features = ptr->x_ix86_apx_features;
> opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
> opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit;
> + opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit;
> + opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit;
> opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
> opts->x_ix86_arch_string = ptr->x_ix86_arch_string;
> opts->x_ix86_tune_string = ptr->x_ix86_tune_string;
> @@ -1125,6 +1131,9 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
> IX86_ATTR_ISA ("apxf", OPT_mapxf),
> IX86_ATTR_ISA ("evex512", OPT_mevex512),
> IX86_ATTR_ISA ("usermsr", OPT_musermsr),
> + IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
> + IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
> + IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
>
> /* enum options */
> IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
> @@ -1411,6 +1420,17 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
> target_clone_attr))
> return error_mark_node;
>
> + /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all
> + AVX512 related ISA flags and not setting EVEX512. When it is used
> + with avx512 related function attribute, we need to enable 512 bit to
> + align with the command line behavior. Manually set EVEX512 for this
> + scenario. */
> + if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
> + && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
> + && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
> + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
> + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
> +
> /* If the changed options are different from the default, rerun
> ix86_option_override_internal, and then save the options away.
> The string options are attribute options, and will be undone
> @@ -1421,7 +1441,10 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
> || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
> || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
> || enum_opts_set.x_ix86_fpmath
> - || enum_opts_set.x_prefer_vector_width_type)
> + || enum_opts_set.x_prefer_vector_width_type
> + || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256)
> + && (opts->x_ix86_isa_flags2_explicit
> + & OPTION_MASK_ISA2_AVX10_1_256)))
> {
> /* If we are using the default tune= or arch=, undo the string assigned,
> and use the default. */
> @@ -1963,7 +1986,7 @@ ix86_option_override_internal (bool main_args_p,
> struct gcc_options *opts_set)
> {
> unsigned int i;
> - unsigned HOST_WIDE_INT ix86_arch_mask;
> + unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2;
> const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
>
> /* -mrecip options. */
> @@ -1982,6 +2005,14 @@ ix86_option_override_internal (bool main_args_p,
> { "vec-sqrt", RECIP_MASK_VEC_SQRT },
> };
>
> + avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD
> + | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW
> + | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA
> + | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2
> + | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ
> + | OPTION_MASK_ISA_AVX512BITALG;
> + avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16
> + | OPTION_MASK_ISA2_AVX512BF16;
>
> /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
> TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
> @@ -2590,12 +2621,99 @@ ix86_option_override_internal (bool main_args_p,
> &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
> & ~opts->x_ix86_isa_flags_explicit);
>
> - /* Set EVEX512 target if it is not explicitly set
> - when AVX512 is enabled. */
> - if (TARGET_AVX512F_P(opts->x_ix86_isa_flags)
> - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
> + /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options except
> + for the following option combinations:
> + 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with no
> + explicit disable on other AVX512 features.
> + 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no
> + explicit disable on other AVX512 features.
> + 3. Both AVX10.1 and AVX512 are disabled. */
> + if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2))
> + {
> + if (opts->x_ix86_no_avx512_explicit
> + && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
> + & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
> + || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
> + & opts->x_ix86_isa_flags2)
> + & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
> + & opts->x_ix86_isa_flags2_explicit)))))
> + warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable "
> + "AVX10 instructions when AVX10.1-512 is available");
> + }
> + else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
> + {
> + if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2)
> + && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit))
> + {
> + if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags)
> + || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
> + {
> + /* We should not emit 512 bit instructions under AVX10.1-256
> + when EVEX512 is enabled w/o any AVX512 features enabled.
> + Disable EVEX512 bit for this. */
> + warning (0, "Using %<-mevex512%> without any AVX512 features "
> + "enabled together with AVX10.1 only will not enable "
> + "any AVX512 or AVX10.1-512 features, using 256 as "
> + "max vector size");
> + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512;
> + }
> + else
> + warning (0, "Vector size conflicts between AVX10.1 and AVX512, "
> + "using 512 as max vector size");
> + }
> + else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
> + && !(OPTION_MASK_ISA2_EVEX512
> + & opts->x_ix86_isa_flags2_explicit))
> + warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
> + "512 as max vector size");
> + else if (opts->x_ix86_no_avx512_explicit
> + && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
> + & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
> + || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2)
> + & (avx512_isa_flags2
> + & opts->x_ix86_isa_flags2_explicit)))))
> + warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions "
> + "when AVX10 is available");
> + }
> + else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
> + && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
> + {
> + if (opts->x_ix86_no_avx10_1_explicit
> + && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
> + & opts->x_ix86_isa_flags2_explicit))
> + {
> + warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
> + "cannot disable AVX512 instructions when "
> + "%<-mavx512XXX%>");
> + /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is
> + disabled. */
> + if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit)
> + {
> + opts->x_ix86_isa_flags = (~avx512_isa_flags
> + & opts->x_ix86_isa_flags)
> + | (avx512_isa_flags & opts->x_ix86_isa_flags_explicit);
> + opts->x_ix86_isa_flags2 = (~avx512_isa_flags
> + & opts->x_ix86_isa_flags2)
> + | (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit);
> + }
> + }
> + }
> +
> + /* Set EVEX512 if one of the following conditions meets:
> + 1. AVX512 is enabled while EVEX512 is not explicitly set/unset.
> + 2. AVX10.1-512 is enabled. */
> + if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2)
> + || (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
> + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)))
> opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
>
> + /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */
> + if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
> + {
> + opts->x_ix86_isa_flags |= avx512_isa_flags;
> + opts->x_ix86_isa_flags2 |= avx512_isa_flags2;
> + }
> +
> /* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */
> if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2))
> {
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index a56367a947b..fe264d142f0 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2374,7 +2374,7 @@ constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512
> constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
> constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
> | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
> - | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
> + | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512;
> constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
> | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
> | PTA_RDPID | PTA_AVX512VPOPCNTDQ;
> diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
> index 0c3b8f4b621..b81c968876e 100644
> --- a/gcc/config/i386/i386.opt
> +++ b/gcc/config/i386/i386.opt
> @@ -36,6 +36,13 @@ HOST_WIDE_INT ix86_isa_flags_explicit
> Variable
> HOST_WIDE_INT ix86_isa_flags2_explicit
>
> +; Indicate if AVX512 and AVX10.1 are explicitly set no.
> +Variable
> +int ix86_no_avx512_explicit = 0
> +
> +Variable
> +int ix86_no_avx10_1_explicit = 0
> +
> ; Additional target flags
> Variable
> int ix86_target_flags
> @@ -96,6 +103,14 @@ HOST_WIDE_INT x_ix86_isa_flags2_explicit
> TargetSave
> HOST_WIDE_INT x_ix86_isa_flags_explicit
>
> +;; which flags were passed by the user
> +TargetSave
> +HOST_WIDE_INT x_ix86_no_avx512_explicit
> +
> +;; which flags were passed by the user
> +TargetSave
> +HOST_WIDE_INT x_ix86_no_avx10_1_explicit
> +
> ;; whether -mtune was not specified
> TargetSave
> unsigned char tune_defaulted
> @@ -1348,3 +1363,18 @@ Support 512 bit vector built-in functions and code generation.
> musermsr
> Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save
> Support USER_MSR built-in functions and code generation.
> +
> +mavx10.1-256
> +Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save
> +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
> +and AVX10.1 built-in functions and code generation.
> +
> +mavx10.1-512
> +Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
> +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
> +and AVX10.1-512 built-in functions and code generation.
> +
> +mavx10.1
> +Target Alias(mavx10.1-256)
> +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
> +and AVX10.1 built-in functions and code generation.
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index fa7402813e7..a4ce2f46d85 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -7283,6 +7283,21 @@ Enable/disable the generation of the SM4 instructions.
> @itemx no-usermsr
> Enable/disable the generation of the USER_MSR instructions.
>
> +@cindex @code{target("avx10.1")} function attribute, x86
> +@item avx10.1
> +@itemx no-avx10.1
> +Enable/disable the generation of the AVX10.1 instructions.
> +
> +@cindex @code{target("avx10.1-256")} function attribute, x86
> +@item avx10.1-256
> +@itemx no-avx10.1-256
> +Enable/disable the generation of the AVX10.1 instructions.
> +
> +@cindex @code{target("avx10.1-512")} function attribute, x86
> +@item avx10.1-512
> +@itemx no-avx10.1-512
> +Enable/disable the generation of the AVX10.1 512 bit instructions.
> +
> @cindex @code{target("cld")} function attribute, x86
> @item cld
> @itemx no-cld
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 6e776a0faa1..7b98f93bd6a 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -1449,7 +1449,7 @@ See RS/6000 and PowerPC Options.
> -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
> -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
> -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
> --musermsr
> +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512
> -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
> -minline-stringops-dynamically -mstringop-strategy=@var{alg}
> -mkl -mwidekl
> @@ -34027,6 +34027,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
> @need 200
> @opindex musermsr
> @itemx -musermsr
> +@need 200
> +@opindex mavx10.1
> +@itemx -mavx10.1
> +@need 200
> +@opindex mavx10.1-256
> +@itemx -mavx10.1-256
> +@need 200
> +@opindex mavx10.1-512
> +@itemx -mavx10.1-512
> These switches enable the use of instructions in the MMX, SSE,
> AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
> AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
> @@ -34037,9 +34046,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
> ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
> UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
> AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
> -AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR or CLDEMOTE
> -extended instruction sets. Each has a corresponding @option{-mno-} option
> -to disable use of these instructions.
> +AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR, AVX10.1 or
> +CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-}
> +option to disable use of these instructions.
>
> These extensions are also available as built-in functions: see
> @ref{x86 Built-in Functions}, for details of the functions enabled and
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index c20af31c642..8dfd8435811 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2496,6 +2496,15 @@ Target supports compiling @code{avx} instructions.
> @item avx_runtime
> Target supports the execution of @code{avx} instructions.
>
> +@item avx10.1
> +Target supports the execution of @code{avx10.1} instructions.
> +
> +@item avx10.1-256
> +Target supports the execution of @code{avx10.1} instructions.
> +
> +@item avx10.1-512
> +Target supports the execution of @code{avx10.1-512} instructions.
> +
> @item avx2
> Target supports compiling @code{avx2} instructions.
>
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
> new file mode 100644
> index 00000000000..cfd9662bb13
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
> +
> +#include <immintrin.h>
> +
> +void
> +f1 ()
> +{
> + register __m256d a __asm ("ymm17");
> + register __m256d b __asm ("ymm16");
> + a = _mm256_add_pd (a, b);
> + asm volatile ("" : "+v" (a));
> +}
> +
> +void
> +f2 ()
> +{
> + register __m128d a __asm ("xmm17");
> + register __m128d b __asm ("xmm16");
> + a = _mm_add_pd (a, b);
> + asm volatile ("" : "+v" (a));
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c
> new file mode 100644
> index 00000000000..0db5240a30f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-10.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f -mno-evex512" } */
> +/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c
> new file mode 100644
> index 00000000000..c0ad4fc27fa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-11.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512 -mno-avx512f" } */
> +/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
> new file mode 100644
> index 00000000000..61f0e4db61b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
> +/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
> new file mode 100644
> index 00000000000..8a111190025
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx512f"))) __m512d
> +foo ()
> +{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
> new file mode 100644
> index 00000000000..03222a7a031
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx512f" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx10.1"))) __m512d
> +foo ()
> +{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c
> new file mode 100644
> index 00000000000..d1731f09a45
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-15.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx512f,no-evex512"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c
> new file mode 100644
> index 00000000000..f5f3ff8127e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-16.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx10.1-512"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
> new file mode 100644
> index 00000000000..a19230f597b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx512f" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("no-avx10.1"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c
> new file mode 100644
> index 00000000000..c50fd2bb29b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-18.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("no-avx512f"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
> new file mode 100644
> index 00000000000..7aacc15aad9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx512f"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
> new file mode 100644
> index 00000000000..0b3991dcf74
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__m512d
> +foo ()
> +{
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c
> new file mode 100644
> index 00000000000..d63c6b40d80
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-20.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mno-avx512f" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx10.1-512"))) __m512d
> +foo ()
> +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
> new file mode 100644
> index 00000000000..27a7265df61
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
> +/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
> +/* { dg-final { scan-assembler-not "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
> new file mode 100644
> index 00000000000..796262283d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
> +/* { dg-final { scan-assembler-not "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("evex512"))) __m512d
> +foo ()
> +{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
> new file mode 100644
> index 00000000000..6e8d64d0f34
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */
> +/* { dg-final { scan-assembler-not "%zmm" } } */
> +
> +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
> +
> +__attribute__ ((target ("avx10.1"))) __m512d
> +foo ()
> +{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
> + __m512d a, b;
> + a = a + b;
> + return a;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
> new file mode 100644
> index 00000000000..3be988a1a62
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
> +
> +#include <immintrin.h>
> +
> +int
> +foo (int c)
> +{
> + register int a __asm ("k7") = c;
> + int b = foo (a);
> + asm volatile ("" : "+k" (b));
> + return b;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
> new file mode 100644
> index 00000000000..68cbf197d61
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=x86-64 -mavx10.1-512" } */
> +
> +#include <immintrin.h>
> +
> +long long
> +foo (long long c)
> +{
> + register long long a __asm ("k7") = c;
> + long long b = foo (a);
> + asm volatile ("" : "+k" (b));
> + return b;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
> new file mode 100644
> index 00000000000..20b78ea9510
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
> +/* { dg-final { scan-assembler-not ".%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
> new file mode 100644
> index 00000000000..827c80ce51e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
> +
> +#include <immintrin.h>
> +
> +long long
> +foo (long long c)
> +{
> + register long long a __asm ("k7") = c;
> + long long b = foo (a);
> + asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */
> + return b;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
> new file mode 100644
> index 00000000000..afce2905421
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f" } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
> new file mode 100644
> index 00000000000..69b6c6a3e1a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
> +
> +#include "avx10_1-1.c"
> diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c
> new file mode 100644
> index 00000000000..8e838277962
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx10_1-9.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */
> +/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */
> +/* { dg-final { scan-assembler "%zmm" } } */
> +
> +#include "avx10_1-2.c"
> --
> 2.31.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-11-13 11:25 ` Richard Biener
2023-11-14 2:40 ` Hongtao Liu
@ 2023-12-12 9:05 ` Florian Weimer
2023-12-12 12:14 ` Richard Biener
1 sibling, 1 reply; 11+ messages in thread
From: Florian Weimer @ 2023-12-12 9:05 UTC (permalink / raw)
To: Richard Biener
Cc: Hongtao Liu, Haochen Jiang, gcc-patches, hongtao.liu, ubizjak
* Richard Biener:
> If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5
> that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit
> (and obviously not requiring more of the AVX512 features that v4
> requires).
As far as I understand it, GCC's Intel tuning for AVX-512 is leaning
heavily towards 256 bit vector length anyway. That's not true for the
default tuning for -march=x86-64-v4, though, it prefers 512 bit vectors.
I've seen third-party reports that AMD Zen 4 does better in some ways
with 512 bit vectors than with 256 bit vectors (despite its 256-bit-wide
execution ports), but I have not tried to verify these observations.
Still, this suggests that restricting a post-x86-64-v3 level to 256 bit
vectors may not be an easy decision.
On the other hand, a new EVEX-capable level might bring earlier adoption
of EVEX capabilities to AMD CPUs, which still should be an improvement
over AVX2. This could benefit AMD as well. So I would really like to
see some AMD feedback here.
There's also the matter that time scales for EVEX adoption are so long
that by then, Intel CPUs may end up supporting and preferring 512 bit
vectors again.
Thanks,
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC] Intel AVX10.1 Compiler Design and Support
2023-12-12 9:05 ` Florian Weimer
@ 2023-12-12 12:14 ` Richard Biener
2023-12-13 2:12 ` Jiang, Haochen
0 siblings, 1 reply; 11+ messages in thread
From: Richard Biener @ 2023-12-12 12:14 UTC (permalink / raw)
To: Florian Weimer
Cc: Hongtao Liu, Haochen Jiang, gcc-patches, hongtao.liu, ubizjak
On Tue, Dec 12, 2023 at 10:05 AM Florian Weimer <fweimer@redhat.com> wrote:
>
> * Richard Biener:
>
> > If it were possible I'd axe x86_64-v4. Maybe we should add a x86_64-v3.5
> > that sits inbetween v3 and v4, offering AVX512 but restricted to 256bit
> > (and obviously not requiring more of the AVX512 features that v4
> > requires).
>
> As far as I understand it, GCC's Intel tuning for AVX-512 is leaning
> heavily towards 256 bit vector length anyway.
Indeed it does, enabling avx256_optimal everywhere, but enabling
512bit moves on Sapphire Rapids (and not Granite Rapids!?).
> That's not true for the
> default tuning for -march=x86-64-v4, though, it prefers 512 bit vectors.
> I've seen third-party reports that AMD Zen 4 does better in some ways
> with 512 bit vectors than with 256 bit vectors (despite its 256-bit-wide
> execution ports), but I have not tried to verify these observations.
> Still, this suggests that restricting a post-x86-64-v3 level to 256 bit
> vectors may not be an easy decision.
The corner Intel painted itself to be in is that their small cores on the
hybrid consumer products only support 128bit native (256bit emulated)
and their data-center "small core" SKU doesn't fare any better there.
That's the reason their marketing invented AVX10 which will allow
the AVX512 ISA play "nice" with a smaller data path (but I'm sure, or
at least I hope, that actual implementations will have a native 256bit
data path and not emulate it via 128bit).
The current problem is that the castrated consumer SKUs cannot use
EVEX at all and in the future will be crippled to 256bits. So that will
be the common thing to target when targeting EVEX support across
Intel/AMD - use 256bit only. Note that AVX10 excludes Zen4 which
lacks support for two niche AVX512 ISA extensions.
> On the other hand, a new EVEX-capable level might bring earlier adoption
> of EVEX capabilities to AMD CPUs, which still should be an improvement
> over AVX2. This could benefit AMD as well. So I would really like to
> see some AMD feedback here.
>
> There's also the matter that time scales for EVEX adoption are so long
> that by then, Intel CPUs may end up supporting and preferring 512 bit
> vectors again.
True, there isn't even widespread VEX adoption yet ... and now there's
APX as the next best thing to target.
That said, my main point was that x86-64-v4 is "broken" as it appears
as a dead end - AVX512 is no more, the future is AVX10, but yet we have
to define x86-64-v5 as something that includes x86-64-v4.
So, can we un-do x86-64-v4?
Richard.
> Thanks,
> Florian
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [RFC] Intel AVX10.1 Compiler Design and Support
2023-12-12 12:14 ` Richard Biener
@ 2023-12-13 2:12 ` Jiang, Haochen
0 siblings, 0 replies; 11+ messages in thread
From: Jiang, Haochen @ 2023-12-13 2:12 UTC (permalink / raw)
To: Richard Biener, Florian Weimer
Cc: Hongtao Liu, gcc-patches, Liu, Hongtao, ubizjak
> > On the other hand, a new EVEX-capable level might bring earlier adoption
> > of EVEX capabilities to AMD CPUs, which still should be an improvement
> > over AVX2. This could benefit AMD as well. So I would really like to
> > see some AMD feedback here.
> >
> > There's also the matter that time scales for EVEX adoption are so long
> > that by then, Intel CPUs may end up supporting and preferring 512 bit
> > vectors again.
>
> True, there isn't even widespread VEX adoption yet ... and now there's
> APX as the next best thing to target.
>
> That said, my main point was that x86-64-v4 is "broken" as it appears
> as a dead end - AVX512 is no more, the future is AVX10, but yet we have
> to define x86-64-v5 as something that includes x86-64-v4.
>
> So, can we un-do x86-64-v4?
As far as I have heard, x86-64-v4 is rarely used. There should be a small
chance to un-do that and not to break too many things. But I am not sure.
Thx,
Haochen
>
> Richard.
>
> > Thanks,
> > Florian
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
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2023-11-10 1:41 [RFC] Intel AVX10.1 Compiler Design and Support Haochen Jiang
2023-11-10 1:41 ` [PATCH] Initial support for AVX10.1 Haochen Jiang
2023-11-20 6:34 ` Hongtao Liu
2023-11-10 10:15 ` [RFC] Intel AVX10.1 Compiler Design and Support Richard Biener
2023-11-13 7:07 ` Hongtao Liu
2023-11-13 11:25 ` Richard Biener
2023-11-14 2:40 ` Hongtao Liu
2023-11-14 6:25 ` Jiang, Haochen
2023-12-12 9:05 ` Florian Weimer
2023-12-12 12:14 ` Richard Biener
2023-12-13 2:12 ` Jiang, Haochen
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