* [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
@ 2023-07-14 13:20 pan2.li
2023-07-18 1:09 ` juzhe.zhong
2023-07-18 2:49 ` [PATCH v2] " pan2.li
0 siblings, 2 replies; 6+ messages in thread
From: pan2.li @ 2023-07-14 13:20 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure
on RV32.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 58 ++++++++++---------
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 210c49c5e8d..1d90b4f50d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FRM_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define CALL_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -31,40 +49,22 @@ set_frm (int frm)
);
}
-static inline void
+void __attribute__ ((noinline)) \
assert_equal (int a, int b, char *message)
{
if (a != b)
{
- printf (message);
+ fprintf (stdout, message);
+ fflush (stdout);
__builtin_abort ();
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- set_frm (0);
-
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FRM_FUNC (0)
+DEFINE_TEST_FRM_FUNC (1)
+DEFINE_TEST_FRM_FUNC (2)
+DEFINE_TEST_FRM_FUNC (3)
+DEFINE_TEST_FRM_FUNC (4)
int
main ()
@@ -73,7 +73,11 @@ main ()
vfloat32m1_t op1;
vfloat32m1_t op2;
- test_float_point_frm_run (op1, op2, vl);
+ CALL_TEST_FUNC (0, op1, op2, vl);
+ CALL_TEST_FUNC (1, op1, op2, vl);
+ CALL_TEST_FUNC (2, op1, op2, vl);
+ CALL_TEST_FUNC (3, op1, op2, vl);
+ CALL_TEST_FUNC (4, op1, op2, vl);
return 0;
}
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
2023-07-14 13:20 [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 pan2.li
@ 2023-07-18 1:09 ` juzhe.zhong
2023-07-18 2:52 ` Li, Pan2
2023-07-18 2:49 ` [PATCH v2] " pan2.li
1 sibling, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-07-18 1:09 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3852 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-07-14 21:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li <pan2.li@intel.com>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure
on RV32.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 58 ++++++++++---------
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 210c49c5e8d..1d90b4f50d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FRM_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define CALL_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -31,40 +49,22 @@ set_frm (int frm)
);
}
-static inline void
+void __attribute__ ((noinline)) \
assert_equal (int a, int b, char *message)
{
if (a != b)
{
- printf (message);
+ fprintf (stdout, message);
+ fflush (stdout);
__builtin_abort ();
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- set_frm (0);
-
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FRM_FUNC (0)
+DEFINE_TEST_FRM_FUNC (1)
+DEFINE_TEST_FRM_FUNC (2)
+DEFINE_TEST_FRM_FUNC (3)
+DEFINE_TEST_FRM_FUNC (4)
int
main ()
@@ -73,7 +73,11 @@ main ()
vfloat32m1_t op1;
vfloat32m1_t op2;
- test_float_point_frm_run (op1, op2, vl);
+ CALL_TEST_FUNC (0, op1, op2, vl);
+ CALL_TEST_FUNC (1, op1, op2, vl);
+ CALL_TEST_FUNC (2, op1, op2, vl);
+ CALL_TEST_FUNC (3, op1, op2, vl);
+ CALL_TEST_FUNC (4, op1, op2, vl);
return 0;
}
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
2023-07-14 13:20 [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 pan2.li
2023-07-18 1:09 ` juzhe.zhong
@ 2023-07-18 2:49 ` pan2.li
2023-07-18 2:53 ` juzhe.zhong
1 sibling, 1 reply; 6+ messages in thread
From: pan2.li @ 2023-07-18 2:49 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 59 +++++++++++--------
1 file changed, 36 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 245ce7d1fc0..1b2789a924b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define RUN_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -41,28 +59,11 @@ assert_equal (int a, int b, char *message)
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FUNC (0)
+DEFINE_TEST_FUNC (1)
+DEFINE_TEST_FUNC (2)
+DEFINE_TEST_FUNC (3)
+DEFINE_TEST_FUNC (4)
int
main ()
@@ -72,8 +73,20 @@ main ()
vfloat32m1_t op2;
set_frm (4);
- test_float_point_frm_run (op1, op2, vl);
+ RUN_TEST_FUNC (0, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (1, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (2, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (3, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (4, op1, op2, vl);
assert_equal (4, get_frm (), "The value of frm register should be 4.");
return 0;
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
2023-07-18 1:09 ` juzhe.zhong
@ 2023-07-18 2:52 ` Li, Pan2
0 siblings, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-07-18 2:52 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 4631 bytes --]
Thanks Juzhe, addressed conflict and passed RV32/RV64 tests with below PATCH v2.
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624723.html
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Tuesday, July 18, 2023 9:09 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
LGTM
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-07-14 21:20
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure
on RV32.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 58 ++++++++++---------
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 210c49c5e8d..1d90b4f50d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FRM_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define CALL_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -31,40 +49,22 @@ set_frm (int frm)
);
}
-static inline void
+void __attribute__ ((noinline)) \
assert_equal (int a, int b, char *message)
{
if (a != b)
{
- printf (message);
+ fprintf (stdout, message);
+ fflush (stdout);
__builtin_abort ();
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- set_frm (0);
-
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FRM_FUNC (0)
+DEFINE_TEST_FRM_FUNC (1)
+DEFINE_TEST_FRM_FUNC (2)
+DEFINE_TEST_FRM_FUNC (3)
+DEFINE_TEST_FRM_FUNC (4)
int
main ()
@@ -73,7 +73,11 @@ main ()
vfloat32m1_t op1;
vfloat32m1_t op2;
- test_float_point_frm_run (op1, op2, vl);
+ CALL_TEST_FUNC (0, op1, op2, vl);
+ CALL_TEST_FUNC (1, op1, op2, vl);
+ CALL_TEST_FUNC (2, op1, op2, vl);
+ CALL_TEST_FUNC (3, op1, op2, vl);
+ CALL_TEST_FUNC (4, op1, op2, vl);
return 0;
}
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
2023-07-18 2:49 ` [PATCH v2] " pan2.li
@ 2023-07-18 2:53 ` juzhe.zhong
2023-07-18 3:04 ` Li, Pan2
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-07-18 2:53 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3955 bytes --]
LGTM.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-07-18 10:49
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li <pan2.li@intel.com>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 59 +++++++++++--------
1 file changed, 36 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 245ce7d1fc0..1b2789a924b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define RUN_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -41,28 +59,11 @@ assert_equal (int a, int b, char *message)
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FUNC (0)
+DEFINE_TEST_FUNC (1)
+DEFINE_TEST_FUNC (2)
+DEFINE_TEST_FUNC (3)
+DEFINE_TEST_FUNC (4)
int
main ()
@@ -72,8 +73,20 @@ main ()
vfloat32m1_t op2;
set_frm (4);
- test_float_point_frm_run (op1, op2, vl);
+ RUN_TEST_FUNC (0, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (1, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (2, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (3, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (4, op1, op2, vl);
assert_equal (4, get_frm (), "The value of frm register should be 4.");
return 0;
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
2023-07-18 2:53 ` juzhe.zhong
@ 2023-07-18 3:04 ` Li, Pan2
0 siblings, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-07-18 3:04 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 4612 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Tuesday, July 18, 2023 10:53 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
LGTM.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-07-18 10:49
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure.
---
.../riscv/rvv/base/float-point-frm-run-1.c | 59 +++++++++++--------
1 file changed, 36 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 245ce7d1fc0..1b2789a924b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include <stdio.h>
#include <stdint-gcc.h>
+#define DEFINE_TEST_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \
+{ \
+ vfloat32m1_t result; \
+ \
+ set_frm (0); \
+ \
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \
+ \
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \
+ \
+ return result; \
+}
+
+#define RUN_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -41,28 +59,11 @@ assert_equal (int a, int b, char *message)
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FUNC (0)
+DEFINE_TEST_FUNC (1)
+DEFINE_TEST_FUNC (2)
+DEFINE_TEST_FUNC (3)
+DEFINE_TEST_FUNC (4)
int
main ()
@@ -72,8 +73,20 @@ main ()
vfloat32m1_t op2;
set_frm (4);
- test_float_point_frm_run (op1, op2, vl);
+ RUN_TEST_FUNC (0, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (1, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (2, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (3, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (4, op1, op2, vl);
assert_equal (4, get_frm (), "The value of frm register should be 4.");
return 0;
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-07-18 3:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-07-14 13:20 [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 pan2.li
2023-07-18 1:09 ` juzhe.zhong
2023-07-18 2:52 ` Li, Pan2
2023-07-18 2:49 ` [PATCH v2] " pan2.li
2023-07-18 2:53 ` juzhe.zhong
2023-07-18 3:04 ` Li, Pan2
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