* [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal.
@ 2023-03-29 7:52 pan2.li
2023-03-29 8:10 ` Richard Biener
2023-03-29 8:53 ` [PATCH v2] RISC-V: " pan2.li
0 siblings, 2 replies; 15+ messages in thread
From: pan2.li @ 2023-03-29 7:52 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, rguenther, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
In most architecture the precision_size of vbool*_t types are caculated
like as the multiple of the type size. For example:
precision_size = type_size * 8 (aka, bit count per bytes).
Unfortunately, some architecture like RISC-V will adjust the precision_size
for the vbool*_t in order to align the ISA. For example as below.
type_size = [1, 1, 1, 1, 2, 4, 8]
precision_size = [1, 2, 4, 8, 16, 32, 64]
Then the precision_size of RISC-V vbool*_t will not be the multiple of the
type_size. This PATCH try to enrich this case when comparing the vn_reference.
Given we have the below code:
void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
vbool8_t v1 = *(vbool8_t*)in;
vbool16_t v2 = *(vbool16_t*)in;
*(vbool8_t*)(out + 100) = v1;
*(vbool16_t*)(out + 200) = v2;
}
Before this PATCH:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m1,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf2,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After this PATCH:
addi a3,a1,100
vsetvli a4,zero,e8,m1,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf2,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
PR 109272
gcc/ChangeLog:
* tree-ssa-sccvn.cc (vn_reference_eq):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-4.c:
* gcc.target/riscv/rvv/base/pr108185-5.c:
* gcc.target/riscv/rvv/base/pr108185-6.c:
---
.../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
gcc/tree-ssa-sccvn.cc | 13 +++++++++++++
4 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index ea3c360d756..e70284fada8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 9fc659d2402..575a7842cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 98275e5267d..95a11d37016 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 6b8d38b270c..c6dfa8fd9a3 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -799,6 +799,19 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
&& (TYPE_PRECISION (vr2->type)
!= TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
return false;
+ else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
+ && VECTOR_BOOLEAN_TYPE_P (vr2->type)
+ && expressions_equal_p (TYPE_SIZE (vr1->type),
+ TYPE_SIZE (vr2->type))
+ && TYPE_PRECISION (vr1->type) != TYPE_PRECISION (vr2->type))
+ /* For the vbool*_t types in most architectures, the precision size is
+ caculated as the multiple of the type size. For example,
+ precision_size = type_size * 8 (aka, bit count per bytes).
+ Unfortunately, some architecture like RISC-V will adjust the
+ precision for the vbool*_t in order to align the ISA and the
+ precision will not be the multiple of the type size. Thus, enrich
+ the type comparation for this case here. */
+ return false;
i = 0;
j = 0;
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 7:52 [PATCH] [RISC-V]: " pan2.li
@ 2023-03-29 8:10 ` Richard Biener
2023-03-29 8:56 ` Li, Pan2
2023-03-29 8:53 ` [PATCH v2] RISC-V: " pan2.li
1 sibling, 1 reply; 15+ messages in thread
From: Richard Biener @ 2023-03-29 8:10 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, kito.cheng, rguenther, yanzhang.wang
On Wed, Mar 29, 2023 at 9:55 AM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the precision_size
> for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of the
> type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
>
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 13 +++++++++++++
> 4 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> index 6b8d38b270c..c6dfa8fd9a3 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,19 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type)
> + && expressions_equal_p (TYPE_SIZE (vr1->type),
> + TYPE_SIZE (vr2->type))
> + && TYPE_PRECISION (vr1->type) != TYPE_PRECISION (vr2->type))
> + /* For the vbool*_t types in most architectures, the precision size is
> + caculated as the multiple of the type size. For example,
> + precision_size = type_size * 8 (aka, bit count per bytes).
> + Unfortunately, some architecture like RISC-V will adjust the
> + precision for the vbool*_t in order to align the ISA and the
> + precision will not be the multiple of the type size. Thus, enrich
> + the type comparation for this case here. */
> + return false;
I would prefer if you write it cheaper, like
else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
&& VECTOR_BOOLEAN_TYPE_P (vr2->type))
{
/* Vector boolean types can have padding, verify we are dealing with
the same number of elements. */
if (TYPE_VECTOR_SUBPARTS (vr1->type) != TYPE_VECTOR_SUBPARTS
(vr2->type))
return false;
}
there is IMHO no reason to compare TYPE_SIZE again.
Richard.
>
> i = 0;
> j = 0;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 7:52 [PATCH] [RISC-V]: " pan2.li
2023-03-29 8:10 ` Richard Biener
@ 2023-03-29 8:53 ` pan2.li
2023-03-29 9:24 ` Richard Biener
1 sibling, 1 reply; 15+ messages in thread
From: pan2.li @ 2023-03-29 8:53 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, rguenther, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
In most architecture the precision_size of vbool*_t types are caculated
like as the multiple of the type size. For example:
precision_size = type_size * 8 (aka, bit count per bytes).
Unfortunately, some architecture like RISC-V will adjust the precision_size
for the vbool*_t in order to align the ISA. For example as below.
type_size = [1, 1, 1, 1, 2, 4, 8]
precision_size = [1, 2, 4, 8, 16, 32, 64]
Then the precision_size of RISC-V vbool*_t will not be the multiple of the
type_size. This PATCH try to enrich this case when comparing the vn_reference.
Given we have the below code:
void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
vbool8_t v1 = *(vbool8_t*)in;
vbool16_t v2 = *(vbool16_t*)in;
*(vbool8_t*)(out + 100) = v1;
*(vbool16_t*)(out + 200) = v2;
}
Before this PATCH:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m1,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf2,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After this PATCH:
addi a3,a1,100
vsetvli a4,zero,e8,m1,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf2,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
PR 109272
gcc/ChangeLog:
* tree-ssa-sccvn.cc (vn_reference_eq):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-4.c:
* gcc.target/riscv/rvv/base/pr108185-5.c:
* gcc.target/riscv/rvv/base/pr108185-6.c:
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index ea3c360d756..e70284fada8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 9fc659d2402..575a7842cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 98275e5267d..95a11d37016 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 6b8d38b270c..567df3cb2c6 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
&& (TYPE_PRECISION (vr2->type)
!= TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
return false;
+ else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
+ && VECTOR_BOOLEAN_TYPE_P (vr2->type))
+ {
+ /* Vector boolean types can have padding, verify we are dealing with
+ the same number of elements, aka the precision of the types.
+ For example, In most architecture the precision_size of vbool*_t
+ types are caculated like below:
+ precision_size = type_size * 8
+
+ Unfortunately, the RISC-V will adjust the precision_size for the
+ vbool*_t in order to align the ISA as below:
+ type_size = [1, 1, 1, 1, 2, 4, 8]
+ precision_size = [1, 2, 4, 8, 16, 32, 64]
+
+ Then the precision_size of RISC-V vbool*_t will not be the multiple
+ of the type_size. We take care of this case consolidated here. */
+ if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
+ TYPE_VECTOR_SUBPARTS (vr2->type)))
+ return false;
+ }
i = 0;
j = 0;
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 8:10 ` Richard Biener
@ 2023-03-29 8:56 ` Li, Pan2
0 siblings, 0 replies; 15+ messages in thread
From: Li, Pan2 @ 2023-03-29 8:56 UTC (permalink / raw)
To: Richard Biener
Cc: gcc-patches, juzhe.zhong, kito.cheng, rguenther, Wang, Yanzhang
Thank you Biener for the professional suggestion. That make it more clean and simple, and update the PATCH v2 for this already.
Pan
-----Original Message-----
From: Richard Biener <richard.guenther@gmail.com>
Sent: Wednesday, March 29, 2023 4:10 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; rguenther@suse.de; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal.
On Wed, Mar 29, 2023 at 9:55 AM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> In most architecture the precision_size of vbool*_t types are
> caculated like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the
> precision_size for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of
> the type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
>
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 13 +++++++++++++
> 4 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> 6b8d38b270c..c6dfa8fd9a3 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,19 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type)
> + && expressions_equal_p (TYPE_SIZE (vr1->type),
> + TYPE_SIZE (vr2->type))
> + && TYPE_PRECISION (vr1->type) != TYPE_PRECISION (vr2->type))
> + /* For the vbool*_t types in most architectures, the precision size is
> + caculated as the multiple of the type size. For example,
> + precision_size = type_size * 8 (aka, bit count per bytes).
> + Unfortunately, some architecture like RISC-V will adjust the
> + precision for the vbool*_t in order to align the ISA and the
> + precision will not be the multiple of the type size. Thus, enrich
> + the type comparation for this case here. */
> + return false;
I would prefer if you write it cheaper, like
else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
&& VECTOR_BOOLEAN_TYPE_P (vr2->type))
{
/* Vector boolean types can have padding, verify we are dealing with
the same number of elements. */
if (TYPE_VECTOR_SUBPARTS (vr1->type) != TYPE_VECTOR_SUBPARTS
(vr2->type))
return false;
}
there is IMHO no reason to compare TYPE_SIZE again.
Richard.
>
> i = 0;
> j = 0;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 8:53 ` [PATCH v2] RISC-V: " pan2.li
@ 2023-03-29 9:24 ` Richard Biener
2023-03-29 9:35 ` juzhe.zhong
0 siblings, 1 reply; 15+ messages in thread
From: Richard Biener @ 2023-03-29 9:24 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, kito.cheng, yanzhang.wang
On Wed, 29 Mar 2023, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the precision_size
> for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of the
> type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
OK if this passes bootstrap / regtest.
Thanks,
Richard.
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> index 6b8d38b270c..567df3cb2c6 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing with
> + the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the multiple
> + of the type_size. We take care of this case consolidated here. */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type)))
> + return false;
> + }
>
> i = 0;
> j = 0;
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 9:24 ` Richard Biener
@ 2023-03-29 9:35 ` juzhe.zhong
2023-03-29 10:38 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: juzhe.zhong @ 2023-03-29 9:35 UTC (permalink / raw)
To: rguenther, pan2.li; +Cc: gcc-patches, Kito.cheng, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 6810 bytes --]
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
juzhe.zhong@rivai.ai
From: Richard Biener
Date: 2023-03-29 17:24
To: pan2.li
CC: gcc-patches; juzhe.zhong; kito.cheng; yanzhang.wang
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
On Wed, 29 Mar 2023, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the precision_size
> for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of the
> type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
OK if this passes bootstrap / regtest.
Thanks,
Richard.
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> index 6b8d38b270c..567df3cb2c6 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing with
> + the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the multiple
> + of the type_size. We take care of this case consolidated here. */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type)))
> + return false;
> + }
>
> i = 0;
> j = 0;
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 9:35 ` juzhe.zhong
@ 2023-03-29 10:38 ` Li, Pan2
2023-04-20 13:56 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: Li, Pan2 @ 2023-03-29 10:38 UTC (permalink / raw)
To: juzhe.zhong, rguenther; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 7542 bytes --]
Cool. Thank you all for this, have a nice day!
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, March 29, 2023 5:35 PM
To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Richard Biener<mailto:rguenther@suse.de>
Date: 2023-03-29 17:24
To: pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
> From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the precision_size
> for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of the
> type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
OK if this passes bootstrap / regtest.
Thanks,
Richard.
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> index 6b8d38b270c..567df3cb2c6 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing with
> + the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the multiple
> + of the type_size. We take care of this case consolidated here. */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type)))
> + return false;
> + }
>
> i = 0;
> j = 0;
>
--
Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-03-29 10:38 ` Li, Pan2
@ 2023-04-20 13:56 ` Li, Pan2
2023-04-24 11:13 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: Li, Pan2 @ 2023-04-20 13:56 UTC (permalink / raw)
To: kito.cheng; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang, juzhe.zhong
Hi Kito,
There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it?
Pann
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
Sent: Wednesday, March 29, 2023 6:39 PM
To: juzhe.zhong@rivai.ai; rguenther <rguenther@suse.de>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Cool. Thank you all for this, have a nice day!
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, March 29, 2023 5:35 PM
To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Richard Biener<mailto:rguenther@suse.de>
Date: 2023-03-29 17:24
To: pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
> From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
>
> In most architecture the precision_size of vbool*_t types are
> caculated like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the
> precision_size for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of
> the type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
OK if this passes bootstrap / regtest.
Thanks,
Richard.
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> 6b8d38b270c..567df3cb2c6 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing
> + with the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the multiple
> + of the type_size. We take care of this case consolidated here. */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type))) return false;
> + }
>
> i = 0;
> j = 0;
>
--
Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-04-20 13:56 ` Li, Pan2
@ 2023-04-24 11:13 ` Li, Pan2
2023-04-25 14:05 ` Kito Cheng
0 siblings, 1 reply; 15+ messages in thread
From: Li, Pan2 @ 2023-04-24 11:13 UTC (permalink / raw)
To: kito.cheng; +Cc: gcc-patches, Kito.cheng, Wang, Yanzhang, juzhe.zhong
Hi,
Just synced this patch with upstream, and passed the X86 bootstrap and regression test already.
Pan
-----Original Message-----
From: Li, Pan2
Sent: Thursday, April 20, 2023 9:57 PM
To: kito.cheng@sifive.com
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; juzhe.zhong@rivai.ai
Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Hi Kito,
There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it?
Pann
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
Sent: Wednesday, March 29, 2023 6:39 PM
To: juzhe.zhong@rivai.ai; rguenther <rguenther@suse.de>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Cool. Thank you all for this, have a nice day!
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, March 29, 2023 5:35 PM
To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Thanks Richard && Pan.
Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Richard Biener<mailto:rguenther@suse.de>
Date: 2023-03-29 17:24
To: pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
> From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
>
> In most architecture the precision_size of vbool*_t types are
> caculated like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the
> precision_size for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of
> the type_size. This PATCH try to enrich this case when comparing the vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
OK if this passes bootstrap / regtest.
Thanks,
Richard.
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c:
> * gcc.target/riscv/rvv/base/pr108185-5.c:
> * gcc.target/riscv/rvv/base/pr108185-6.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index ea3c360d756..e70284fada8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> 6b8d38b270c..567df3cb2c6 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing
> + with the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the multiple
> + of the type_size. We take care of this case consolidated here. */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type))) return false;
> + }
>
> i = 0;
> j = 0;
>
--
Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-04-24 11:13 ` Li, Pan2
@ 2023-04-25 14:05 ` Kito Cheng
2023-04-25 14:10 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2023-04-25 14:05 UTC (permalink / raw)
To: Li, Pan2; +Cc: kito.cheng, gcc-patches, Wang, Yanzhang, juzhe.zhong
Plz write description for every item in changelog, otherwise the gcc
git hook will reject this patch.
remote: *** The following commit was rejected by your
hooks.commit-extra-checker script (status: 1)
remote: *** commit: 2777f46a58af65be380a2f44bf5cdf93e2d11886
remote: *** ChangeLog format failed:
remote: *** ERR: missing description of a change: " *
tree-ssa-sccvn.cc (vn_reference_eq):"
remote: ***
remote: *** Please see: https://gcc.gnu.org/codingconventions.html#ChangeLogs
remote: ***
remote: error: hook declined to update refs/heads/master
On Mon, Apr 24, 2023 at 7:14 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi,
>
> Just synced this patch with upstream, and passed the X86 bootstrap and regression test already.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Thursday, April 20, 2023 9:57 PM
> To: kito.cheng@sifive.com
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; juzhe.zhong@rivai.ai
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Hi Kito,
>
> There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it?
>
> Pann
>
> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
> Sent: Wednesday, March 29, 2023 6:39 PM
> To: juzhe.zhong@rivai.ai; rguenther <rguenther@suse.de>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Cool. Thank you all for this, have a nice day!
>
> Pan
>
> From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> Sent: Wednesday, March 29, 2023 5:35 PM
> To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Thanks Richard && Pan.
>
> Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
>
> ________________________________
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
>
> From: Richard Biener<mailto:rguenther@suse.de>
> Date: 2023-03-29 17:24
> To: pan2.li<mailto:pan2.li@intel.com>
> CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
> Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
> On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
>
> > From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> >
> > In most architecture the precision_size of vbool*_t types are
> > caculated like as the multiple of the type size. For example:
> > precision_size = type_size * 8 (aka, bit count per bytes).
> >
> > Unfortunately, some architecture like RISC-V will adjust the
> > precision_size for the vbool*_t in order to align the ISA. For example as below.
> > type_size = [1, 1, 1, 1, 2, 4, 8]
> > precision_size = [1, 2, 4, 8, 16, 32, 64]
> >
> > Then the precision_size of RISC-V vbool*_t will not be the multiple of
> > the type_size. This PATCH try to enrich this case when comparing the vn_reference.
> >
> > Given we have the below code:
> > void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> > vbool8_t v1 = *(vbool8_t*)in;
> > vbool16_t v2 = *(vbool16_t*)in;
> >
> > *(vbool8_t*)(out + 100) = v1;
> > *(vbool16_t*)(out + 200) = v2;
> > }
> >
> > Before this PATCH:
> > csrr t0,vlenb
> > slli t1,t0,1
> > csrr a3,vlenb
> > sub sp,sp,t1
> > slli a4,a3,1
> > add a4,a4,sp
> > addi a2,a1,100
> > vsetvli a5,zero,e8,m1,ta,ma
> > sub a3,a4,a3
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a2)
> > vsm.v v24,0(a3)
> > addi a1,a1,200
> > csrr t0,vlenb
> > vsetvli a4,zero,e8,mf2,ta,ma
> > slli t1,t0,1
> > vlm.v v24,0(a3)
> > vsm.v v24,0(a1)
> > add sp,sp,t1
> > jr ra
> >
> > After this PATCH:
> > addi a3,a1,100
> > vsetvli a4,zero,e8,m1,ta,ma
> > addi a1,a1,200
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a3)
> > vsetvli a5,zero,e8,mf2,ta,ma
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a1)
> > ret
>
> OK if this passes bootstrap / regtest.
>
> Thanks,
> Richard.
>
> > PR 109272
> >
> > gcc/ChangeLog:
> >
> > * tree-ssa-sccvn.cc (vn_reference_eq):
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/pr108185-4.c:
> > * gcc.target/riscv/rvv/base/pr108185-5.c:
> > * gcc.target/riscv/rvv/base/pr108185-6.c:
> >
> > Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > ---
> > .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> > gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> > 4 files changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > index ea3c360d756..e70284fada8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > index 9fc659d2402..575a7842cdf 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > index 98275e5267d..95a11d37016 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> > 6b8d38b270c..567df3cb2c6 100644
> > --- a/gcc/tree-ssa-sccvn.cc
> > +++ b/gcc/tree-ssa-sccvn.cc
> > @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> > && (TYPE_PRECISION (vr2->type)
> > != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> > return false;
> > + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> > + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> > + {
> > + /* Vector boolean types can have padding, verify we are dealing
> > + with the same number of elements, aka the precision of the types.
> > + For example, In most architecture the precision_size of vbool*_t
> > + types are caculated like below:
> > + precision_size = type_size * 8
> > +
> > + Unfortunately, the RISC-V will adjust the precision_size for the
> > + vbool*_t in order to align the ISA as below:
> > + type_size = [1, 1, 1, 1, 2, 4, 8]
> > + precision_size = [1, 2, 4, 8, 16, 32, 64]
> > +
> > + Then the precision_size of RISC-V vbool*_t will not be the multiple
> > + of the type_size. We take care of this case consolidated here. */
> > + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> > + TYPE_VECTOR_SUBPARTS (vr2->type))) return false;
> > + }
> >
> > i = 0;
> > j = 0;
> >
>
> --
> Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
> SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-04-25 14:05 ` Kito Cheng
@ 2023-04-25 14:10 ` Li, Pan2
2023-04-25 14:31 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: Li, Pan2 @ 2023-04-25 14:10 UTC (permalink / raw)
To: Kito Cheng; +Cc: kito.cheng, gcc-patches, Wang, Yanzhang, juzhe.zhong
Oh, I see. This PATCH month drafted ago and missed that part. Sorry for inconvenient and will update it ASAP.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Tuesday, April 25, 2023 10:05 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: kito.cheng@sifive.com; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; juzhe.zhong@rivai.ai
Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Plz write description for every item in changelog, otherwise the gcc git hook will reject this patch.
remote: *** The following commit was rejected by your hooks.commit-extra-checker script (status: 1)
remote: *** commit: 2777f46a58af65be380a2f44bf5cdf93e2d11886
remote: *** ChangeLog format failed:
remote: *** ERR: missing description of a change: " *
tree-ssa-sccvn.cc (vn_reference_eq):"
remote: ***
remote: *** Please see: https://gcc.gnu.org/codingconventions.html#ChangeLogs
remote: ***
remote: error: hook declined to update refs/heads/master
On Mon, Apr 24, 2023 at 7:14 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Hi,
>
> Just synced this patch with upstream, and passed the X86 bootstrap and regression test already.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Thursday, April 20, 2023 9:57 PM
> To: kito.cheng@sifive.com
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>;
> juzhe.zhong@rivai.ai
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Hi Kito,
>
> There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it?
>
> Pann
>
> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org>
> On Behalf Of Li, Pan2 via Gcc-patches
> Sent: Wednesday, March 29, 2023 6:39 PM
> To: juzhe.zhong@rivai.ai; rguenther <rguenther@suse.de>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Cool. Thank you all for this, have a nice day!
>
> Pan
>
> From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> Sent: Wednesday, March 29, 2023 5:35 PM
> To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Thanks Richard && Pan.
>
> Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
>
> ________________________________
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
>
> From: Richard Biener<mailto:rguenther@suse.de>
> Date: 2023-03-29 17:24
> To: pan2.li<mailto:pan2.li@intel.com>
> CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>;
> juzhe.zhong<mailto:juzhe.zhong@rivai.ai>;
> kito.cheng<mailto:kito.cheng@sifive.com>;
> yanzhang.wang<mailto:yanzhang.wang@intel.com>
> Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
> On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
>
> > From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> >
> > In most architecture the precision_size of vbool*_t types are
> > caculated like as the multiple of the type size. For example:
> > precision_size = type_size * 8 (aka, bit count per bytes).
> >
> > Unfortunately, some architecture like RISC-V will adjust the
> > precision_size for the vbool*_t in order to align the ISA. For example as below.
> > type_size = [1, 1, 1, 1, 2, 4, 8]
> > precision_size = [1, 2, 4, 8, 16, 32, 64]
> >
> > Then the precision_size of RISC-V vbool*_t will not be the multiple
> > of the type_size. This PATCH try to enrich this case when comparing the vn_reference.
> >
> > Given we have the below code:
> > void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> > vbool8_t v1 = *(vbool8_t*)in;
> > vbool16_t v2 = *(vbool16_t*)in;
> >
> > *(vbool8_t*)(out + 100) = v1;
> > *(vbool16_t*)(out + 200) = v2;
> > }
> >
> > Before this PATCH:
> > csrr t0,vlenb
> > slli t1,t0,1
> > csrr a3,vlenb
> > sub sp,sp,t1
> > slli a4,a3,1
> > add a4,a4,sp
> > addi a2,a1,100
> > vsetvli a5,zero,e8,m1,ta,ma
> > sub a3,a4,a3
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a2)
> > vsm.v v24,0(a3)
> > addi a1,a1,200
> > csrr t0,vlenb
> > vsetvli a4,zero,e8,mf2,ta,ma
> > slli t1,t0,1
> > vlm.v v24,0(a3)
> > vsm.v v24,0(a1)
> > add sp,sp,t1
> > jr ra
> >
> > After this PATCH:
> > addi a3,a1,100
> > vsetvli a4,zero,e8,m1,ta,ma
> > addi a1,a1,200
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a3)
> > vsetvli a5,zero,e8,mf2,ta,ma
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a1)
> > ret
>
> OK if this passes bootstrap / regtest.
>
> Thanks,
> Richard.
>
> > PR 109272
> >
> > gcc/ChangeLog:
> >
> > * tree-ssa-sccvn.cc (vn_reference_eq):
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/pr108185-4.c:
> > * gcc.target/riscv/rvv/base/pr108185-5.c:
> > * gcc.target/riscv/rvv/base/pr108185-6.c:
> >
> > Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > ---
> > .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> > gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> > 4 files changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > index ea3c360d756..e70284fada8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > index 9fc659d2402..575a7842cdf 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > index 98275e5267d..95a11d37016 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> > 6b8d38b270c..567df3cb2c6 100644
> > --- a/gcc/tree-ssa-sccvn.cc
> > +++ b/gcc/tree-ssa-sccvn.cc
> > @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> > && (TYPE_PRECISION (vr2->type)
> > != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> > return false;
> > + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> > + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> > + {
> > + /* Vector boolean types can have padding, verify we are
> > + dealing with the same number of elements, aka the precision of the types.
> > + For example, In most architecture the precision_size of vbool*_t
> > + types are caculated like below:
> > + precision_size = type_size * 8
> > +
> > + Unfortunately, the RISC-V will adjust the precision_size for the
> > + vbool*_t in order to align the ISA as below:
> > + type_size = [1, 1, 1, 1, 2, 4, 8]
> > + precision_size = [1, 2, 4, 8, 16, 32, 64]
> > +
> > + Then the precision_size of RISC-V vbool*_t will not be the
> > + multiple of the type_size. We take care of this case consolidated here. */
> > + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> > + TYPE_VECTOR_SUBPARTS (vr2->type))) return false;
> > + }
> >
> > i = 0;
> > j = 0;
> >
>
> --
> Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
> SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461
> Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal
[not found] <Message-Id: <20230329075222.2888608-1-pan2.li@intel.com>
@ 2023-04-25 14:29 ` pan2.li
2023-04-26 3:29 ` Kito Cheng
0 siblings, 1 reply; 15+ messages in thread
From: pan2.li @ 2023-04-25 14:29 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
In most architecture the precision_size of vbool*_t types are caculated
like as the multiple of the type size. For example:
precision_size = type_size * 8 (aka, bit count per bytes).
Unfortunately, some architecture like RISC-V will adjust the
precision_size
for the vbool*_t in order to align the ISA. For example as below.
type_size = [1, 1, 1, 1, 2, 4, 8]
precision_size = [1, 2, 4, 8, 16, 32, 64]
Then the precision_size of RISC-V vbool*_t will not be the multiple of
the
type_size. This PATCH try to enrich this case when comparing the
vn_reference.
Given we have the below code:
void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict
out) {
vbool8_t v1 = *(vbool8_t*)in;
vbool16_t v2 = *(vbool16_t*)in;
*(vbool8_t*)(out + 100) = v1;
*(vbool16_t*)(out + 200) = v2;
}
Before this PATCH:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m1,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf2,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After this PATCH:
addi a3,a1,100
vsetvli a4,zero,e8,m1,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf2,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
PR 109272
gcc/ChangeLog:
* tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
check for vn_reference equal.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-4.c: Update test check
condition.
* gcc.target/riscv/rvv/base/pr108185-5.c: Likewise.
* gcc.target/riscv/rvv/base/pr108185-6.c: Likewise.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 6e4d1cb1e44..321cd5c818e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 9fc659d2402..575a7842cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 98275e5267d..95a11d37016 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 94b793e1caf..94d6163e6ae 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
&& (TYPE_PRECISION (vr2->type)
!= TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
return false;
+ else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
+ && VECTOR_BOOLEAN_TYPE_P (vr2->type))
+ {
+ /* Vector boolean types can have padding, verify we are dealing with
+ the same number of elements, aka the precision of the types.
+ For example, In most architecture the precision_size of vbool*_t
+ types are caculated like below:
+ precision_size = type_size * 8
+
+ Unfortunately, the RISC-V will adjust the precision_size for the
+ vbool*_t in order to align the ISA as below:
+ type_size = [1, 1, 1, 1, 2, 4, 8]
+ precision_size = [1, 2, 4, 8, 16, 32, 64]
+
+ Then the precision_size of RISC-V vbool*_t will not be the multiple
+ of the type_size. We take care of this case consolidated here. */
+ if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
+ TYPE_VECTOR_SUBPARTS (vr2->type)))
+ return false;
+ }
i = 0;
j = 0;
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
2023-04-25 14:10 ` Li, Pan2
@ 2023-04-25 14:31 ` Li, Pan2
0 siblings, 0 replies; 15+ messages in thread
From: Li, Pan2 @ 2023-04-25 14:31 UTC (permalink / raw)
To: Kito Cheng; +Cc: kito.cheng, gcc-patches, Wang, Yanzhang, juzhe.zhong
Thanks for patient, update the PATCH v3 as below link.
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616686.html
Pan
-----Original Message-----
From: Li, Pan2
Sent: Tuesday, April 25, 2023 10:10 PM
To: Kito Cheng <kito.cheng@gmail.com>
Cc: kito.cheng@sifive.com; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; juzhe.zhong@rivai.ai
Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Oh, I see. This PATCH month drafted ago and missed that part. Sorry for inconvenient and will update it ASAP.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Tuesday, April 25, 2023 10:05 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: kito.cheng@sifive.com; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; juzhe.zhong@rivai.ai
Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
Plz write description for every item in changelog, otherwise the gcc git hook will reject this patch.
remote: *** The following commit was rejected by your hooks.commit-extra-checker script (status: 1)
remote: *** commit: 2777f46a58af65be380a2f44bf5cdf93e2d11886
remote: *** ChangeLog format failed:
remote: *** ERR: missing description of a change: " *
tree-ssa-sccvn.cc (vn_reference_eq):"
remote: ***
remote: *** Please see: https://gcc.gnu.org/codingconventions.html#ChangeLogs
remote: ***
remote: error: hook declined to update refs/heads/master
On Mon, Apr 24, 2023 at 7:14 PM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Hi,
>
> Just synced this patch with upstream, and passed the X86 bootstrap and regression test already.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Thursday, April 20, 2023 9:57 PM
> To: kito.cheng@sifive.com
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>;
> juzhe.zhong@rivai.ai
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Hi Kito,
>
> There is one patch reviewed already and I suppose it will be ok after GCC 14 open. Could you please help to double check about it?
>
> Pann
>
> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org>
> On Behalf Of Li, Pan2 via Gcc-patches
> Sent: Wednesday, March 29, 2023 6:39 PM
> To: juzhe.zhong@rivai.ai; rguenther <rguenther@suse.de>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: RE: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Cool. Thank you all for this, have a nice day!
>
> Pan
>
> From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> Sent: Wednesday, March 29, 2023 5:35 PM
> To: rguenther <rguenther@suse.de>; Li, Pan2 <pan2.li@intel.com>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Kito.cheng
> <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
>
> Thanks Richard && Pan.
>
> Pan has passed the bootstrap and I will merge this patch when GCC 14 is open (I have write access now).
>
> ________________________________
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
>
> From: Richard Biener<mailto:rguenther@suse.de>
> Date: 2023-03-29 17:24
> To: pan2.li<mailto:pan2.li@intel.com>
> CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>;
> juzhe.zhong<mailto:juzhe.zhong@rivai.ai>;
> kito.cheng<mailto:kito.cheng@sifive.com>;
> yanzhang.wang<mailto:yanzhang.wang@intel.com>
> Subject: Re: [PATCH v2] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal.
> On Wed, 29 Mar 2023, pan2.li@intel.com<mailto:pan2.li@intel.com> wrote:
>
> > From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> >
> > In most architecture the precision_size of vbool*_t types are
> > caculated like as the multiple of the type size. For example:
> > precision_size = type_size * 8 (aka, bit count per bytes).
> >
> > Unfortunately, some architecture like RISC-V will adjust the
> > precision_size for the vbool*_t in order to align the ISA. For example as below.
> > type_size = [1, 1, 1, 1, 2, 4, 8]
> > precision_size = [1, 2, 4, 8, 16, 32, 64]
> >
> > Then the precision_size of RISC-V vbool*_t will not be the multiple
> > of the type_size. This PATCH try to enrich this case when comparing the vn_reference.
> >
> > Given we have the below code:
> > void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) {
> > vbool8_t v1 = *(vbool8_t*)in;
> > vbool16_t v2 = *(vbool16_t*)in;
> >
> > *(vbool8_t*)(out + 100) = v1;
> > *(vbool16_t*)(out + 200) = v2;
> > }
> >
> > Before this PATCH:
> > csrr t0,vlenb
> > slli t1,t0,1
> > csrr a3,vlenb
> > sub sp,sp,t1
> > slli a4,a3,1
> > add a4,a4,sp
> > addi a2,a1,100
> > vsetvli a5,zero,e8,m1,ta,ma
> > sub a3,a4,a3
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a2)
> > vsm.v v24,0(a3)
> > addi a1,a1,200
> > csrr t0,vlenb
> > vsetvli a4,zero,e8,mf2,ta,ma
> > slli t1,t0,1
> > vlm.v v24,0(a3)
> > vsm.v v24,0(a1)
> > add sp,sp,t1
> > jr ra
> >
> > After this PATCH:
> > addi a3,a1,100
> > vsetvli a4,zero,e8,m1,ta,ma
> > addi a1,a1,200
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a3)
> > vsetvli a5,zero,e8,mf2,ta,ma
> > vlm.v v24,0(a0)
> > vsm.v v24,0(a1)
> > ret
>
> OK if this passes bootstrap / regtest.
>
> Thanks,
> Richard.
>
> > PR 109272
> >
> > gcc/ChangeLog:
> >
> > * tree-ssa-sccvn.cc (vn_reference_eq):
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/pr108185-4.c:
> > * gcc.target/riscv/rvv/base/pr108185-5.c:
> > * gcc.target/riscv/rvv/base/pr108185-6.c:
> >
> > Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
> > ---
> > .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> > .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> > gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> > 4 files changed, 23 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > index ea3c360d756..e70284fada8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> > @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > index 9fc659d2402..575a7842cdf 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> > @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > index 98275e5267d..95a11d37016 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> > @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in,
> > int8_t * restrict out) {
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> > /* { dg-final { scan-assembler-times
> > {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > -/* { dg-final { scan-assembler-times
> > {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> > +/* { dg-final { scan-assembler-times
> > +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> > diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index
> > 6b8d38b270c..567df3cb2c6 100644
> > --- a/gcc/tree-ssa-sccvn.cc
> > +++ b/gcc/tree-ssa-sccvn.cc
> > @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
> > && (TYPE_PRECISION (vr2->type)
> > != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> > return false;
> > + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> > + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> > + {
> > + /* Vector boolean types can have padding, verify we are
> > + dealing with the same number of elements, aka the precision of the types.
> > + For example, In most architecture the precision_size of vbool*_t
> > + types are caculated like below:
> > + precision_size = type_size * 8
> > +
> > + Unfortunately, the RISC-V will adjust the precision_size for the
> > + vbool*_t in order to align the ISA as below:
> > + type_size = [1, 1, 1, 1, 2, 4, 8]
> > + precision_size = [1, 2, 4, 8, 16, 32, 64]
> > +
> > + Then the precision_size of RISC-V vbool*_t will not be the
> > + multiple of the type_size. We take care of this case consolidated here. */
> > + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> > + TYPE_VECTOR_SUBPARTS (vr2->type))) return false;
> > + }
> >
> > i = 0;
> > j = 0;
> >
>
> --
> Richard Biener <rguenther@suse.de<mailto:rguenther@suse.de>>
> SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461
> Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald,
> Boudien Moerman; HRB 36809 (AG Nuernberg)
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal
2023-04-25 14:29 ` [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal pan2.li
@ 2023-04-26 3:29 ` Kito Cheng
2023-04-26 3:33 ` Li, Pan2
0 siblings, 1 reply; 15+ messages in thread
From: Kito Cheng @ 2023-04-26 3:29 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, yanzhang.wang
[-- Attachment #1: Type: text/plain, Size: 6571 bytes --]
Committed, thanks!
On Tue, Apr 25, 2023 at 10:29 PM <pan2.li@intel.com> wrote:
> From: Pan Li <pan2.li@intel.com>
>
> In most architecture the precision_size of vbool*_t types are caculated
> like as the multiple of the type size. For example:
> precision_size = type_size * 8 (aka, bit count per bytes).
>
> Unfortunately, some architecture like RISC-V will adjust the
> precision_size
> for the vbool*_t in order to align the ISA. For example as below.
> type_size = [1, 1, 1, 1, 2, 4, 8]
> precision_size = [1, 2, 4, 8, 16, 32, 64]
>
> Then the precision_size of RISC-V vbool*_t will not be the multiple of
> the
> type_size. This PATCH try to enrich this case when comparing the
> vn_reference.
>
> Given we have the below code:
> void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict
> out) {
> vbool8_t v1 = *(vbool8_t*)in;
> vbool16_t v2 = *(vbool16_t*)in;
>
> *(vbool8_t*)(out + 100) = v1;
> *(vbool16_t*)(out + 200) = v2;
> }
>
> Before this PATCH:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m1,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf2,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After this PATCH:
> addi a3,a1,100
> vsetvli a4,zero,e8,m1,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf2,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
>
> PR 109272
>
> gcc/ChangeLog:
>
> * tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
> check for vn_reference equal.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-4.c: Update test check
> condition.
> * gcc.target/riscv/rvv/base/pr108185-5.c: Likewise.
> * gcc.target/riscv/rvv/base/pr108185-6.c: Likewise.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
> gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> index 6e4d1cb1e44..321cd5c818e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
> @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t *
> restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
> +/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> index 9fc659d2402..575a7842cdf 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
> @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t *
> restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
> +/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> index 98275e5267d..95a11d37016 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
> @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t *
> restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
> +/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
> index 94b793e1caf..94d6163e6ae 100644
> --- a/gcc/tree-ssa-sccvn.cc
> +++ b/gcc/tree-ssa-sccvn.cc
> @@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1,
> const_vn_reference_t const vr2)
> && (TYPE_PRECISION (vr2->type)
> != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
> return false;
> + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
> + && VECTOR_BOOLEAN_TYPE_P (vr2->type))
> + {
> + /* Vector boolean types can have padding, verify we are dealing with
> + the same number of elements, aka the precision of the types.
> + For example, In most architecture the precision_size of vbool*_t
> + types are caculated like below:
> + precision_size = type_size * 8
> +
> + Unfortunately, the RISC-V will adjust the precision_size for the
> + vbool*_t in order to align the ISA as below:
> + type_size = [1, 1, 1, 1, 2, 4, 8]
> + precision_size = [1, 2, 4, 8, 16, 32, 64]
> +
> + Then the precision_size of RISC-V vbool*_t will not be the
> multiple
> + of the type_size. We take care of this case consolidated here.
> */
> + if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
> + TYPE_VECTOR_SUBPARTS (vr2->type)))
> + return false;
> + }
>
> i = 0;
> j = 0;
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal
2023-04-26 3:29 ` Kito Cheng
@ 2023-04-26 3:33 ` Li, Pan2
0 siblings, 0 replies; 15+ messages in thread
From: Li, Pan2 @ 2023-04-26 3:33 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 6658 bytes --]
Thanks a lot, kito, will pay more attention for the changelogs.
Pan
From: Kito Cheng <kito.cheng@sifive.com>
Sent: Wednesday, April 26, 2023 11:30 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal
Committed, thanks!
On Tue, Apr 25, 2023 at 10:29 PM <pan2.li@intel.com<mailto:pan2.li@intel.com>> wrote:
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
In most architecture the precision_size of vbool*_t types are caculated
like as the multiple of the type size. For example:
precision_size = type_size * 8 (aka, bit count per bytes).
Unfortunately, some architecture like RISC-V will adjust the
precision_size
for the vbool*_t in order to align the ISA. For example as below.
type_size = [1, 1, 1, 1, 2, 4, 8]
precision_size = [1, 2, 4, 8, 16, 32, 64]
Then the precision_size of RISC-V vbool*_t will not be the multiple of
the
type_size. This PATCH try to enrich this case when comparing the
vn_reference.
Given we have the below code:
void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict
out) {
vbool8_t v1 = *(vbool8_t*)in;
vbool16_t v2 = *(vbool16_t*)in;
*(vbool8_t*)(out + 100) = v1;
*(vbool16_t*)(out + 200) = v2;
}
Before this PATCH:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m1,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf2,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After this PATCH:
addi a3,a1,100
vsetvli a4,zero,e8,m1,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf2,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
PR 109272
gcc/ChangeLog:
* tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
check for vn_reference equal.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-4.c: Update test check
condition.
* gcc.target/riscv/rvv/base/pr108185-5.c: Likewise.
* gcc.target/riscv/rvv/base/pr108185-6.c: Likewise.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
.../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +-
gcc/tree-ssa-sccvn.cc | 20 +++++++++++++++++++
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 6e4d1cb1e44..321cd5c818e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 9fc659d2402..575a7842cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 98275e5267d..95a11d37016 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 94b793e1caf..94d6163e6ae 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -799,6 +799,26 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
&& (TYPE_PRECISION (vr2->type)
!= TREE_INT_CST_LOW (TYPE_SIZE (vr2->type))))
return false;
+ else if (VECTOR_BOOLEAN_TYPE_P (vr1->type)
+ && VECTOR_BOOLEAN_TYPE_P (vr2->type))
+ {
+ /* Vector boolean types can have padding, verify we are dealing with
+ the same number of elements, aka the precision of the types.
+ For example, In most architecture the precision_size of vbool*_t
+ types are caculated like below:
+ precision_size = type_size * 8
+
+ Unfortunately, the RISC-V will adjust the precision_size for the
+ vbool*_t in order to align the ISA as below:
+ type_size = [1, 1, 1, 1, 2, 4, 8]
+ precision_size = [1, 2, 4, 8, 16, 32, 64]
+
+ Then the precision_size of RISC-V vbool*_t will not be the multiple
+ of the type_size. We take care of this case consolidated here. */
+ if (maybe_ne (TYPE_VECTOR_SUBPARTS (vr1->type),
+ TYPE_VECTOR_SUBPARTS (vr2->type)))
+ return false;
+ }
i = 0;
j = 0;
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-04-26 3:33 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <Message-Id: <20230329075222.2888608-1-pan2.li@intel.com>
2023-04-25 14:29 ` [PATCH v3] RISC-V: Bugfix for RVV vbool*_t vn_reference_equal pan2.li
2023-04-26 3:29 ` Kito Cheng
2023-04-26 3:33 ` Li, Pan2
2023-03-29 7:52 [PATCH] [RISC-V]: " pan2.li
2023-03-29 8:10 ` Richard Biener
2023-03-29 8:56 ` Li, Pan2
2023-03-29 8:53 ` [PATCH v2] RISC-V: " pan2.li
2023-03-29 9:24 ` Richard Biener
2023-03-29 9:35 ` juzhe.zhong
2023-03-29 10:38 ` Li, Pan2
2023-04-20 13:56 ` Li, Pan2
2023-04-24 11:13 ` Li, Pan2
2023-04-25 14:05 ` Kito Cheng
2023-04-25 14:10 ` Li, Pan2
2023-04-25 14:31 ` Li, Pan2
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