* [PATCH] loongarch: fix mulsidi3_64bit instruction
@ 2022-07-08 13:18 Xi Ruoyao
2022-07-08 13:31 ` [PATCH v2] " Xi Ruoyao
0 siblings, 1 reply; 5+ messages in thread
From: Xi Ruoyao @ 2022-07-08 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: Lulu Cheng, Chenghua Xu, Wang Xuerui
I think this should be obvious. Ok for trunk and gcc-12 branch?
(Note: this bug really amazed me. It's just a simple typo and all of us
failed to spot it reviewing the LoongArch port. Incredibly, it can be
reproduced with such a simple test case (in the patch) but did not blow
the entire system up. I didn't see anything abnormal until it blown up
two UBSan test cases when I tried to port UBSan for LoongArch.)
-- >8 --
(mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
"mulw.d.w", not "mul.d".
gcc/ChangeLog:
* config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
instead of mul.d.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/mul-1.c: New test.
* gcc.target/loongarch/mul-2.c: New test.
---
gcc/config/loongarch/loongarch.md | 2 +-
gcc/testsuite/gcc.target/loongarch/mul-1.c | 20 ++++++++++++++++++++
gcc/testsuite/gcc.target/loongarch/mul-2.c | 10 ++++++++++
3 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-2.c
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..8f8412fba84 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit"
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_64BIT"
- "mul.d\t%0,%1,%2"
+ "mulw.d.w\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
diff --git a/gcc/testsuite/gcc.target/loongarch/mul-1.c b/gcc/testsuite/gcc.target/loongarch/mul-1.c
new file mode 100644
index 00000000000..8b6800804fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mul-1.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+
+typedef __INT64_TYPE__ int64_t;
+typedef __INT32_TYPE__ int32_t;
+
+/* f() was misoptimized to a single "mul.d" instruction on LA64. */
+__attribute__((noipa, noinline)) int64_t
+f(int64_t a, int64_t b)
+{
+ return (int64_t)(int32_t)a * (int64_t)(int32_t)b;
+}
+
+int
+main()
+{
+ int64_t a = 0x1145140000000001;
+ int64_t b = 0x1919810000000001;
+ if (f(a, b) != 1)
+ __builtin_abort();
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mul-2.c b/gcc/testsuite/gcc.target/loongarch/mul-2.c
new file mode 100644
index 00000000000..a9a713210df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mul-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "mulw.d.w\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+/* This should be optimized to mulw.d.w for LA64. */
+__attribute__((noipa, noinline)) long
+f(long a, long b)
+{
+ return (long)(int)a * (long)(int)b;
+}
--
2.37.0
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2] loongarch: fix mulsidi3_64bit instruction
2022-07-08 13:18 [PATCH] loongarch: fix mulsidi3_64bit instruction Xi Ruoyao
@ 2022-07-08 13:31 ` Xi Ruoyao
2022-07-09 2:56 ` [PATCH v3] " Xi Ruoyao
0 siblings, 1 reply; 5+ messages in thread
From: Xi Ruoyao @ 2022-07-08 13:31 UTC (permalink / raw)
To: gcc-patches; +Cc: Chenghua Xu, Lulu Cheng, Wang Xuerui
v2: Move one portable test to gcc.c-torture so it will be tested with
all optimization levels. And it might be helpful if the engineer of the
next GCC port makes a similar typo :).
-- >8 --
(mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
"mulw.d.w", not "mul.d".
gcc/ChangeLog:
* config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
instead of mul.d.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/mulw_d_w.c: New test.
* gcc.c-torture/execute/mul-sext.c: New test.
---
gcc/config/loongarch/loongarch.md | 2 +-
.../gcc.c-torture/execute/mul-sext.c | 20 +++++++++++++++++++
gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 10 ++++++++++
3 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.c-torture/execute/mul-sext.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..8f8412fba84 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit"
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_64BIT"
- "mul.d\t%0,%1,%2"
+ "mulw.d.w\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
diff --git a/gcc/testsuite/gcc.c-torture/execute/mul-sext.c b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
new file mode 100644
index 00000000000..8b6800804fb
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+
+typedef __INT64_TYPE__ int64_t;
+typedef __INT32_TYPE__ int32_t;
+
+/* f() was misoptimized to a single "mul.d" instruction on LA64. */
+__attribute__((noipa, noinline)) int64_t
+f(int64_t a, int64_t b)
+{
+ return (int64_t)(int32_t)a * (int64_t)(int32_t)b;
+}
+
+int
+main()
+{
+ int64_t a = 0x1145140000000001;
+ int64_t b = 0x1919810000000001;
+ if (f(a, b) != 1)
+ __builtin_abort();
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
new file mode 100644
index 00000000000..a9a713210df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "mulw.d.w\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+/* This should be optimized to mulw.d.w for LA64. */
+__attribute__((noipa, noinline)) long
+f(long a, long b)
+{
+ return (long)(int)a * (long)(int)b;
+}
--
2.37.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v3] loongarch: fix mulsidi3_64bit instruction
2022-07-08 13:31 ` [PATCH v2] " Xi Ruoyao
@ 2022-07-09 2:56 ` Xi Ruoyao
2022-07-10 1:45 ` Lulu Cheng
0 siblings, 1 reply; 5+ messages in thread
From: Xi Ruoyao @ 2022-07-09 2:56 UTC (permalink / raw)
To: gcc-patches; +Cc: Chenghua Xu, Lulu Cheng, Wang Xuerui
v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's because
multiplication is Abelian and the compiler may switch the order of
operands in the future.
-- >8 --
(mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
"mulw.d.w", not "mul.d".
gcc/ChangeLog:
* config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
instead of mul.d.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/mulw_d_w.c: New test.
* gcc.c-torture/execute/mul-sext.c: New test.
---
gcc/config/loongarch/loongarch.md | 2 +-
.../gcc.c-torture/execute/mul-sext.c | 20 +++++++++++++++++++
gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 10 ++++++++++
3 files changed, 31 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.c-torture/execute/mul-sext.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..8f8412fba84 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit"
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
"TARGET_64BIT"
- "mul.d\t%0,%1,%2"
+ "mulw.d.w\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
diff --git a/gcc/testsuite/gcc.c-torture/execute/mul-sext.c b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
new file mode 100644
index 00000000000..8b6800804fb
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+
+typedef __INT64_TYPE__ int64_t;
+typedef __INT32_TYPE__ int32_t;
+
+/* f() was misoptimized to a single "mul.d" instruction on LA64. */
+__attribute__((noipa, noinline)) int64_t
+f(int64_t a, int64_t b)
+{
+ return (int64_t)(int32_t)a * (int64_t)(int32_t)b;
+}
+
+int
+main()
+{
+ int64_t a = 0x1145140000000001;
+ int64_t b = 0x1919810000000001;
+ if (f(a, b) != 1)
+ __builtin_abort();
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
new file mode 100644
index 00000000000..4ab7df8836b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "mulw.d.w" } } */
+
+/* This should be optimized to mulw.d.w for LA64. */
+__attribute__((noipa, noinline)) long
+f(long a, long b)
+{
+ return (long)(int)a * (long)(int)b;
+}
--
2.37.0
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v3] loongarch: fix mulsidi3_64bit instruction
2022-07-09 2:56 ` [PATCH v3] " Xi Ruoyao
@ 2022-07-10 1:45 ` Lulu Cheng
2022-07-10 3:43 ` Xi Ruoyao
0 siblings, 1 reply; 5+ messages in thread
From: Lulu Cheng @ 2022-07-10 1:45 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches; +Cc: Chenghua Xu, Wang Xuerui
在 2022/7/9 上午10:56, Xi Ruoyao 写道:
> v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's because
> multiplication is Abelian and the compiler may switch the order of
> operands in the future.
> -- >8 --
>
> (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
> "mulw.d.w", not "mul.d".
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
> instead of mul.d.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/loongarch/mulw_d_w.c: New test.
> * gcc.c-torture/execute/mul-sext.c: New test.
> ---
I think there is no problem with this modification.
Thankes!
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] loongarch: fix mulsidi3_64bit instruction
2022-07-10 1:45 ` Lulu Cheng
@ 2022-07-10 3:43 ` Xi Ruoyao
0 siblings, 0 replies; 5+ messages in thread
From: Xi Ruoyao @ 2022-07-10 3:43 UTC (permalink / raw)
To: Lulu Cheng, gcc-patches; +Cc: Chenghua Xu, Wang Xuerui
On Sun, 2022-07-10 at 09:45 +0800, Lulu Cheng wrote:
>
> 在 2022/7/9 上午10:56, Xi Ruoyao 写道:
> > v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's
> > because
> > multiplication is Abelian and the compiler may switch the order of
> > operands in the future.
> > -- >8 --
> >
> > (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
> > "mulw.d.w", not "mul.d".
> >
> > gcc/ChangeLog:
> >
> > * config/loongarch/loongarch.md (mulsidi3_64bit): Use
> > mulw.d.w
> > instead of mul.d.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/loongarch/mulw_d_w.c: New test.
> > * gcc.c-torture/execute/mul-sext.c: New test.
> > ---
>
> I think there is no problem with this modification.
>
> Thankes!
>
Pushed r13-1591 and r12-8562.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 5+ messages in thread
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2022-07-08 13:18 [PATCH] loongarch: fix mulsidi3_64bit instruction Xi Ruoyao
2022-07-08 13:31 ` [PATCH v2] " Xi Ruoyao
2022-07-09 2:56 ` [PATCH v3] " Xi Ruoyao
2022-07-10 1:45 ` Lulu Cheng
2022-07-10 3:43 ` Xi Ruoyao
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