* [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache ()
@ 2022-10-22 8:25 Tomas Vanek
2022-10-25 13:22 ` Luis Machado
0 siblings, 1 reply; 4+ messages in thread
From: Tomas Vanek @ 2022-10-22 8:25 UTC (permalink / raw)
To: gdb-patches
Arm v8-M Architecture Reference Manual,
D1.2.141 IPSR, Interrupt Program Status Register reads
"Exception, bits [8:0]"
9 bits, not 8! It is uncommon but true!
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
---
gdb/arm-tdep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index b397ca3..923447a 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
}
ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
- if ((xpsr & 0xff) != 0)
+ if ((xpsr & 0x1ff) != 0)
/* Handler mode: This is the mode that exceptions are handled in. */
arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
else
--
1.9.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache ()
2022-10-22 8:25 [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache () Tomas Vanek
@ 2022-10-25 13:22 ` Luis Machado
2022-10-25 15:35 ` Tomas Vanek
2022-10-26 12:04 ` Luis Machado
0 siblings, 2 replies; 4+ messages in thread
From: Luis Machado @ 2022-10-25 13:22 UTC (permalink / raw)
To: Tomas Vanek, gdb-patches
Hi Tomas,
On 10/22/22 09:25, Tomas Vanek wrote:
> Arm v8-M Architecture Reference Manual,
> D1.2.141 IPSR, Interrupt Program Status Register reads
> "Exception, bits [8:0]"
>
> 9 bits, not 8! It is uncommon but true!
>
> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
> ---
> gdb/arm-tdep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index b397ca3..923447a 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
> }
>
> ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
> - if ((xpsr & 0xff) != 0)
> + if ((xpsr & 0x1ff) != 0)
> /* Handler mode: This is the mode that exceptions are handled in. */
> arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
> else
Good catch. This LGTM.
I suppose you need us to push this patch on your behalf?
One thing that would be nice to do is to have a flags/fields type for XPSR, which
would then display things in a nicer way to the user. Something like CPSR for a-profile.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache ()
2022-10-25 13:22 ` Luis Machado
@ 2022-10-25 15:35 ` Tomas Vanek
2022-10-26 12:04 ` Luis Machado
1 sibling, 0 replies; 4+ messages in thread
From: Tomas Vanek @ 2022-10-25 15:35 UTC (permalink / raw)
To: Luis Machado, gdb-patches
Hi Luis,
On 25/10/2022 15:22, Luis Machado wrote:
> Hi Tomas,
>
> On 10/22/22 09:25, Tomas Vanek wrote:
>> Arm v8-M Architecture Reference Manual,
>> D1.2.141 IPSR, Interrupt Program Status Register reads
>> "Exception, bits [8:0]"
>>
>> 9 bits, not 8! It is uncommon but true!
>>
>> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
>> ---
>> gdb/arm-tdep.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index b397ca3..923447a 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
>> }
>> ULONGEST xpsr = get_frame_register_unsigned (this_frame,
>> ARM_PS_REGNUM);
>> - if ((xpsr & 0xff) != 0)
>> + if ((xpsr & 0x1ff) != 0)
>> /* Handler mode: This is the mode that exceptions are handled
>> in. */
>> arm_cache_switch_prev_sp (cache, tdep,
>> tdep->m_profile_msp_s_regnum);
>> else
>
> Good catch. This LGTM.
>
> I suppose you need us to push this patch on your behalf?
>
Yes, please push all my patches as they are ready.
Thanks
Tomas
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache ()
2022-10-25 13:22 ` Luis Machado
2022-10-25 15:35 ` Tomas Vanek
@ 2022-10-26 12:04 ` Luis Machado
1 sibling, 0 replies; 4+ messages in thread
From: Luis Machado @ 2022-10-26 12:04 UTC (permalink / raw)
To: Tomas Vanek, gdb-patches
On 10/25/22 14:22, Luis Machado via Gdb-patches wrote:
> Hi Tomas,
>
> On 10/22/22 09:25, Tomas Vanek wrote:
>> Arm v8-M Architecture Reference Manual,
>> D1.2.141 IPSR, Interrupt Program Status Register reads
>> "Exception, bits [8:0]"
>>
>> 9 bits, not 8! It is uncommon but true!
>>
>> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
>> ---
>> gdb/arm-tdep.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index b397ca3..923447a 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
>> }
>> ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
>> - if ((xpsr & 0xff) != 0)
>> + if ((xpsr & 0x1ff) != 0)
>> /* Handler mode: This is the mode that exceptions are handled in. */
>> arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
>> else
>
> Good catch. This LGTM.
>
> I suppose you need us to push this patch on your behalf?
>
> One thing that would be nice to do is to have a flags/fields type for XPSR, which
> would then display things in a nicer way to the user. Something like CPSR for a-profile.
Pushed.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-10-22 8:25 [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache () Tomas Vanek
2022-10-25 13:22 ` Luis Machado
2022-10-25 15:35 ` Tomas Vanek
2022-10-26 12:04 ` Luis Machado
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